ARM: mxs: Add gpio support
MXS-based SoCs implement gpio support in block PINCTRL. Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
This commit is contained in:
Shawn Guo
Uwe Kleine-König
Родитель
4e472096fa
Коммит
fba311fcf0
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/*
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* MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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*
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* Based on code from Freescale,
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* Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/gpio.h>
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#include <mach/mx23.h>
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#include <mach/mx28.h>
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#include <asm-generic/bug.h>
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#include "gpio.h"
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static struct mxs_gpio_port *mxs_gpio_ports;
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static int gpio_table_size;
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#define PINCTRL_DOUT(n) ((cpu_is_mx23() ? 0x0500 : 0x0700) + (n) * 0x10)
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#define PINCTRL_DIN(n) ((cpu_is_mx23() ? 0x0600 : 0x0900) + (n) * 0x10)
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#define PINCTRL_DOE(n) ((cpu_is_mx23() ? 0x0700 : 0x0b00) + (n) * 0x10)
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#define PINCTRL_PIN2IRQ(n) ((cpu_is_mx23() ? 0x0800 : 0x1000) + (n) * 0x10)
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#define PINCTRL_IRQEN(n) ((cpu_is_mx23() ? 0x0900 : 0x1100) + (n) * 0x10)
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#define PINCTRL_IRQLEV(n) ((cpu_is_mx23() ? 0x0a00 : 0x1200) + (n) * 0x10)
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#define PINCTRL_IRQPOL(n) ((cpu_is_mx23() ? 0x0b00 : 0x1300) + (n) * 0x10)
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#define PINCTRL_IRQSTAT(n) ((cpu_is_mx23() ? 0x0c00 : 0x1400) + (n) * 0x10)
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#define GPIO_INT_FALL_EDGE 0x0
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#define GPIO_INT_LOW_LEV 0x1
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#define GPIO_INT_RISE_EDGE 0x2
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#define GPIO_INT_HIGH_LEV 0x3
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#define GPIO_INT_LEV_MASK (1 << 0)
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#define GPIO_INT_POL_MASK (1 << 1)
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/* Note: This driver assumes 32 GPIOs are handled in one register */
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static void clear_gpio_irqstatus(struct mxs_gpio_port *port, u32 index)
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{
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__mxs_clrl(1 << index, port->base + PINCTRL_IRQSTAT(port->id));
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}
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static void set_gpio_irqenable(struct mxs_gpio_port *port, u32 index,
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int enable)
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{
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if (enable) {
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__mxs_setl(1 << index, port->base + PINCTRL_IRQEN(port->id));
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__mxs_setl(1 << index, port->base + PINCTRL_PIN2IRQ(port->id));
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} else {
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__mxs_clrl(1 << index, port->base + PINCTRL_IRQEN(port->id));
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}
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}
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static void mxs_gpio_ack_irq(u32 irq)
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{
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u32 gpio = irq_to_gpio(irq);
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clear_gpio_irqstatus(&mxs_gpio_ports[gpio / 32], gpio & 0x1f);
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}
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static void mxs_gpio_mask_irq(u32 irq)
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{
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u32 gpio = irq_to_gpio(irq);
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set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 0);
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}
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static void mxs_gpio_unmask_irq(u32 irq)
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{
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u32 gpio = irq_to_gpio(irq);
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set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 1);
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}
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static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset);
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static int mxs_gpio_set_irq_type(u32 irq, u32 type)
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{
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u32 gpio = irq_to_gpio(irq);
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u32 pin_mask = 1 << (gpio & 31);
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struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32];
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void __iomem *pin_addr;
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int edge;
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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edge = GPIO_INT_RISE_EDGE;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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edge = GPIO_INT_FALL_EDGE;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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edge = GPIO_INT_LOW_LEV;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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edge = GPIO_INT_HIGH_LEV;
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break;
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default:
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return -EINVAL;
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}
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/* set level or edge */
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pin_addr = port->base + PINCTRL_IRQLEV(port->id);
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if (edge & GPIO_INT_LEV_MASK)
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__mxs_setl(pin_mask, pin_addr);
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else
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__mxs_clrl(pin_mask, pin_addr);
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/* set polarity */
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pin_addr = port->base + PINCTRL_IRQPOL(port->id);
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if (edge & GPIO_INT_POL_MASK)
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__mxs_setl(pin_mask, pin_addr);
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else
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__mxs_clrl(pin_mask, pin_addr);
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clear_gpio_irqstatus(port, gpio & 0x1f);
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return 0;
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}
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/* MXS has one interrupt *per* gpio port */
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static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
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{
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u32 irq_stat;
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struct mxs_gpio_port *port = (struct mxs_gpio_port *)get_irq_data(irq);
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u32 gpio_irq_no_base = port->virtual_irq_start;
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irq_stat = __raw_readl(port->base + PINCTRL_IRQSTAT(port->id)) &
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__raw_readl(port->base + PINCTRL_IRQEN(port->id));
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while (irq_stat != 0) {
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int irqoffset = fls(irq_stat) - 1;
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generic_handle_irq(gpio_irq_no_base + irqoffset);
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irq_stat &= ~(1 << irqoffset);
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}
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}
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/*
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* Set interrupt number "irq" in the GPIO as a wake-up source.
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* While system is running, all registered GPIO interrupts need to have
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* wake-up enabled. When system is suspended, only selected GPIO interrupts
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* need to have wake-up enabled.
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* @param irq interrupt source number
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* @param enable enable as wake-up if equal to non-zero
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* @return This function returns 0 on success.
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*/
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static int mxs_gpio_set_wake_irq(u32 irq, u32 enable)
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{
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u32 gpio = irq_to_gpio(irq);
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u32 gpio_idx = gpio & 0x1f;
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struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32];
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if (enable) {
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if (port->irq_high && (gpio_idx >= 16))
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enable_irq_wake(port->irq_high);
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else
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enable_irq_wake(port->irq);
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} else {
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if (port->irq_high && (gpio_idx >= 16))
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disable_irq_wake(port->irq_high);
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else
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disable_irq_wake(port->irq);
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}
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return 0;
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}
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static struct irq_chip gpio_irq_chip = {
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.ack = mxs_gpio_ack_irq,
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.mask = mxs_gpio_mask_irq,
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.unmask = mxs_gpio_unmask_irq,
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.set_type = mxs_gpio_set_irq_type,
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.set_wake = mxs_gpio_set_wake_irq,
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};
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static void mxs_set_gpio_direction(struct gpio_chip *chip, unsigned offset,
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int dir)
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{
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struct mxs_gpio_port *port =
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container_of(chip, struct mxs_gpio_port, chip);
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void __iomem *pin_addr = port->base + PINCTRL_DOE(port->id);
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if (dir)
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__mxs_setl(1 << offset, pin_addr);
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else
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__mxs_clrl(1 << offset, pin_addr);
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}
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static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct mxs_gpio_port *port =
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container_of(chip, struct mxs_gpio_port, chip);
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return (__raw_readl(port->base + PINCTRL_DIN(port->id)) >> offset) & 1;
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}
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static void mxs_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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struct mxs_gpio_port *port =
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container_of(chip, struct mxs_gpio_port, chip);
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void __iomem *pin_addr = port->base + PINCTRL_DOUT(port->id);
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if (value)
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__mxs_setl(1 << offset, pin_addr);
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else
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__mxs_clrl(1 << offset, pin_addr);
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}
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static int mxs_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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struct mxs_gpio_port *port =
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container_of(chip, struct mxs_gpio_port, chip);
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return port->virtual_irq_start + offset;
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}
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static int mxs_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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mxs_set_gpio_direction(chip, offset, 0);
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return 0;
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}
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static int mxs_gpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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mxs_gpio_set(chip, offset, value);
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mxs_set_gpio_direction(chip, offset, 1);
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return 0;
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}
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int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt)
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{
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int i, j;
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/* save for local usage */
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mxs_gpio_ports = port;
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gpio_table_size = cnt;
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pr_info("MXS GPIO hardware\n");
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for (i = 0; i < cnt; i++) {
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/* disable the interrupt and clear the status */
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__raw_writel(0, port[i].base + PINCTRL_PIN2IRQ(i));
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__raw_writel(0, port[i].base + PINCTRL_IRQEN(i));
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/* clear address has to be used to clear IRQSTAT bits */
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__mxs_clrl(~0U, port[i].base + PINCTRL_IRQSTAT(i));
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for (j = port[i].virtual_irq_start;
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j < port[i].virtual_irq_start + 32; j++) {
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set_irq_chip(j, &gpio_irq_chip);
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set_irq_handler(j, handle_level_irq);
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set_irq_flags(j, IRQF_VALID);
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}
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/* setup one handler for each entry */
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set_irq_chained_handler(port[i].irq, mxs_gpio_irq_handler);
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set_irq_data(port[i].irq, &port[i]);
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/* register gpio chip */
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port[i].chip.direction_input = mxs_gpio_direction_input;
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port[i].chip.direction_output = mxs_gpio_direction_output;
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port[i].chip.get = mxs_gpio_get;
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port[i].chip.set = mxs_gpio_set;
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port[i].chip.to_irq = mxs_gpio_to_irq;
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port[i].chip.base = i * 32;
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port[i].chip.ngpio = 32;
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/* its a serious configuration bug when it fails */
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BUG_ON(gpiochip_add(&port[i].chip) < 0);
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}
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return 0;
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}
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#define DEFINE_MXS_GPIO_PORT(soc, _id) \
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{ \
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.chip.label = "gpio-" #_id, \
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.id = _id, \
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.irq = soc ## _INT_GPIO ## _id, \
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.base = soc ## _IO_ADDRESS( \
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soc ## _PINCTRL ## _BASE_ADDR), \
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.virtual_irq_start = MXS_GPIO_IRQ_START + (_id) * 32, \
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}
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#define DEFINE_REGISTER_FUNCTION(prefix) \
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int __init prefix ## _register_gpios(void) \
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{ \
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return mxs_gpio_init(prefix ## _gpio_ports, \
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ARRAY_SIZE(prefix ## _gpio_ports)); \
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}
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#ifdef CONFIG_SOC_IMX23
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static struct mxs_gpio_port mx23_gpio_ports[] = {
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DEFINE_MXS_GPIO_PORT(MX23, 0),
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DEFINE_MXS_GPIO_PORT(MX23, 1),
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DEFINE_MXS_GPIO_PORT(MX23, 2),
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};
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DEFINE_REGISTER_FUNCTION(mx23)
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#endif
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#ifdef CONFIG_SOC_IMX28
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static struct mxs_gpio_port mx28_gpio_ports[] = {
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DEFINE_MXS_GPIO_PORT(MX28, 0),
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DEFINE_MXS_GPIO_PORT(MX28, 1),
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DEFINE_MXS_GPIO_PORT(MX28, 2),
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DEFINE_MXS_GPIO_PORT(MX28, 3),
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DEFINE_MXS_GPIO_PORT(MX28, 4),
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};
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DEFINE_REGISTER_FUNCTION(mx28)
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#endif
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@ -0,0 +1,34 @@
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/*
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* Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
|
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* as published by the Free Software Foundation; either version 2
|
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* of the License, or (at your option) any later version.
|
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#ifndef __MXS_GPIO_H__
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#define __MXS_GPIO_H__
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struct mxs_gpio_port {
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void __iomem *base;
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int id;
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int irq;
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int irq_high;
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int virtual_irq_start;
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struct gpio_chip chip;
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};
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int mxs_gpio_init(struct mxs_gpio_port*, int);
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#endif /* __MXS_GPIO_H__ */
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@ -0,0 +1,35 @@
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/*
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* Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
|
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*/
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#ifndef __MACH_MXS_GPIO_H__
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#define __MACH_MXS_GPIO_H__
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#include <asm-generic/gpio.h>
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#define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr))
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/* use gpiolib dispatchers */
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#define gpio_get_value __gpio_get_value
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#define gpio_set_value __gpio_set_value
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#define gpio_cansleep __gpio_cansleep
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#define gpio_to_irq __gpio_to_irq
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#define irq_to_gpio(irq) ((irq) - MXS_GPIO_IRQ_START)
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#endif /* __MACH_MXS_GPIO_H__ */
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