Merge branch 'cpufreq/arm/linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm
Pull ARM cpufreq changes for v5.3 from Viresh Kumar: "This pull request contains: - Minor fixes for brcmstb driver (Florian). - New imx-cpufreq driver, its bindings and code around it (Leonard). - New Raspberry Pi driver (Nicolas). - Minor fix for s5pv210 driver (Pawel). - Minor cleanup for armada driver (YueHaibing)." * 'cpufreq/arm/linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm: cpufreq: s5pv210: Don't flood kernel log after cpufreq change cpufreq: add driver for Raspberry Pi cpufreq: Switch imx7d to imx-cpufreq-dt for speed grading cpufreq: imx-cpufreq-dt: Remove global platform match list cpufreq: brcmstb-avs-cpufreq: Fix types for voltage/frequency cpufreq: brcmstb-avs-cpufreq: Fix initial command check cpufreq: armada-37xx: Remove set but not used variable 'freq' cpufreq: imx-cpufreq-dt: Fix no OPPs available on unfused parts dt-bindings: imx-cpufreq-dt: Document opp-supported-hw usage cpufreq: Add imx-cpufreq-dt driver
This commit is contained in:
Rafael J. Wysocki
Коммит
fba7402017
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@ -0,0 +1,37 @@
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i.MX CPUFreq-DT OPP bindings
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================================
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Certain i.MX SoCs support different OPPs depending on the "market segment" and
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"speed grading" value which are written in fuses. These bits are combined with
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the opp-supported-hw values for each OPP to check if the OPP is allowed.
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Required properties:
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--------------------
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For each opp entry in 'operating-points-v2' table:
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- opp-supported-hw: Two bitmaps indicating:
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- Supported speed grade mask
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- Supported market segment mask
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0: Consumer
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1: Extended Consumer
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2: Industrial
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3: Automotive
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Example:
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--------
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opp_table {
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compatible = "operating-points-v2";
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opp-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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/* grade >= 0, consumer only */
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opp-supported-hw = <0xf>, <0x3>;
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};
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opp-1300000000 {
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opp-hz = /bits/ 64 <1300000000>;
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opp-microvolt = <1000000>;
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/* grade >= 1, all segments */
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opp-supported-hw = <0xe>, <0x7>;
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};
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}
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@ -93,6 +93,15 @@ config ARM_IMX6Q_CPUFREQ
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If in doubt, say N.
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config ARM_IMX_CPUFREQ_DT
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tristate "Freescale i.MX8M cpufreq support"
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depends on ARCH_MXC && CPUFREQ_DT
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help
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This adds cpufreq driver support for Freescale i.MX8M series SoCs,
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based on cpufreq-dt.
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If in doubt, say N.
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config ARM_KIRKWOOD_CPUFREQ
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def_bool MACH_KIRKWOOD
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help
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@ -133,6 +142,14 @@ config ARM_QCOM_CPUFREQ_HW
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The driver implements the cpufreq interface for this HW engine.
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Say Y if you want to support CPUFreq HW.
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config ARM_RASPBERRYPI_CPUFREQ
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tristate "Raspberry Pi cpufreq support"
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depends on CLK_RASPBERRYPI || COMPILE_TEST
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help
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This adds the CPUFreq driver for Raspberry Pi
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If in doubt, say N.
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config ARM_S3C_CPUFREQ
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bool
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help
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@ -56,6 +56,7 @@ obj-$(CONFIG_ACPI_CPPC_CPUFREQ) += cppc_cpufreq.o
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obj-$(CONFIG_ARCH_DAVINCI) += davinci-cpufreq.o
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obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o
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obj-$(CONFIG_ARM_IMX6Q_CPUFREQ) += imx6q-cpufreq.o
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obj-$(CONFIG_ARM_IMX_CPUFREQ_DT) += imx-cpufreq-dt.o
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obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ) += kirkwood-cpufreq.o
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obj-$(CONFIG_ARM_MEDIATEK_CPUFREQ) += mediatek-cpufreq.o
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obj-$(CONFIG_MACH_MVEBU_V7) += mvebu-cpufreq.o
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@ -64,6 +65,7 @@ obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o
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obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o
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obj-$(CONFIG_ARM_QCOM_CPUFREQ_HW) += qcom-cpufreq-hw.o
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obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRYO) += qcom-cpufreq-kryo.o
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obj-$(CONFIG_ARM_RASPBERRYPI_CPUFREQ) += raspberrypi-cpufreq.o
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obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o
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obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o
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obj-$(CONFIG_ARM_S3C2416_CPUFREQ) += s3c2416-cpufreq.o
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@ -257,7 +257,7 @@ static void __init armada37xx_cpufreq_avs_configure(struct regmap *base,
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static void __init armada37xx_cpufreq_avs_setup(struct regmap *base,
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struct armada_37xx_dvfs *dvfs)
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{
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unsigned int avs_val = 0, freq;
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unsigned int avs_val = 0;
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int load_level = 0;
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if (base == NULL)
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@ -275,8 +275,6 @@ static void __init armada37xx_cpufreq_avs_setup(struct regmap *base,
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for (load_level = 1; load_level < LOAD_LEVEL_NR; load_level++) {
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freq = dvfs->cpu_freq_max / dvfs->divider[load_level];
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avs_val = dvfs->avs[load_level];
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regmap_update_bits(base, ARMADA_37XX_AVS_VSET(load_level-1),
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ARMADA_37XX_AVS_VDD_MASK << ARMADA_37XX_AVS_HIGH_VDD_LIMIT |
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@ -384,12 +384,12 @@ static int brcm_avs_set_pstate(struct private_data *priv, unsigned int pstate)
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return __issue_avs_command(priv, AVS_CMD_SET_PSTATE, true, args);
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}
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static unsigned long brcm_avs_get_voltage(void __iomem *base)
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static u32 brcm_avs_get_voltage(void __iomem *base)
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{
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return readl(base + AVS_MBOX_VOLTAGE1);
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}
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static unsigned long brcm_avs_get_frequency(void __iomem *base)
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static u32 brcm_avs_get_frequency(void __iomem *base)
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{
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return readl(base + AVS_MBOX_FREQUENCY) * 1000; /* in kHz */
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}
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@ -446,8 +446,8 @@ static bool brcm_avs_is_firmware_loaded(struct private_data *priv)
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rc = brcm_avs_get_pmap(priv, NULL);
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magic = readl(priv->base + AVS_MBOX_MAGIC);
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return (magic == AVS_FIRMWARE_MAGIC) && (rc != -ENOTSUPP) &&
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(rc != -EINVAL);
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return (magic == AVS_FIRMWARE_MAGIC) && ((rc != -ENOTSUPP) ||
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(rc != -EINVAL));
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}
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static unsigned int brcm_avs_cpufreq_get(unsigned int cpu)
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@ -653,14 +653,14 @@ static ssize_t show_brcm_avs_voltage(struct cpufreq_policy *policy, char *buf)
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{
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struct private_data *priv = policy->driver_data;
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return sprintf(buf, "0x%08lx\n", brcm_avs_get_voltage(priv->base));
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return sprintf(buf, "0x%08x\n", brcm_avs_get_voltage(priv->base));
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}
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static ssize_t show_brcm_avs_frequency(struct cpufreq_policy *policy, char *buf)
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{
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struct private_data *priv = policy->driver_data;
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return sprintf(buf, "0x%08lx\n", brcm_avs_get_frequency(priv->base));
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return sprintf(buf, "0x%08x\n", brcm_avs_get_frequency(priv->base));
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}
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cpufreq_freq_attr_ro(brcm_avs_pstate);
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@ -40,7 +40,6 @@ static const struct of_device_id whitelist[] __initconst = {
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{ .compatible = "fsl,imx27", },
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{ .compatible = "fsl,imx51", },
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{ .compatible = "fsl,imx53", },
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{ .compatible = "fsl,imx7d", },
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{ .compatible = "marvell,berlin", },
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{ .compatible = "marvell,pxa250", },
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@ -108,6 +107,10 @@ static const struct of_device_id blacklist[] __initconst = {
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{ .compatible = "calxeda,highbank", },
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{ .compatible = "calxeda,ecx-2000", },
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{ .compatible = "fsl,imx7d", },
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{ .compatible = "fsl,imx8mq", },
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{ .compatible = "fsl,imx8mm", },
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{ .compatible = "marvell,armadaxp", },
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{ .compatible = "mediatek,mt2701", },
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@ -0,0 +1,97 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2019 NXP
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*/
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#include <linux/cpu.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/nvmem-consumer.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_opp.h>
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#include <linux/slab.h>
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#define OCOTP_CFG3_SPEED_GRADE_SHIFT 8
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#define OCOTP_CFG3_SPEED_GRADE_MASK (0x3 << 8)
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#define OCOTP_CFG3_MKT_SEGMENT_SHIFT 6
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#define OCOTP_CFG3_MKT_SEGMENT_MASK (0x3 << 6)
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/* cpufreq-dt device registered by imx-cpufreq-dt */
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static struct platform_device *cpufreq_dt_pdev;
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static struct opp_table *cpufreq_opp_table;
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static int imx_cpufreq_dt_probe(struct platform_device *pdev)
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{
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struct device *cpu_dev = get_cpu_device(0);
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u32 cell_value, supported_hw[2];
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int speed_grade, mkt_segment;
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int ret;
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ret = nvmem_cell_read_u32(cpu_dev, "speed_grade", &cell_value);
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if (ret)
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return ret;
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speed_grade = (cell_value & OCOTP_CFG3_SPEED_GRADE_MASK) >> OCOTP_CFG3_SPEED_GRADE_SHIFT;
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mkt_segment = (cell_value & OCOTP_CFG3_MKT_SEGMENT_MASK) >> OCOTP_CFG3_MKT_SEGMENT_SHIFT;
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/*
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* Early samples without fuses written report "0 0" which means
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* consumer segment and minimum speed grading.
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*
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* According to datasheet minimum speed grading is not supported for
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* consumer parts so clamp to 1 to avoid warning for "no OPPs"
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*
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* Applies to 8mq and 8mm.
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*/
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if (mkt_segment == 0 && speed_grade == 0 && (
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of_machine_is_compatible("fsl,imx8mm") ||
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of_machine_is_compatible("fsl,imx8mq")))
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speed_grade = 1;
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supported_hw[0] = BIT(speed_grade);
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supported_hw[1] = BIT(mkt_segment);
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dev_info(&pdev->dev, "cpu speed grade %d mkt segment %d supported-hw %#x %#x\n",
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speed_grade, mkt_segment, supported_hw[0], supported_hw[1]);
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cpufreq_opp_table = dev_pm_opp_set_supported_hw(cpu_dev, supported_hw, 2);
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if (IS_ERR(cpufreq_opp_table)) {
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ret = PTR_ERR(cpufreq_opp_table);
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dev_err(&pdev->dev, "Failed to set supported opp: %d\n", ret);
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return ret;
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}
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cpufreq_dt_pdev = platform_device_register_data(
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&pdev->dev, "cpufreq-dt", -1, NULL, 0);
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if (IS_ERR(cpufreq_dt_pdev)) {
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dev_pm_opp_put_supported_hw(cpufreq_opp_table);
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ret = PTR_ERR(cpufreq_dt_pdev);
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dev_err(&pdev->dev, "Failed to register cpufreq-dt: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static int imx_cpufreq_dt_remove(struct platform_device *pdev)
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{
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platform_device_unregister(cpufreq_dt_pdev);
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dev_pm_opp_put_supported_hw(cpufreq_opp_table);
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return 0;
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}
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static struct platform_driver imx_cpufreq_dt_driver = {
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.probe = imx_cpufreq_dt_probe,
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.remove = imx_cpufreq_dt_remove,
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.driver = {
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.name = "imx-cpufreq-dt",
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},
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};
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module_platform_driver(imx_cpufreq_dt_driver);
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MODULE_ALIAS("platform:imx-cpufreq-dt");
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MODULE_DESCRIPTION("Freescale i.MX cpufreq speed grading driver");
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MODULE_LICENSE("GPL v2");
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@ -0,0 +1,97 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Raspberry Pi cpufreq driver
|
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*
|
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* Copyright (C) 2019, Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
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*/
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#include <linux/clk.h>
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#include <linux/cpu.h>
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#include <linux/cpufreq.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_opp.h>
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|
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#define RASPBERRYPI_FREQ_INTERVAL 100000000
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|
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static struct platform_device *cpufreq_dt;
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|
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static int raspberrypi_cpufreq_probe(struct platform_device *pdev)
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{
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struct device *cpu_dev;
|
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unsigned long min, max;
|
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unsigned long rate;
|
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struct clk *clk;
|
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int ret;
|
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|
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cpu_dev = get_cpu_device(0);
|
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if (!cpu_dev) {
|
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pr_err("Cannot get CPU for cpufreq driver\n");
|
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return -ENODEV;
|
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}
|
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|
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clk = clk_get(cpu_dev, NULL);
|
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if (IS_ERR(clk)) {
|
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dev_err(cpu_dev, "Cannot get clock for CPU0\n");
|
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return PTR_ERR(clk);
|
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}
|
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|
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/*
|
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* The max and min frequencies are configurable in the Raspberry Pi
|
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* firmware, so we query them at runtime.
|
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*/
|
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min = roundup(clk_round_rate(clk, 0), RASPBERRYPI_FREQ_INTERVAL);
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max = roundup(clk_round_rate(clk, ULONG_MAX), RASPBERRYPI_FREQ_INTERVAL);
|
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clk_put(clk);
|
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|
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for (rate = min; rate <= max; rate += RASPBERRYPI_FREQ_INTERVAL) {
|
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ret = dev_pm_opp_add(cpu_dev, rate, 0);
|
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if (ret)
|
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goto remove_opp;
|
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}
|
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|
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cpufreq_dt = platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
|
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ret = PTR_ERR_OR_ZERO(cpufreq_dt);
|
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if (ret) {
|
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dev_err(cpu_dev, "Failed to create platform device, %d\n", ret);
|
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goto remove_opp;
|
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}
|
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|
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return 0;
|
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|
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remove_opp:
|
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dev_pm_opp_remove_all_dynamic(cpu_dev);
|
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|
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return ret;
|
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}
|
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|
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static int raspberrypi_cpufreq_remove(struct platform_device *pdev)
|
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{
|
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struct device *cpu_dev;
|
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|
||||
cpu_dev = get_cpu_device(0);
|
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if (cpu_dev)
|
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dev_pm_opp_remove_all_dynamic(cpu_dev);
|
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|
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platform_device_unregister(cpufreq_dt);
|
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|
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return 0;
|
||||
}
|
||||
|
||||
/*
|
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* Since the driver depends on clk-raspberrypi, which may return EPROBE_DEFER,
|
||||
* all the activity is performed in the probe, which may be defered as well.
|
||||
*/
|
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static struct platform_driver raspberrypi_cpufreq_driver = {
|
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.driver = {
|
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.name = "raspberrypi-cpufreq",
|
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},
|
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.probe = raspberrypi_cpufreq_probe,
|
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.remove = raspberrypi_cpufreq_remove,
|
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};
|
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module_platform_driver(raspberrypi_cpufreq_driver);
|
||||
|
||||
MODULE_AUTHOR("Nicolas Saenz Julienne <nsaenzjulienne@suse.de");
|
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MODULE_DESCRIPTION("Raspberry Pi cpufreq driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_ALIAS("platform:raspberrypi-cpufreq");
|
||||
|
|
@ -481,7 +481,7 @@ static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index)
|
|||
arm_volt, arm_volt_max);
|
||||
}
|
||||
|
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printk(KERN_DEBUG "Perf changed[L%d]\n", index);
|
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pr_debug("Perf changed[L%d]\n", index);
|
||||
|
||||
exit:
|
||||
mutex_unlock(&set_freq_lock);
|
||||
|
|
|
|||
|
|
@ -103,6 +103,9 @@ static int __init imx8_soc_init(void)
|
|||
if (IS_ERR(soc_dev))
|
||||
goto free_rev;
|
||||
|
||||
if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT))
|
||||
platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0);
|
||||
|
||||
return 0;
|
||||
|
||||
free_rev:
|
||||
|
|
|
|||
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