coresight: cti-sysfs: Re-use same functions for similar sysfs register accessors
Currently each accessor macro creates an identical function which wastes space in the text area and pollutes the ftrace function name list. Change it so that the same function is used, but the register to access is passed in as parameter rather than baked into each function. Note that only the single accessor is used here and not csdev_access_relaxed_read_pair() like in the previous commit, so so a single unsigned offset value is stored instead. Signed-off-by: James Clark <james.clark@arm.com> Reviewed-by: Mike Leach <mike.leach@linaro.org> Link: https://lore.kernel.org/r/20220830172614.340962-5-james.clark@arm.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
This commit is contained in:
James Clark
Mathieu Poirier
Родитель
08e9fa5f36
Коммит
fbca79e554
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@ -163,48 +163,82 @@ static struct attribute *coresight_cti_attrs[] = {
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/* register based attributes */
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/* macro to access RO registers with power check only (no enable check). */
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#define coresight_cti_reg(name, offset) \
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static ssize_t name##_show(struct device *dev, \
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struct device_attribute *attr, char *buf) \
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{ \
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struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); \
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u32 val = 0; \
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pm_runtime_get_sync(dev->parent); \
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spin_lock(&drvdata->spinlock); \
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if (drvdata->config.hw_powered) \
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val = readl_relaxed(drvdata->base + offset); \
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spin_unlock(&drvdata->spinlock); \
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pm_runtime_put_sync(dev->parent); \
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return sprintf(buf, "0x%x\n", val); \
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} \
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static DEVICE_ATTR_RO(name)
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/* Read registers with power check only (no enable check). */
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static ssize_t coresight_cti_reg_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
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struct cs_off_attribute *cti_attr = container_of(attr, struct cs_off_attribute, attr);
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u32 val = 0;
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pm_runtime_get_sync(dev->parent);
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spin_lock(&drvdata->spinlock);
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if (drvdata->config.hw_powered)
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val = readl_relaxed(drvdata->base + cti_attr->off);
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spin_unlock(&drvdata->spinlock);
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pm_runtime_put_sync(dev->parent);
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return sysfs_emit(buf, "0x%x\n", val);
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}
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/* Write registers with power check only (no enable check). */
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static ssize_t coresight_cti_reg_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t size)
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{
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struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
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struct cs_off_attribute *cti_attr = container_of(attr, struct cs_off_attribute, attr);
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unsigned long val = 0;
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if (kstrtoul(buf, 0, &val))
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return -EINVAL;
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pm_runtime_get_sync(dev->parent);
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spin_lock(&drvdata->spinlock);
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if (drvdata->config.hw_powered)
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cti_write_single_reg(drvdata, cti_attr->off, val);
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spin_unlock(&drvdata->spinlock);
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pm_runtime_put_sync(dev->parent);
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return size;
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}
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#define coresight_cti_reg(name, offset) \
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(&((struct cs_off_attribute[]) { \
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{ \
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__ATTR(name, 0444, coresight_cti_reg_show, NULL), \
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offset \
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} \
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})[0].attr.attr)
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#define coresight_cti_reg_rw(name, offset) \
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(&((struct cs_off_attribute[]) { \
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{ \
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__ATTR(name, 0644, coresight_cti_reg_show, \
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coresight_cti_reg_store), \
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offset \
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} \
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})[0].attr.attr)
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#define coresight_cti_reg_wo(name, offset) \
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(&((struct cs_off_attribute[]) { \
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{ \
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__ATTR(name, 0200, NULL, coresight_cti_reg_store), \
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offset \
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} \
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})[0].attr.attr)
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/* coresight management registers */
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coresight_cti_reg(devaff0, CTIDEVAFF0);
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coresight_cti_reg(devaff1, CTIDEVAFF1);
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coresight_cti_reg(authstatus, CORESIGHT_AUTHSTATUS);
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coresight_cti_reg(devarch, CORESIGHT_DEVARCH);
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coresight_cti_reg(devid, CORESIGHT_DEVID);
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coresight_cti_reg(devtype, CORESIGHT_DEVTYPE);
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coresight_cti_reg(pidr0, CORESIGHT_PERIPHIDR0);
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coresight_cti_reg(pidr1, CORESIGHT_PERIPHIDR1);
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coresight_cti_reg(pidr2, CORESIGHT_PERIPHIDR2);
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coresight_cti_reg(pidr3, CORESIGHT_PERIPHIDR3);
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coresight_cti_reg(pidr4, CORESIGHT_PERIPHIDR4);
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static struct attribute *coresight_cti_mgmt_attrs[] = {
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&dev_attr_devaff0.attr,
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&dev_attr_devaff1.attr,
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&dev_attr_authstatus.attr,
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&dev_attr_devarch.attr,
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&dev_attr_devid.attr,
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&dev_attr_devtype.attr,
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&dev_attr_pidr0.attr,
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&dev_attr_pidr1.attr,
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&dev_attr_pidr2.attr,
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&dev_attr_pidr3.attr,
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&dev_attr_pidr4.attr,
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coresight_cti_reg(devaff0, CTIDEVAFF0),
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coresight_cti_reg(devaff1, CTIDEVAFF1),
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coresight_cti_reg(authstatus, CORESIGHT_AUTHSTATUS),
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coresight_cti_reg(devarch, CORESIGHT_DEVARCH),
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coresight_cti_reg(devid, CORESIGHT_DEVID),
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coresight_cti_reg(devtype, CORESIGHT_DEVTYPE),
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coresight_cti_reg(pidr0, CORESIGHT_PERIPHIDR0),
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coresight_cti_reg(pidr1, CORESIGHT_PERIPHIDR1),
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coresight_cti_reg(pidr2, CORESIGHT_PERIPHIDR2),
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coresight_cti_reg(pidr3, CORESIGHT_PERIPHIDR3),
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coresight_cti_reg(pidr4, CORESIGHT_PERIPHIDR4),
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NULL,
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};
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@ -454,86 +488,11 @@ static ssize_t apppulse_store(struct device *dev,
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}
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static DEVICE_ATTR_WO(apppulse);
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coresight_cti_reg(triginstatus, CTITRIGINSTATUS);
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coresight_cti_reg(trigoutstatus, CTITRIGOUTSTATUS);
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coresight_cti_reg(chinstatus, CTICHINSTATUS);
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coresight_cti_reg(choutstatus, CTICHOUTSTATUS);
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/*
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* Define CONFIG_CORESIGHT_CTI_INTEGRATION_REGS to enable the access to the
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* integration control registers. Normally only used to investigate connection
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* data.
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*/
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#ifdef CONFIG_CORESIGHT_CTI_INTEGRATION_REGS
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/* macro to access RW registers with power check only (no enable check). */
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#define coresight_cti_reg_rw(name, offset) \
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static ssize_t name##_show(struct device *dev, \
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struct device_attribute *attr, char *buf) \
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{ \
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struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); \
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u32 val = 0; \
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pm_runtime_get_sync(dev->parent); \
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spin_lock(&drvdata->spinlock); \
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if (drvdata->config.hw_powered) \
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val = readl_relaxed(drvdata->base + offset); \
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spin_unlock(&drvdata->spinlock); \
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pm_runtime_put_sync(dev->parent); \
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return sprintf(buf, "0x%x\n", val); \
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} \
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\
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static ssize_t name##_store(struct device *dev, \
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struct device_attribute *attr, \
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const char *buf, size_t size) \
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{ \
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struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); \
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unsigned long val = 0; \
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if (kstrtoul(buf, 0, &val)) \
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return -EINVAL; \
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\
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pm_runtime_get_sync(dev->parent); \
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spin_lock(&drvdata->spinlock); \
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if (drvdata->config.hw_powered) \
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cti_write_single_reg(drvdata, offset, val); \
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spin_unlock(&drvdata->spinlock); \
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pm_runtime_put_sync(dev->parent); \
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return size; \
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} \
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static DEVICE_ATTR_RW(name)
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/* macro to access WO registers with power check only (no enable check). */
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#define coresight_cti_reg_wo(name, offset) \
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static ssize_t name##_store(struct device *dev, \
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struct device_attribute *attr, \
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const char *buf, size_t size) \
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{ \
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struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); \
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unsigned long val = 0; \
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if (kstrtoul(buf, 0, &val)) \
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return -EINVAL; \
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\
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pm_runtime_get_sync(dev->parent); \
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spin_lock(&drvdata->spinlock); \
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if (drvdata->config.hw_powered) \
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cti_write_single_reg(drvdata, offset, val); \
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spin_unlock(&drvdata->spinlock); \
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pm_runtime_put_sync(dev->parent); \
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return size; \
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} \
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static DEVICE_ATTR_WO(name)
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coresight_cti_reg_rw(itchout, ITCHOUT);
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coresight_cti_reg_rw(ittrigout, ITTRIGOUT);
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coresight_cti_reg_rw(itctrl, CORESIGHT_ITCTRL);
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coresight_cti_reg_wo(itchinack, ITCHINACK);
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coresight_cti_reg_wo(ittriginack, ITTRIGINACK);
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coresight_cti_reg(ittrigin, ITTRIGIN);
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coresight_cti_reg(itchin, ITCHIN);
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coresight_cti_reg(itchoutack, ITCHOUTACK);
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coresight_cti_reg(ittrigoutack, ITTRIGOUTACK);
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#endif /* CORESIGHT_CTI_INTEGRATION_REGS */
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static struct attribute *coresight_cti_regs_attrs[] = {
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&dev_attr_inout_sel.attr,
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&dev_attr_inen.attr,
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@ -544,20 +503,20 @@ static struct attribute *coresight_cti_regs_attrs[] = {
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&dev_attr_appset.attr,
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&dev_attr_appclear.attr,
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&dev_attr_apppulse.attr,
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&dev_attr_triginstatus.attr,
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&dev_attr_trigoutstatus.attr,
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&dev_attr_chinstatus.attr,
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&dev_attr_choutstatus.attr,
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coresight_cti_reg(triginstatus, CTITRIGINSTATUS),
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coresight_cti_reg(trigoutstatus, CTITRIGOUTSTATUS),
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coresight_cti_reg(chinstatus, CTICHINSTATUS),
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coresight_cti_reg(choutstatus, CTICHOUTSTATUS),
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#ifdef CONFIG_CORESIGHT_CTI_INTEGRATION_REGS
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&dev_attr_itctrl.attr,
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&dev_attr_ittrigin.attr,
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&dev_attr_itchin.attr,
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&dev_attr_ittrigout.attr,
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&dev_attr_itchout.attr,
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&dev_attr_itchoutack.attr,
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&dev_attr_ittrigoutack.attr,
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&dev_attr_ittriginack.attr,
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&dev_attr_itchinack.attr,
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coresight_cti_reg_rw(itctrl, CORESIGHT_ITCTRL),
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coresight_cti_reg(ittrigin, ITTRIGIN),
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coresight_cti_reg(itchin, ITCHIN),
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coresight_cti_reg_rw(ittrigout, ITTRIGOUT),
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coresight_cti_reg_rw(itchout, ITCHOUT),
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coresight_cti_reg(itchoutack, ITCHOUTACK),
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coresight_cti_reg(ittrigoutack, ITTRIGOUTACK),
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coresight_cti_reg_wo(ittriginack, ITTRIGINACK),
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coresight_cti_reg_wo(itchinack, ITCHINACK),
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#endif
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NULL,
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};
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@ -45,6 +45,11 @@ struct cs_pair_attribute {
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s32 hi_off;
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};
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struct cs_off_attribute {
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struct device_attribute attr;
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u32 off;
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};
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extern ssize_t coresight_simple_show(struct device *_dev,
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struct device_attribute *attr, char *buf);
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