hpt366: remove ->init_setup
* Split off hpt{374,371,366}_init() helper from init_setup_hpt{374,371,366}().
* Merge init_setup_{374,372n,371,372a,302,366}() into hpt366_init_one().
While at it:
* Use "HPT36x" name for HPT366/HPT368 chipsets.
* Add .chip_name to struct hpt_info and use it to set set d->name.
* Convert .max_ultra in struct hpt_info to .udma_mask and use it to set
d->udma_mask.
* Fix hpt302 to use HPT302_ALLOW_ATA133_6 define.
* Change HPT366/HPT374 interrupt fixup message from KERN_WARNING to KERN_INFO.
* Use the second hpt366_chipsets[] entry for HPT37x chipsets using HPT36x PCI
device ID and fix .enablebits/.host_flags for HPT36x hpt366_chipsets[] entry.
* Bump driver version.
Cc: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
This commit is contained in:
Bartlomiej Zolnierkiewicz
Родитель
bfd314a304
Коммит
fbf47840fe
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@ -1,9 +1,10 @@
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/*
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* linux/drivers/ide/pci/hpt366.c Version 1.15 Oct 1, 2007
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* linux/drivers/ide/pci/hpt366.c Version 1.20 Oct 1, 2007
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*
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* Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
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* Portions Copyright (C) 2001 Sun Microsystems, Inc.
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* Portions Copyright (C) 2003 Red Hat Inc
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* Portions Copyright (C) 2007 Bartlomiej Zolnierkiewicz
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* Portions Copyright (C) 2005-2007 MontaVista Software, Inc.
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*
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* Thanks to HighPoint Technologies for their assistance, and hardware.
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@ -393,8 +394,9 @@ enum ata_clock {
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*/
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struct hpt_info {
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char *chip_name; /* Chip name */
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u8 chip_type; /* Chip type */
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u8 max_ultra; /* Max. UltraDMA mode allowed */
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u8 udma_mask; /* Allowed UltraDMA modes mask. */
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u8 dpll_clk; /* DPLL clock in MHz */
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u8 pci_clk; /* PCI clock in MHz */
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u32 **settings; /* Chipset settings table */
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@ -432,78 +434,89 @@ static u32 *hpt37x_settings[NUM_ATA_CLOCKS] = {
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};
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static struct hpt_info hpt36x __devinitdata = {
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.chip_name = "HPT36x",
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.chip_type = HPT36x,
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.max_ultra = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? 4 : 3) : 2,
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.udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2,
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.dpll_clk = 0, /* no DPLL */
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.settings = hpt36x_settings
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};
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static struct hpt_info hpt370 __devinitdata = {
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.chip_name = "HPT370",
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.chip_type = HPT370,
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.max_ultra = HPT370_ALLOW_ATA100_5 ? 5 : 4,
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.udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
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.dpll_clk = 48,
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.settings = hpt37x_settings
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};
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static struct hpt_info hpt370a __devinitdata = {
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.chip_name = "HPT370A",
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.chip_type = HPT370A,
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.max_ultra = HPT370_ALLOW_ATA100_5 ? 5 : 4,
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.udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
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.dpll_clk = 48,
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.settings = hpt37x_settings
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};
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static struct hpt_info hpt374 __devinitdata = {
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.chip_name = "HPT374",
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.chip_type = HPT374,
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.max_ultra = 5,
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.udma_mask = ATA_UDMA5,
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.dpll_clk = 48,
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.settings = hpt37x_settings
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};
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static struct hpt_info hpt372 __devinitdata = {
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.chip_name = "HPT372",
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.chip_type = HPT372,
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.max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5,
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.udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
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.dpll_clk = 55,
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.settings = hpt37x_settings
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};
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static struct hpt_info hpt372a __devinitdata = {
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.chip_name = "HPT372A",
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.chip_type = HPT372A,
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.max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5,
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.udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
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.dpll_clk = 66,
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.settings = hpt37x_settings
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};
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static struct hpt_info hpt302 __devinitdata = {
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.chip_name = "HPT302",
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.chip_type = HPT302,
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.max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5,
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.udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
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.dpll_clk = 66,
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.settings = hpt37x_settings
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};
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static struct hpt_info hpt371 __devinitdata = {
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.chip_name = "HPT371",
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.chip_type = HPT371,
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.max_ultra = HPT371_ALLOW_ATA133_6 ? 6 : 5,
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.udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
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.dpll_clk = 66,
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.settings = hpt37x_settings
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};
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static struct hpt_info hpt372n __devinitdata = {
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.chip_name = "HPT372N",
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.chip_type = HPT372N,
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.max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5,
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.udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
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.dpll_clk = 77,
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.settings = hpt37x_settings
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};
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static struct hpt_info hpt302n __devinitdata = {
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.chip_name = "HPT302N",
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.chip_type = HPT302N,
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.max_ultra = HPT302_ALLOW_ATA133_6 ? 6 : 5,
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.udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
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.dpll_clk = 77,
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.settings = hpt37x_settings
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};
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static struct hpt_info hpt371n __devinitdata = {
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.chip_name = "HPT371N",
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.chip_type = HPT371N,
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.max_ultra = HPT371_ALLOW_ATA133_6 ? 6 : 5,
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.udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
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.dpll_clk = 77,
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.settings = hpt37x_settings
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};
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@ -1136,7 +1149,7 @@ static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const cha
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* Select 66 MHz DPLL clock only if UltraATA/133 mode is
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* supported/enabled, use 50 MHz DPLL clock otherwise...
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*/
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if (info->max_ultra == 6) {
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if (info->udma_mask == ATA_UDMA6) {
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dpll_clk = 66;
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clock = ATA_CLOCK_66MHZ;
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} else if (dpll_clk) { /* HPT36x chips don't have DPLL */
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@ -1366,53 +1379,19 @@ static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
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ide_setup_dma(hwif, dmabase, 8);
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}
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static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
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static void __devinit hpt374_init(struct pci_dev *dev, struct pci_dev *dev2)
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{
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struct pci_dev *dev2;
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if (PCI_FUNC(dev->devfn) & 1)
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return -ENODEV;
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pci_set_drvdata(dev, &hpt374);
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if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
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int ret;
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pci_set_drvdata(dev2, &hpt374);
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if (dev2->irq != dev->irq) {
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/* FIXME: we need a core pci_set_interrupt() */
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dev2->irq = dev->irq;
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printk(KERN_WARNING "%s: PCI config space interrupt "
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"fixed.\n", d->name);
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}
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ret = ide_setup_pci_devices(dev, dev2, d);
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if (ret < 0)
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pci_dev_put(dev2);
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return ret;
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if (dev2->irq != dev->irq) {
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/* FIXME: we need a core pci_set_interrupt() */
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dev2->irq = dev->irq;
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printk(KERN_INFO "HPT374: PCI config space interrupt fixed\n");
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}
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return ide_setup_pci_device(dev, d);
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}
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static int __devinit init_setup_hpt372n(struct pci_dev *dev, ide_pci_device_t *d)
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static void __devinit hpt371_init(struct pci_dev *dev)
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{
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pci_set_drvdata(dev, &hpt372n);
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return ide_setup_pci_device(dev, d);
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}
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static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
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{
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struct hpt_info *info;
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u8 mcr1 = 0;
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if (dev->revision > 1) {
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d->name = "HPT371N";
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info = &hpt371n;
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} else
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info = &hpt371;
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/*
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* HPT371 chips physically have only one channel, the secondary one,
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* but the primary channel registers do exist! Go figure...
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@ -1422,173 +1401,83 @@ static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
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pci_read_config_byte(dev, 0x50, &mcr1);
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if (mcr1 & 0x04)
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pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
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pci_set_drvdata(dev, info);
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return ide_setup_pci_device(dev, d);
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}
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static int __devinit init_setup_hpt372a(struct pci_dev *dev, ide_pci_device_t *d)
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static int __devinit hpt36x_init(struct pci_dev *dev, struct pci_dev *dev2)
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{
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struct hpt_info *info;
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u8 mcr1 = 0, pin1 = 0, pin2 = 0;
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if (dev->revision > 1) {
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d->name = "HPT372N";
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/*
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* Now we'll have to force both channels enabled if
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* at least one of them has been enabled by BIOS...
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*/
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pci_read_config_byte(dev, 0x50, &mcr1);
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if (mcr1 & 0x30)
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pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
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info = &hpt372n;
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} else
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info = &hpt372a;
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pci_set_drvdata(dev, info);
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pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
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pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
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return ide_setup_pci_device(dev, d);
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if (pin1 != pin2 && dev->irq == dev2->irq) {
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printk(KERN_INFO "HPT36x: onboard version of chipset, "
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"pin1=%d pin2=%d\n", pin1, pin2);
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return 1;
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}
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return 0;
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}
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static int __devinit init_setup_hpt302(struct pci_dev *dev, ide_pci_device_t *d)
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{
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struct hpt_info *info;
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if (dev->revision > 1) {
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d->name = "HPT302N";
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info = &hpt302n;
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} else
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info = &hpt302;
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pci_set_drvdata(dev, info);
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return ide_setup_pci_device(dev, d);
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}
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static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
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{
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struct pci_dev *dev2;
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u8 rev = dev->revision;
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static char *chipset_names[] = { "HPT366", "HPT366", "HPT368",
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"HPT370", "HPT370A", "HPT372",
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"HPT372N" };
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static struct hpt_info *info[] = { &hpt36x, &hpt36x, &hpt36x,
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&hpt370, &hpt370a, &hpt372,
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&hpt372n };
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if (PCI_FUNC(dev->devfn) & 1)
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return -ENODEV;
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switch (rev) {
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case 0:
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case 1:
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case 2:
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static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
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{ /* 0 */
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.name = "HPT36x",
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.init_chipset = init_chipset_hpt366,
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.init_hwif = init_hwif_hpt366,
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.init_dma = init_dma_hpt366,
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/*
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* HPT36x chips have one channel per function and have
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* both channel enable bits located differently and visible
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* to both functions -- really stupid design decision... :-(
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* Bit 4 is for the primary channel, bit 5 for the secondary.
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*/
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d->host_flags |= IDE_HFLAG_SINGLE;
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d->enablebits[0].mask = d->enablebits[0].val = 0x10;
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d->udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ?
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ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2;
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break;
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case 3:
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case 4:
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d->udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4;
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break;
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default:
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rev = 6;
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/* fall thru */
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case 5:
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case 6:
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d->udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5;
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break;
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}
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d->name = chipset_names[rev];
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pci_set_drvdata(dev, info[rev]);
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if (rev > 2)
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goto init_single;
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if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
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u8 mcr1 = 0, pin1 = 0, pin2 = 0;
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int ret;
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pci_set_drvdata(dev2, info[rev]);
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/*
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* Now we'll have to force both channels enabled if
|
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* at least one of them has been enabled by BIOS...
|
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*/
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pci_read_config_byte(dev, 0x50, &mcr1);
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if (mcr1 & 0x30)
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pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
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pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
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pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
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if (pin1 != pin2 && dev->irq == dev2->irq) {
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d->host_flags |= IDE_HFLAG_BOOTABLE;
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printk("%s: onboard version of chipset, pin1=%d pin2=%d\n",
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d->name, pin1, pin2);
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}
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ret = ide_setup_pci_devices(dev, dev2, d);
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if (ret < 0)
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pci_dev_put(dev2);
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return ret;
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}
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init_single:
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return ide_setup_pci_device(dev, d);
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}
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|
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static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
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{ /* 0 */
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.name = "HPT366",
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.init_setup = init_setup_hpt366,
|
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.init_chipset = init_chipset_hpt366,
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.init_hwif = init_hwif_hpt366,
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.init_dma = init_dma_hpt366,
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.enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
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.enablebits = {{0x50,0x10,0x10}, {0x54,0x04,0x04}},
|
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.extra = 240,
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.host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
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.host_flags = IDE_HFLAG_SINGLE |
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IDE_HFLAG_NO_ATAPI_DMA |
|
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IDE_HFLAG_OFF_BOARD,
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.pio_mask = ATA_PIO4,
|
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.mwdma_mask = ATA_MWDMA2,
|
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},{ /* 1 */
|
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.name = "HPT372A",
|
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.init_setup = init_setup_hpt372a,
|
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.init_chipset = init_chipset_hpt366,
|
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.init_hwif = init_hwif_hpt366,
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.init_dma = init_dma_hpt366,
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.enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
|
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.udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
|
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.extra = 240,
|
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.host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
|
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.pio_mask = ATA_PIO4,
|
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.mwdma_mask = ATA_MWDMA2,
|
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},{ /* 2 */
|
||||
.name = "HPT302",
|
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.init_setup = init_setup_hpt302,
|
||||
.init_chipset = init_chipset_hpt366,
|
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.init_hwif = init_hwif_hpt366,
|
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.init_dma = init_dma_hpt366,
|
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.enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
|
||||
.udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
|
||||
.extra = 240,
|
||||
.host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
|
||||
.pio_mask = ATA_PIO4,
|
||||
.mwdma_mask = ATA_MWDMA2,
|
||||
},{ /* 3 */
|
||||
.name = "HPT371",
|
||||
.init_setup = init_setup_hpt371,
|
||||
.init_chipset = init_chipset_hpt366,
|
||||
.init_hwif = init_hwif_hpt366,
|
||||
.init_dma = init_dma_hpt366,
|
||||
.enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
|
||||
.udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
|
||||
.extra = 240,
|
||||
.host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
|
||||
.pio_mask = ATA_PIO4,
|
||||
.mwdma_mask = ATA_MWDMA2,
|
||||
},{ /* 4 */
|
||||
.name = "HPT374",
|
||||
.init_setup = init_setup_hpt374,
|
||||
.init_chipset = init_chipset_hpt366,
|
||||
.init_hwif = init_hwif_hpt366,
|
||||
.init_dma = init_dma_hpt366,
|
||||
|
|
@ -1600,12 +1489,10 @@ static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
|
|||
.mwdma_mask = ATA_MWDMA2,
|
||||
},{ /* 5 */
|
||||
.name = "HPT372N",
|
||||
.init_setup = init_setup_hpt372n,
|
||||
.init_chipset = init_chipset_hpt366,
|
||||
.init_hwif = init_hwif_hpt366,
|
||||
.init_dma = init_dma_hpt366,
|
||||
.enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
|
||||
.udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
|
||||
.extra = 240,
|
||||
.host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
|
||||
.pio_mask = ATA_PIO4,
|
||||
|
|
@ -1620,16 +1507,77 @@ static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
|
|||
*
|
||||
* Called when the PCI registration layer (or the IDE initialization)
|
||||
* finds a device matching our IDE device tables.
|
||||
*
|
||||
* NOTE: since we'll have to modify some fields of the ide_pci_device_t
|
||||
* structure depending on the chip's revision, we'd better pass a local
|
||||
* copy down the call chain...
|
||||
*/
|
||||
static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
||||
{
|
||||
ide_pci_device_t d = hpt366_chipsets[id->driver_data];
|
||||
struct hpt_info *info = NULL;
|
||||
struct pci_dev *dev2 = NULL;
|
||||
ide_pci_device_t d;
|
||||
u8 idx = id->driver_data;
|
||||
u8 rev = dev->revision;
|
||||
|
||||
return d.init_setup(dev, &d);
|
||||
if ((idx == 0 || idx == 4) && (PCI_FUNC(dev->devfn) & 1))
|
||||
return -ENODEV;
|
||||
|
||||
switch (idx) {
|
||||
case 0:
|
||||
if (rev < 3)
|
||||
info = &hpt36x;
|
||||
else {
|
||||
static struct hpt_info *hpt37x_info[] =
|
||||
{ &hpt370, &hpt370a, &hpt372, &hpt372n };
|
||||
|
||||
info = hpt37x_info[min_t(u8, rev, 6) - 3];
|
||||
idx++;
|
||||
}
|
||||
break;
|
||||
case 1:
|
||||
info = (rev > 1) ? &hpt372n : &hpt372a;
|
||||
break;
|
||||
case 2:
|
||||
info = (rev > 1) ? &hpt302n : &hpt302;
|
||||
break;
|
||||
case 3:
|
||||
hpt371_init(dev);
|
||||
info = (rev > 1) ? &hpt371n : &hpt371;
|
||||
break;
|
||||
case 4:
|
||||
info = &hpt374;
|
||||
break;
|
||||
case 5:
|
||||
info = &hpt372n;
|
||||
break;
|
||||
}
|
||||
|
||||
d = hpt366_chipsets[idx];
|
||||
|
||||
d.name = info->chip_name;
|
||||
d.udma_mask = info->udma_mask;
|
||||
|
||||
pci_set_drvdata(dev, info);
|
||||
|
||||
if (info == &hpt36x || info == &hpt374)
|
||||
dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
|
||||
|
||||
if (dev2) {
|
||||
int ret;
|
||||
|
||||
pci_set_drvdata(dev2, info);
|
||||
|
||||
if (info == &hpt374)
|
||||
hpt374_init(dev, dev2);
|
||||
else {
|
||||
if (hpt36x_init(dev, dev2))
|
||||
d.host_flags |= IDE_HFLAG_BOOTABLE;
|
||||
}
|
||||
|
||||
ret = ide_setup_pci_devices(dev, dev2, &d);
|
||||
if (ret < 0)
|
||||
pci_dev_put(dev2);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return ide_setup_pci_device(dev, &d);
|
||||
}
|
||||
|
||||
static const struct pci_device_id hpt366_pci_tbl[] = {
|
||||
|
|
|
|||
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