powerpc/85xx: add DOZE/NAP support for e500 core
The e500 core enter DOZE/NAP power-saving modes when the core go to cpu_idle routine. The power management default running mode is DOZE, If the user echo 1 > /proc/sys/kernel/powersave-nap the system will change to NAP running mode. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
Родитель
3dfa877367
Коммит
fc4033b2f8
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@ -38,6 +38,7 @@ obj-$(CONFIG_IBMVIO) += vio.o
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obj-$(CONFIG_IBMEBUS) += ibmebus.o
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obj-$(CONFIG_GENERIC_TBSYNC) += smp-tbsync.o
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obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
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obj-$(CONFIG_E500) += idle_e500.o
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obj-$(CONFIG_6xx) += idle_6xx.o l2cr_6xx.o cpu_setup_6xx.o
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obj-$(CONFIG_TAU) += tau_6xx.o
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obj-$(CONFIG_HIBERNATION) += swsusp.o suspend.o \
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@ -1491,7 +1491,6 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x80200000,
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.cpu_name = "e500",
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/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
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.cpu_features = CPU_FTRS_E500,
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.cpu_user_features = COMMON_USER_BOOKE |
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PPC_FEATURE_HAS_SPE_COMP |
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@ -1508,7 +1507,6 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x80210000,
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.cpu_name = "e500v2",
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/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
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.cpu_features = CPU_FTRS_E500_2,
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.cpu_user_features = COMMON_USER_BOOKE |
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PPC_FEATURE_HAS_SPE_COMP |
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@ -1526,7 +1524,6 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x80230000,
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.cpu_name = "e500mc",
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/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
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.cpu_features = CPU_FTRS_E500MC,
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.cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
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.icache_bsize = 64,
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@ -176,14 +176,14 @@ transfer_to_handler:
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cmplw r1,r9 /* if r1 <= ksp_limit */
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ble- stack_ovf /* then the kernel stack overflowed */
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5:
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#ifdef CONFIG_6xx
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#if defined(CONFIG_6xx) || defined(CONFIG_E500)
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rlwinm r9,r1,0,0,31-THREAD_SHIFT
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tophys(r9,r9) /* check local flags */
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lwz r12,TI_LOCAL_FLAGS(r9)
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mtcrf 0x01,r12
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bt- 31-TLF_NAPPING,4f
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bt- 31-TLF_SLEEPING,7f
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#endif /* CONFIG_6xx */
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#endif /* CONFIG_6xx || CONFIG_E500 */
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.globl transfer_to_handler_cont
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transfer_to_handler_cont:
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3:
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@ -196,10 +196,10 @@ transfer_to_handler_cont:
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SYNC
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RFI /* jump to handler, enable MMU */
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#ifdef CONFIG_6xx
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#if defined (CONFIG_6xx) || defined(CONFIG_E500)
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4: rlwinm r12,r12,0,~_TLF_NAPPING
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stw r12,TI_LOCAL_FLAGS(r9)
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b power_save_6xx_restore
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b power_save_ppc32_restore
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7: rlwinm r12,r12,0,~_TLF_SLEEPING
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stw r12,TI_LOCAL_FLAGS(r9)
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@ -39,6 +39,7 @@
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#include <asm/thread_info.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/cache.h>
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#include "head_booke.h"
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/* As with the other PowerPC ports, it is expected that when code
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@ -1071,6 +1072,52 @@ _GLOBAL(set_context)
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isync /* Force context change */
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blr
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_GLOBAL(flush_dcache_L1)
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mfspr r3,SPRN_L1CFG0
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rlwinm r5,r3,9,3 /* Extract cache block size */
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twlgti r5,1 /* Only 32 and 64 byte cache blocks
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* are currently defined.
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*/
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li r4,32
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subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
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* log2(number of ways)
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*/
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slw r5,r4,r5 /* r5 = cache block size */
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rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
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mulli r7,r7,13 /* An 8-way cache will require 13
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* loads per set.
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*/
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slw r7,r7,r6
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/* save off HID0 and set DCFA */
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mfspr r8,SPRN_HID0
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ori r9,r8,HID0_DCFA@l
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mtspr SPRN_HID0,r9
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isync
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lis r4,KERNELBASE@h
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mtctr r7
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1: lwz r3,0(r4) /* Load... */
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add r4,r4,r5
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bdnz 1b
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msync
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lis r4,KERNELBASE@h
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mtctr r7
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1: dcbf 0,r4 /* ...and flush. */
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add r4,r4,r5
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bdnz 1b
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/* restore HID0 */
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mtspr SPRN_HID0,r8
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isync
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blr
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/*
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* We put a few things here that have to be page-aligned. This stuff
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* goes at the beginning of the data segment, which is page-aligned.
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@ -153,7 +153,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
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* address of current. R11 points to the exception frame (physical
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* address). We have to preserve r10.
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*/
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_GLOBAL(power_save_6xx_restore)
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_GLOBAL(power_save_ppc32_restore)
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lwz r9,_LINK(r11) /* interrupted in ppc6xx_idle: */
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stw r9,_NIP(r11) /* make it do a blr */
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@ -0,0 +1,84 @@
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/*
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* Copyright (C) 2008 Freescale Semiconductor, Inc. All rights reserved.
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* Dave Liu <daveliu@freescale.com>
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* copy from idle_6xx.S and modify for e500 based processor,
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* implement the power_save function in idle.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/threads.h>
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#include <asm/reg.h>
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#include <asm/page.h>
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#include <asm/cputable.h>
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#include <asm/thread_info.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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.text
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_GLOBAL(e500_idle)
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rlwinm r3,r1,0,0,31-THREAD_SHIFT /* current thread_info */
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lwz r4,TI_LOCAL_FLAGS(r3) /* set napping bit */
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ori r4,r4,_TLF_NAPPING /* so when we take an exception */
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stw r4,TI_LOCAL_FLAGS(r3) /* it will return to our caller */
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/* Check if we can nap or doze, put HID0 mask in r3 */
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lis r3,0
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BEGIN_FTR_SECTION
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lis r3,HID0_DOZE@h
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END_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE)
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BEGIN_FTR_SECTION
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/* Now check if user enabled NAP mode */
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lis r4,powersave_nap@ha
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lwz r4,powersave_nap@l(r4)
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cmpwi 0,r4,0
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beq 1f
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stwu r1,-16(r1)
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mflr r0
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stw r0,20(r1)
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bl flush_dcache_L1
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lwz r0,20(r1)
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addi r1,r1,16
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mtlr r0
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lis r3,HID0_NAP@h
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END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
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1:
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/* Go to NAP or DOZE now */
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mfspr r4,SPRN_HID0
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rlwinm r4,r4,0,~(HID0_DOZE|HID0_NAP|HID0_SLEEP)
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or r4,r4,r3
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isync
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mtspr SPRN_HID0,r4
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isync
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mfmsr r7
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oris r7,r7,MSR_WE@h
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ori r7,r7,MSR_EE
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msync
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mtmsr r7
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isync
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2: b 2b
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/*
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* Return from NAP/DOZE mode, restore some CPU specific registers,
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* r2 containing physical address of current.
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* r11 points to the exception frame (physical address).
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* We have to preserve r10.
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*/
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_GLOBAL(power_save_ppc32_restore)
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lwz r9,_LINK(r11) /* interrupted in e500_idle */
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stw r9,_NIP(r11) /* make it do a blr */
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#ifdef CONFIG_SMP
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mfspr r12,SPRN_SPRG3
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lwz r11,TI_CPU(r12) /* get cpu number * 4 */
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slwi r11,r11,2
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#else
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li r11,0
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#endif
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b transfer_to_handler_cont
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@ -127,6 +127,11 @@ void __init machine_init(unsigned long dt_ptr, unsigned long phys)
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ppc_md.power_save = ppc6xx_idle;
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#endif
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#ifdef CONFIG_E500
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if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
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cpu_has_feature(CPU_FTR_CAN_NAP))
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ppc_md.power_save = e500_idle;
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#endif
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if (ppc_md.progress)
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ppc_md.progress("id mach(): done", 0x200);
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}
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@ -347,12 +347,13 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
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#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
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CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
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CPU_FTR_UNIFIED_ID_CACHE)
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#define CPU_FTRS_E500 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
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CPU_FTR_NODSISRALIGN)
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#define CPU_FTRS_E500_2 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
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CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
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#define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_BIG_PHYS | \
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#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
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CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN)
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#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
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CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | \
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CPU_FTR_NODSISRALIGN)
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#define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
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CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
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#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
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/* 64-bit CPUs */
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@ -262,6 +262,7 @@ struct machdep_calls {
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#endif
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};
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extern void e500_idle(void);
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extern void power4_idle(void);
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extern void power4_cpu_offline_powersave(void);
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extern void ppc6xx_idle(void);
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@ -240,7 +240,7 @@
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#define HID0_DAPUEN (1<<8) /* Debug APU enable */
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#define HID0_SGE (1<<7) /* Store Gathering Enable */
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#define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */
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#define HID0_DFCA (1<<6) /* Data Cache Flush Assist */
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#define HID0_DCFA (1<<6) /* Data Cache Flush Assist */
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#define HID0_LRSTK (1<<4) /* Link register stack - 745x */
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#define HID0_BTIC (1<<5) /* Branch Target Instr Cache Enable */
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#define HID0_ABE (1<<3) /* Address Broadcast Enable */
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@ -61,6 +61,8 @@
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#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
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#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
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#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
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#define SPRN_L1CFG0 0x203 /* L1 Cache Configure Register 0 */
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#define SPRN_L1CFG1 0x204 /* L1 Cache Configure Register 1 */
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#define SPRN_ATB 0x20E /* Alternate Time Base */
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#define SPRN_ATBL 0x20E /* Alternate Time Base Lower */
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#define SPRN_ATBU 0x20F /* Alternate Time Base Upper */
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