powerpc/booke: Move MMUCSR definition into mmu-book3e.h
The MMUCSR is now defined as part of the Book-3E architecture so we can move it into mmu-book3e.h and add some of the additional bits defined by the architecture specs. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@ -114,6 +114,18 @@
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#define MAS7_RPN 0xFFFFFFFF
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/* Bit definitions for MMUCSR0 */
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#define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
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#define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
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#define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
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#define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
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#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
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MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
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#define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
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#define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
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#define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
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#define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
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/* TLBnCFG encoding */
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#define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
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#define TLBnCFG_HES 0x00002000 /* HW select supported */
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@ -430,12 +430,6 @@
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#define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */
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#define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */
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/* Bit definitions for MMUCSR0 */
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#define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
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#define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
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#define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
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#define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
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/* Bit definitions for SGR. */
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#define SGR_NORMAL 0 /* Speculative fetching allowed. */
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#define SGR_GUARDED 1 /* Speculative fetching disallowed. */
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@ -124,8 +124,6 @@ _GLOBAL(_tlbil_pid)
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* to have the larger code path before the _SECTION_ELSE
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*/
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#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
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MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
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/*
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* Flush MMU TLB on the local processor
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*/
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