powerpc/64s/exception: untangle early machine check handler branch
machine_check_early_common now branches to machine_check_handle_early which is its only caller. Move interleaving code out of the way, and remove the branch. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20190802105709.27696-16-npiggin@gmail.com
This commit is contained in:
Nicholas Piggin
Michael Ellerman
Родитель
b7d9ccec30
Коммит
fce16d4822
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@ -956,6 +956,16 @@ TRAMP_REAL_BEGIN(machine_check_fwnmi)
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TRAMP_KVM_SKIP(PACA_EXMC, 0x200)
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TRAMP_KVM_SKIP(PACA_EXMC, 0x200)
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#define MACHINE_CHECK_HANDLER_WINDUP \
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/* Clear MSR_RI before setting SRR0 and SRR1. */\
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li r9,0; \
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mtmsrd r9,1; /* Clear MSR_RI */ \
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/* Decrement paca->in_mce now RI is clear. */ \
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lhz r12,PACA_IN_MCE(r13); \
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subi r12,r12,1; \
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sth r12,PACA_IN_MCE(r13); \
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EXCEPTION_RESTORE_REGS EXC_STD
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EXC_COMMON_BEGIN(machine_check_early_common)
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EXC_COMMON_BEGIN(machine_check_early_common)
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mtctr r10 /* Restore ctr */
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mtctr r10 /* Restore ctr */
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mfspr r11,SPRN_SRR0
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mfspr r11,SPRN_SRR0
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@ -1011,74 +1021,7 @@ BEGIN_FTR_SECTION
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END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
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END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
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li r10,MSR_RI
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li r10,MSR_RI
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mtmsrd r10,1
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mtmsrd r10,1
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b machine_check_handle_early
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EXC_COMMON_BEGIN(machine_check_common)
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/*
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* Machine check is different because we use a different
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* save area: PACA_EXMC instead of PACA_EXGEN.
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*/
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EXCEPTION_COMMON(PACA_EXMC, 0x200)
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FINISH_NAP
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RECONCILE_IRQ_STATE(r10, r11)
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ld r3,PACA_EXMC+EX_DAR(r13)
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lwz r4,PACA_EXMC+EX_DSISR(r13)
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/* Enable MSR_RI when finished with PACA_EXMC */
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li r10,MSR_RI
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mtmsrd r10,1
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std r3,_DAR(r1)
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std r4,_DSISR(r1)
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bl save_nvgprs
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addi r3,r1,STACK_FRAME_OVERHEAD
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bl machine_check_exception
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b ret_from_except
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#define MACHINE_CHECK_HANDLER_WINDUP \
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/* Clear MSR_RI before setting SRR0 and SRR1. */\
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li r9,0; \
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mtmsrd r9,1; /* Clear MSR_RI */ \
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/* Decrement paca->in_mce now RI is clear. */ \
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lhz r12,PACA_IN_MCE(r13); \
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subi r12,r12,1; \
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sth r12,PACA_IN_MCE(r13); \
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EXCEPTION_RESTORE_REGS EXC_STD
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#ifdef CONFIG_PPC_P7_NAP
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/*
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* This is an idle wakeup. Low level machine check has already been
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* done. Queue the event then call the idle code to do the wake up.
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*/
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EXC_COMMON_BEGIN(machine_check_idle_common)
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bl machine_check_queue_event
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/*
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* We have not used any non-volatile GPRs here, and as a rule
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* most exception code including machine check does not.
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* Therefore PACA_NAPSTATELOST does not need to be set. Idle
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* wakeup will restore volatile registers.
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*
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* Load the original SRR1 into r3 for pnv_powersave_wakeup_mce.
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*
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* Then decrement MCE nesting after finishing with the stack.
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*/
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ld r3,_MSR(r1)
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ld r4,_LINK(r1)
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lhz r11,PACA_IN_MCE(r13)
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subi r11,r11,1
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sth r11,PACA_IN_MCE(r13)
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mtlr r4
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rlwinm r10,r3,47-31,30,31
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cmpwi cr1,r10,2
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bltlr cr1 /* no state loss, return to idle caller */
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b idle_return_gpr_loss
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#endif
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/*
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* Handle machine check early in real mode. We come here with
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* ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack.
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*/
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EXC_COMMON_BEGIN(machine_check_handle_early)
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bl save_nvgprs
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bl save_nvgprs
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addi r3,r1,STACK_FRAME_OVERHEAD
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addi r3,r1,STACK_FRAME_OVERHEAD
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bl machine_check_early
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bl machine_check_early
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@ -1157,6 +1100,58 @@ END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
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EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 1, 0x200, 1, 1, 0
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EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 1, 0x200, 1, 1, 0
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EXCEPTION_PROLOG_2_REAL machine_check_common, EXC_STD, 0
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EXCEPTION_PROLOG_2_REAL machine_check_common, EXC_STD, 0
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EXC_COMMON_BEGIN(machine_check_common)
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/*
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* Machine check is different because we use a different
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* save area: PACA_EXMC instead of PACA_EXGEN.
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*/
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EXCEPTION_COMMON(PACA_EXMC, 0x200)
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FINISH_NAP
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RECONCILE_IRQ_STATE(r10, r11)
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ld r3,PACA_EXMC+EX_DAR(r13)
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lwz r4,PACA_EXMC+EX_DSISR(r13)
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/* Enable MSR_RI when finished with PACA_EXMC */
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li r10,MSR_RI
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mtmsrd r10,1
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std r3,_DAR(r1)
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std r4,_DSISR(r1)
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bl save_nvgprs
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addi r3,r1,STACK_FRAME_OVERHEAD
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bl machine_check_exception
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b ret_from_except
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#ifdef CONFIG_PPC_P7_NAP
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/*
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* This is an idle wakeup. Low level machine check has already been
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* done. Queue the event then call the idle code to do the wake up.
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*/
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EXC_COMMON_BEGIN(machine_check_idle_common)
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bl machine_check_queue_event
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/*
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* We have not used any non-volatile GPRs here, and as a rule
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* most exception code including machine check does not.
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* Therefore PACA_NAPSTATELOST does not need to be set. Idle
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* wakeup will restore volatile registers.
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*
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* Load the original SRR1 into r3 for pnv_powersave_wakeup_mce.
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*
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* Then decrement MCE nesting after finishing with the stack.
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*/
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ld r3,_MSR(r1)
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ld r4,_LINK(r1)
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lhz r11,PACA_IN_MCE(r13)
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subi r11,r11,1
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sth r11,PACA_IN_MCE(r13)
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mtlr r4
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rlwinm r10,r3,47-31,30,31
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cmpwi cr1,r10,2
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bltlr cr1 /* no state loss, return to idle caller */
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b idle_return_gpr_loss
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#endif
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EXC_COMMON_BEGIN(unrecoverable_mce)
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EXC_COMMON_BEGIN(unrecoverable_mce)
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/*
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/*
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* We are going down. But there are chances that we might get hit by
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* We are going down. But there are chances that we might get hit by
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