[SPARC64]: Send all device interrupts via one PIL.
This is the first in a series of cleanups that will hopefully
allow a seamless attempt at using the generic IRQ handling
infrastructure in the Linux kernel.
Define PIL_DEVICE_IRQ and vector all device interrupts through
there.
Get rid of the ugly pil0_dummy_{bucket,desc}, instead vector
the timer interrupt directly to a specific handler since the
timer interrupt is the only event that will be signaled on
PIL 14.
The irq_worklist is now in the per-cpu trap_block[].
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
Родитель
3185d4d287
Коммит
fd0504c321
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@ -22,6 +22,7 @@
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#include <asm/estate.h>
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#include <asm/auxio.h>
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#include <asm/sfafsr.h>
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#include <asm/pil.h>
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#define curptr g6
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@ -434,17 +435,13 @@ do_ivec:
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sllx %g3, 5, %g3
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or %g2, %lo(ivector_table), %g2
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add %g2, %g3, %g3
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ldub [%g3 + 0x04], %g4 /* pil */
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mov 1, %g2
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sllx %g2, %g4, %g2
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sllx %g4, 2, %g4
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TRAP_LOAD_IRQ_WORK(%g6, %g1)
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lduw [%g6 + %g4], %g5 /* g5 = irq_work(cpu, pil) */
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lduw [%g6], %g5 /* g5 = irq_work(cpu) */
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stw %g5, [%g3 + 0x00] /* bucket->irq_chain = g5 */
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stw %g3, [%g6 + %g4] /* irq_work(cpu, pil) = bucket */
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wr %g2, 0x0, %set_softint
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stw %g3, [%g6] /* irq_work(cpu) = bucket */
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wr %g0, 1 << PIL_DEVICE_IRQ, %set_softint
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retry
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do_ivec_xcall:
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mov 0x50, %g1
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@ -68,11 +68,7 @@ struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BY
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* access to this structure takes a TLB miss it could cause
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* the 5-level sparc v9 trap stack to overflow.
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*/
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struct irq_work_struct {
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unsigned int irq_worklists[16];
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};
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struct irq_work_struct __irq_work[NR_CPUS];
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#define irq_work(__cpu, __pil) &(__irq_work[(__cpu)].irq_worklists[(__pil)])
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#define irq_work(__cpu) &(trap_block[(__cpu)].irq_worklist)
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static struct irqaction *irq_action[NR_IRQS+1];
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@ -91,10 +87,8 @@ static void register_irq_proc (unsigned int irq);
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*/
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#define put_ino_in_irqaction(action, irq) \
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action->flags &= 0xffffffffffffUL; \
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if (__bucket(irq) == &pil0_dummy_bucket) \
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action->flags |= 0xdeadUL << 48; \
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else \
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action->flags |= __irq_ino(irq) << 48;
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action->flags |= __irq_ino(irq) << 48;
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#define get_ino_in_irqaction(action) (action->flags >> 48)
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#define put_smpaff_in_irqaction(action, smpaff) (action)->mask = (smpaff)
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@ -251,15 +245,6 @@ void disable_irq(unsigned int irq)
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}
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}
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/* The timer is the one "weird" interrupt which is generated by
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* the CPU %tick register and not by some normal vectored interrupt
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* source. To handle this special case, we use this dummy INO bucket.
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*/
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static struct irq_desc pil0_dummy_desc;
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static struct ino_bucket pil0_dummy_bucket = {
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.irq_info = &pil0_dummy_desc,
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};
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static void build_irq_error(const char *msg, unsigned int ino, int pil, int inofixup,
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unsigned long iclr, unsigned long imap,
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struct ino_bucket *bucket)
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@ -276,15 +261,7 @@ unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long
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struct ino_bucket *bucket;
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int ino;
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if (pil == 0) {
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if (iclr != 0UL || imap != 0UL) {
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prom_printf("Invalid dummy bucket for PIL0 (%lx:%lx)\n",
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iclr, imap);
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prom_halt();
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}
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return __irq(&pil0_dummy_bucket);
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}
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BUG_ON(pil == 0);
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BUG_ON(tlb_type == hypervisor);
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/* RULE: Both must be specified in all other cases. */
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@ -371,7 +348,7 @@ static void atomic_bucket_insert(struct ino_bucket *bucket)
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__asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
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__asm__ __volatile__("wrpr %0, %1, %%pstate"
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: : "r" (pstate), "i" (PSTATE_IE));
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ent = irq_work(smp_processor_id(), bucket->pil);
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ent = irq_work(smp_processor_id());
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bucket->irq_chain = *ent;
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*ent = __irq(bucket);
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__asm__ __volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate));
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@ -437,7 +414,7 @@ int request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_
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if (unlikely(!bucket->irq_info))
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return -ENODEV;
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if ((bucket != &pil0_dummy_bucket) && (irqflags & SA_SAMPLE_RANDOM)) {
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if (irqflags & SA_SAMPLE_RANDOM) {
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/*
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* This function might sleep, we want to call it first,
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* outside of the atomic block. In SA_STATIC_ALLOC case,
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@ -465,12 +442,9 @@ int request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_
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}
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bucket->flags |= IBF_ACTIVE;
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pending = 0;
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if (bucket != &pil0_dummy_bucket) {
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pending = bucket->pending;
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if (pending)
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bucket->pending = 0;
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}
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pending = bucket->pending;
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if (pending)
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bucket->pending = 0;
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action->handler = handler;
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action->flags = irqflags;
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@ -487,13 +461,12 @@ int request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_
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/* We ate the IVEC already, this makes sure it does not get lost. */
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if (pending) {
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atomic_bucket_insert(bucket);
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set_softint(1 << bucket->pil);
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set_softint(1 << PIL_DEVICE_IRQ);
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}
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spin_unlock_irqrestore(&irq_action_lock, flags);
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if (bucket != &pil0_dummy_bucket)
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register_irq_proc(__irq_ino(irq));
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register_irq_proc(__irq_ino(irq));
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#ifdef CONFIG_SMP
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distribute_irqs();
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@ -533,7 +506,9 @@ void free_irq(unsigned int irq, void *dev_id)
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{
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struct irqaction *action;
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struct ino_bucket *bucket;
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struct irq_desc *desc;
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unsigned long flags;
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int ent, i;
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spin_lock_irqsave(&irq_action_lock, flags);
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@ -549,42 +524,39 @@ void free_irq(unsigned int irq, void *dev_id)
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spin_lock_irqsave(&irq_action_lock, flags);
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bucket = __bucket(irq);
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if (bucket != &pil0_dummy_bucket) {
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struct irq_desc *desc = bucket->irq_info;
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int ent, i;
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desc = bucket->irq_info;
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for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) {
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struct irqaction *p = &desc->action[i];
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for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) {
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struct irqaction *p = &desc->action[i];
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if (p == action) {
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desc->action_active_mask &= ~(1 << i);
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if (p == action) {
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desc->action_active_mask &= ~(1 << i);
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break;
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}
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}
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if (!desc->action_active_mask) {
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unsigned long imap = bucket->imap;
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/* This unique interrupt source is now inactive. */
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bucket->flags &= ~IBF_ACTIVE;
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/* See if any other buckets share this bucket's IMAP
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* and are still active.
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*/
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for (ent = 0; ent < NUM_IVECS; ent++) {
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struct ino_bucket *bp = &ivector_table[ent];
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if (bp != bucket &&
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bp->imap == imap &&
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(bp->flags & IBF_ACTIVE) != 0)
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break;
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}
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}
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if (!desc->action_active_mask) {
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unsigned long imap = bucket->imap;
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/* This unique interrupt source is now inactive. */
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bucket->flags &= ~IBF_ACTIVE;
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/* See if any other buckets share this bucket's IMAP
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* and are still active.
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*/
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for (ent = 0; ent < NUM_IVECS; ent++) {
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struct ino_bucket *bp = &ivector_table[ent];
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if (bp != bucket &&
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bp->imap == imap &&
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(bp->flags & IBF_ACTIVE) != 0)
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break;
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}
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/* Only disable when no other sub-irq levels of
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* the same IMAP are active.
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*/
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if (ent == NUM_IVECS)
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disable_irq(irq);
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}
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/* Only disable when no other sub-irq levels of
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* the same IMAP are active.
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*/
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if (ent == NUM_IVECS)
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disable_irq(irq);
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}
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spin_unlock_irqrestore(&irq_action_lock, flags);
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@ -625,7 +597,7 @@ void synchronize_irq(unsigned int irq)
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}
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#endif /* CONFIG_SMP */
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static void process_bucket(int irq, struct ino_bucket *bp, struct pt_regs *regs)
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static void process_bucket(struct ino_bucket *bp, struct pt_regs *regs)
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{
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struct irq_desc *desc = bp->irq_info;
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unsigned char flags = bp->flags;
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@ -676,51 +648,54 @@ static void process_bucket(int irq, struct ino_bucket *bp, struct pt_regs *regs)
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/* Test and add entropy */
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if (random & SA_SAMPLE_RANDOM)
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add_interrupt_randomness(irq);
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add_interrupt_randomness(bp->pil);
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}
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out:
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bp->flags &= ~IBF_INPROGRESS;
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}
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#ifndef CONFIG_SMP
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extern irqreturn_t timer_interrupt(int, void *, struct pt_regs *);
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void timer_irq(int irq, struct pt_regs *regs)
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{
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unsigned long clr_mask = 1 << irq;
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unsigned long tick_mask = tick_ops->softint_mask;
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if (get_softint() & tick_mask) {
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irq = 0;
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clr_mask = tick_mask;
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}
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clear_softint(clr_mask);
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irq_enter();
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kstat_this_cpu.irqs[irq]++;
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timer_interrupt(irq, NULL, regs);
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irq_exit();
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}
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#endif
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void handler_irq(int irq, struct pt_regs *regs)
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{
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struct ino_bucket *bp;
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int cpu = smp_processor_id();
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#ifndef CONFIG_SMP
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/*
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* Check for TICK_INT on level 14 softint.
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/* XXX at this point we should be able to assert that
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* XXX irq is PIL_DEVICE_IRQ...
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*/
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{
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unsigned long clr_mask = 1 << irq;
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unsigned long tick_mask = tick_ops->softint_mask;
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if ((irq == 14) && (get_softint() & tick_mask)) {
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irq = 0;
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clr_mask = tick_mask;
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}
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clear_softint(clr_mask);
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}
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#else
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clear_softint(1 << irq);
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#endif
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irq_enter();
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kstat_this_cpu.irqs[irq]++;
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/* Sliiiick... */
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#ifndef CONFIG_SMP
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bp = ((irq != 0) ?
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__bucket(xchg32(irq_work(cpu, irq), 0)) :
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&pil0_dummy_bucket);
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#else
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bp = __bucket(xchg32(irq_work(cpu, irq), 0));
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#endif
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bp = __bucket(xchg32(irq_work(cpu), 0));
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while (bp) {
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struct ino_bucket *nbp = __bucket(bp->irq_chain);
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kstat_this_cpu.irqs[bp->pil]++;
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bp->irq_chain = 0;
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process_bucket(irq, bp, regs);
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process_bucket(bp, regs);
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bp = nbp;
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}
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irq_exit();
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@ -929,7 +904,7 @@ void init_irqwork_curcpu(void)
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{
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int cpu = hard_smp_processor_id();
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memset(__irq_work + cpu, 0, sizeof(struct irq_work_struct));
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trap_block[cpu].irq_worklist = 0;
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}
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static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type)
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@ -5,6 +5,7 @@
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#include <asm/cpudata.h>
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#include <asm/intr_queue.h>
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#include <asm/pil.h>
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.text
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.align 32
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@ -106,19 +107,13 @@ sun4v_dev_mondo:
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or %g4, %lo(ivector_table), %g4
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add %g4, %g3, %g4
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/* Load IRQ %pil into %g5. */
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ldub [%g4 + 0x04], %g5
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/* Insert ivector_table[] entry into __irq_work[] queue. */
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sllx %g5, 2, %g3
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lduw [%g1 + %g3], %g2 /* g2 = irq_work(cpu, pil) */
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lduw [%g1], %g2 /* g2 = irq_work(cpu) */
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stw %g2, [%g4 + 0x00] /* bucket->irq_chain = g2 */
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stw %g4, [%g1 + %g3] /* irq_work(cpu, pil) = bucket */
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stw %g4, [%g1] /* irq_work(cpu) = bucket */
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/* Signal the interrupt by setting (1 << pil) in %softint. */
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mov 1, %g2
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sllx %g2, %g5, %g2
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wr %g2, 0x0, %set_softint
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wr %g0, 1 << PIL_DEVICE_IRQ, %set_softint
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sun4v_dev_mondo_queue_empty:
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retry
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|
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|
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@ -457,7 +457,7 @@ static inline void timer_check_rtc(void)
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}
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}
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static irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs * regs)
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irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs * regs)
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{
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unsigned long ticks, compare, pstate;
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|
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@ -1020,19 +1020,9 @@ static unsigned long sparc64_init_timers(void)
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return clock;
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}
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static void sparc64_start_timers(irqreturn_t (*cfunc)(int, void *, struct pt_regs *))
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static void sparc64_start_timers(void)
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{
|
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unsigned long pstate;
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int err;
|
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|
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/* Register IRQ handler. */
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err = request_irq(build_irq(0, 0, 0UL, 0UL), cfunc, 0,
|
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"timer", NULL);
|
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if (err) {
|
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prom_printf("Serious problem, cannot register TICK_INT\n");
|
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prom_halt();
|
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}
|
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|
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/* Guarantee that the following sequences execute
|
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* uninterrupted.
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|
|
@ -1116,7 +1106,7 @@ void __init time_init(void)
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/* Now that the interpolator is registered, it is
|
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* safe to start the timer ticking.
|
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*/
|
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sparc64_start_timers(timer_interrupt);
|
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sparc64_start_timers();
|
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|
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timer_ticks_per_nsec_quotient =
|
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(((NSEC_PER_SEC << SPARC64_NSEC_PER_CYC_SHIFT) +
|
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|
|
|
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|
|
@ -2544,7 +2544,9 @@ void __init trap_init(void)
|
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(TRAP_PER_CPU_TSB_HUGE !=
|
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offsetof(struct trap_per_cpu, tsb_huge)) ||
|
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(TRAP_PER_CPU_TSB_HUGE_TEMP !=
|
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offsetof(struct trap_per_cpu, tsb_huge_temp)))
|
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offsetof(struct trap_per_cpu, tsb_huge_temp)) ||
|
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(TRAP_PER_CPU_IRQ_WORKLIST !=
|
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offsetof(struct trap_per_cpu, irq_worklist)))
|
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trap_per_cpu_offsets_are_bolixed_dave();
|
||||
|
||||
if ((TSB_CONFIG_TSB !=
|
||||
|
|
|
|||
|
|
@ -58,13 +58,11 @@ tl0_irq2: BTRAP(0x42)
|
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tl0_irq3: BTRAP(0x43)
|
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tl0_irq4: BTRAP(0x44)
|
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#endif
|
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tl0_irq5: TRAP_IRQ(handler_irq, 5) TRAP_IRQ(handler_irq, 6)
|
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tl0_irq7: TRAP_IRQ(handler_irq, 7) TRAP_IRQ(handler_irq, 8)
|
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tl0_irq9: TRAP_IRQ(handler_irq, 9) TRAP_IRQ(handler_irq, 10)
|
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tl0_irq11: TRAP_IRQ(handler_irq, 11) TRAP_IRQ(handler_irq, 12)
|
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tl0_irq13: TRAP_IRQ(handler_irq, 13)
|
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tl0_irq5: TRAP_IRQ(handler_irq, 5)
|
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tl0_irq6: BTRAP(0x46) BTRAP(0x47) BTRAP(0x48) BTRAP(0x49)
|
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tl0_irq10: BTRAP(0x4a) BTRAP(0x4b) BTRAP(0x4c) BTRAP(0x4d)
|
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#ifndef CONFIG_SMP
|
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tl0_irq14: TRAP_IRQ(handler_irq, 14)
|
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tl0_irq14: TRAP_IRQ(timer_irq, 14)
|
||||
#else
|
||||
tl0_irq14: TICK_SMP_IRQ
|
||||
#endif
|
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|
|
|
|||
|
|
@ -74,8 +74,10 @@ struct trap_per_cpu {
|
|||
unsigned long tsb_huge;
|
||||
unsigned long tsb_huge_temp;
|
||||
|
||||
/* Dcache line 8: Unused, needed to keep trap_block a power-of-2 in size. */
|
||||
unsigned long __pad2[4];
|
||||
/* Dcache line 8: IRQ work list, and keep trap_block a power-of-2 in size. */
|
||||
unsigned int irq_worklist;
|
||||
unsigned int __pad1;
|
||||
unsigned long __pad2[3];
|
||||
} __attribute__((aligned(64)));
|
||||
extern struct trap_per_cpu trap_block[NR_CPUS];
|
||||
extern void init_cur_cpu_trap(struct thread_info *);
|
||||
|
|
@ -119,6 +121,7 @@ extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
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|||
#define TRAP_PER_CPU_CPU_LIST_PA 0xc8
|
||||
#define TRAP_PER_CPU_TSB_HUGE 0xd0
|
||||
#define TRAP_PER_CPU_TSB_HUGE_TEMP 0xd8
|
||||
#define TRAP_PER_CPU_IRQ_WORKLIST 0xe0
|
||||
|
||||
#define TRAP_BLOCK_SZ_SHIFT 8
|
||||
|
||||
|
|
@ -171,11 +174,8 @@ extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
|
|||
|
||||
/* Clobbers TMP, loads local processor's IRQ work area into DEST. */
|
||||
#define TRAP_LOAD_IRQ_WORK(DEST, TMP) \
|
||||
__GET_CPUID(TMP) \
|
||||
sethi %hi(__irq_work), DEST; \
|
||||
sllx TMP, 6, TMP; \
|
||||
or DEST, %lo(__irq_work), DEST; \
|
||||
add DEST, TMP, DEST;
|
||||
TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
|
||||
add DEST, TRAP_PER_CPU_IRQ_WORKLIST, DEST;
|
||||
|
||||
/* Clobbers TMP, loads DEST with current thread info pointer. */
|
||||
#define TRAP_LOAD_THREAD_REG(DEST, TMP) \
|
||||
|
|
@ -211,9 +211,10 @@ extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
|
|||
TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
|
||||
ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
|
||||
|
||||
/* Clobbers TMP, loads local processor's IRQ work area into DEST. */
|
||||
#define TRAP_LOAD_IRQ_WORK(DEST, TMP) \
|
||||
sethi %hi(__irq_work), DEST; \
|
||||
or DEST, %lo(__irq_work), DEST;
|
||||
TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
|
||||
add DEST, TRAP_PER_CPU_IRQ_WORKLIST, DEST;
|
||||
|
||||
#define TRAP_LOAD_THREAD_REG(DEST, TMP) \
|
||||
TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
|
||||
|
|
|
|||
|
|
@ -5,9 +5,9 @@
|
|||
/* To avoid some locking problems, we hard allocate certain PILs
|
||||
* for SMP cross call messages that must do a etrap/rtrap.
|
||||
*
|
||||
* A cli() does not block the cross call delivery, so when SMP
|
||||
* locking is an issue we reschedule the event into a PIL interrupt
|
||||
* which is blocked by cli().
|
||||
* A local_irq_disable() does not block the cross call delivery, so
|
||||
* when SMP locking is an issue we reschedule the event into a PIL
|
||||
* interrupt which is blocked by local_irq_disable().
|
||||
*
|
||||
* In fact any XCALL which has to etrap/rtrap has a problem because
|
||||
* it is difficult to prevent rtrap from running BH's, and that would
|
||||
|
|
@ -17,6 +17,7 @@
|
|||
#define PIL_SMP_RECEIVE_SIGNAL 2
|
||||
#define PIL_SMP_CAPTURE 3
|
||||
#define PIL_SMP_CTX_NEW_VERSION 4
|
||||
#define PIL_DEVICE_IRQ 5
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#define PIL_RESERVED(PIL) ((PIL) == PIL_SMP_CALL_FUNC || \
|
||||
|
|
|
|||
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