x86/entry: Remove DBn stacks
Both #DB itself, as all other IST users (NMI, #MC) now clear DR7 on entry. Combined with not allowing breakpoints on entry/noinstr/NOKPROBE text and no single step (EFLAGS.TF) inside the #DB handler should guarantee no nested #DB. Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lkml.kernel.org/r/20200529213321.303027161@infradead.org
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@ -396,11 +396,6 @@ SYM_CODE_END(\asmsym)
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idtentry \vector asm_\cfunc \cfunc has_error_code=0
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.endm
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/*
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* MCE and DB exceptions
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*/
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#define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss_rw) + (TSS_ist + (x) * 8)
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/**
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* idtentry_mce_db - Macro to generate entry stubs for #MC and #DB
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* @vector: Vector number
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@ -416,10 +411,6 @@ SYM_CODE_END(\asmsym)
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* If hits in kernel mode then it needs to go through the paranoid
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* entry as the exception can hit any random state. No preemption
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* check on exit to keep the paranoid path simple.
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*
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* If the trap is #DB then the interrupt stack entry in the IST is
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* moved to the second stack, so a potential recursion will have a
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* fresh IST.
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*/
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.macro idtentry_mce_db vector asmsym cfunc
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SYM_CODE_START(\asmsym)
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@ -445,16 +436,8 @@ SYM_CODE_START(\asmsym)
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movq %rsp, %rdi /* pt_regs pointer */
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.if \vector == X86_TRAP_DB
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subq $DB_STACK_OFFSET, CPU_TSS_IST(IST_INDEX_DB)
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.endif
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call \cfunc
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.if \vector == X86_TRAP_DB
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addq $DB_STACK_OFFSET, CPU_TSS_IST(IST_INDEX_DB)
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.endif
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jmp paranoid_exit
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/* Switch to the regular task stack and use the noist entry point */
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@ -11,15 +11,11 @@
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#ifdef CONFIG_X86_64
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/* Macro to enforce the same ordering and stack sizes */
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#define ESTACKS_MEMBERS(guardsize, db2_holesize)\
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#define ESTACKS_MEMBERS(guardsize) \
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char DF_stack_guard[guardsize]; \
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char DF_stack[EXCEPTION_STKSZ]; \
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char NMI_stack_guard[guardsize]; \
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char NMI_stack[EXCEPTION_STKSZ]; \
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char DB2_stack_guard[guardsize]; \
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char DB2_stack[db2_holesize]; \
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char DB1_stack_guard[guardsize]; \
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char DB1_stack[EXCEPTION_STKSZ]; \
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char DB_stack_guard[guardsize]; \
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char DB_stack[EXCEPTION_STKSZ]; \
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char MCE_stack_guard[guardsize]; \
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@ -28,12 +24,12 @@
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/* The exception stacks' physical storage. No guard pages required */
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struct exception_stacks {
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ESTACKS_MEMBERS(0, 0)
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ESTACKS_MEMBERS(0)
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};
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/* The effective cpu entry area mapping with guard pages. */
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struct cea_exception_stacks {
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ESTACKS_MEMBERS(PAGE_SIZE, EXCEPTION_STKSZ)
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ESTACKS_MEMBERS(PAGE_SIZE)
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};
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/*
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@ -42,8 +38,6 @@ struct cea_exception_stacks {
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enum exception_stack_ordering {
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ESTACK_DF,
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ESTACK_NMI,
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ESTACK_DB2,
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ESTACK_DB1,
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ESTACK_DB,
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ESTACK_MCE,
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N_EXCEPTION_STACKS
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@ -57,9 +57,6 @@ int main(void)
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BLANK();
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#undef ENTRY
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OFFSET(TSS_ist, tss_struct, x86_tss.ist);
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DEFINE(DB_STACK_OFFSET, offsetof(struct cea_exception_stacks, DB_stack) -
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offsetof(struct cea_exception_stacks, DB1_stack));
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BLANK();
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#ifdef CONFIG_STACKPROTECTOR
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@ -22,15 +22,13 @@
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static const char * const exception_stack_names[] = {
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[ ESTACK_DF ] = "#DF",
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[ ESTACK_NMI ] = "NMI",
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[ ESTACK_DB2 ] = "#DB2",
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[ ESTACK_DB1 ] = "#DB1",
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[ ESTACK_DB ] = "#DB",
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[ ESTACK_MCE ] = "#MC",
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};
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const char *stack_type_name(enum stack_type type)
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{
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BUILD_BUG_ON(N_EXCEPTION_STACKS != 6);
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BUILD_BUG_ON(N_EXCEPTION_STACKS != 4);
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if (type == STACK_TYPE_IRQ)
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return "IRQ";
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@ -79,7 +77,6 @@ static const
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struct estack_pages estack_pages[CEA_ESTACK_PAGES] ____cacheline_aligned = {
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EPAGERANGE(DF),
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EPAGERANGE(NMI),
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EPAGERANGE(DB1),
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EPAGERANGE(DB),
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EPAGERANGE(MCE),
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};
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@ -91,7 +88,7 @@ static bool in_exception_stack(unsigned long *stack, struct stack_info *info)
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struct pt_regs *regs;
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unsigned int k;
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BUILD_BUG_ON(N_EXCEPTION_STACKS != 6);
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BUILD_BUG_ON(N_EXCEPTION_STACKS != 4);
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begin = (unsigned long)__this_cpu_read(cea_exception_stacks);
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/*
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@ -107,7 +107,6 @@ static void __init percpu_setup_exception_stacks(unsigned int cpu)
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*/
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cea_map_stack(DF);
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cea_map_stack(NMI);
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cea_map_stack(DB1);
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cea_map_stack(DB);
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cea_map_stack(MCE);
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}
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