KVM: MMU: Expose the LA57 feature to VM.
This patch exposes 5 level page table feature to the VM. At the same time, the canonical virtual address checking is extended to support both 48-bits and 57-bits address width. Signed-off-by: Yu Zhang <yu.c.zhang@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Yu Zhang
Paolo Bonzini
Родитель
855feb6736
Коммит
fd8cb43373
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@ -85,8 +85,8 @@
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| X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
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| X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \
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| X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \
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| X86_CR4_OSXMMEXCPT | X86_CR4_VMXE | X86_CR4_SMAP \
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| X86_CR4_PKE))
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| X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \
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| X86_CR4_SMAP | X86_CR4_PKE))
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#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
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@ -1300,20 +1300,6 @@ static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code)
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kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
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}
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static inline u64 get_canonical(u64 la)
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{
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return ((int64_t)la << 16) >> 16;
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}
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static inline bool is_noncanonical_address(u64 la)
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{
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#ifdef CONFIG_X86_64
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return get_canonical(la) != la;
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#else
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return false;
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#endif
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}
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#define TSS_IOPB_BASE_OFFSET 0x66
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#define TSS_BASE_SIZE 0x68
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#define TSS_IOPB_SIZE (65536 / 8)
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@ -126,13 +126,16 @@ int kvm_update_cpuid(struct kvm_vcpu *vcpu)
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best->ebx = xstate_required_size(vcpu->arch.xcr0, true);
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/*
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* The existing code assumes virtual address is 48-bit in the canonical
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* address checks; exit if it is ever changed.
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* The existing code assumes virtual address is 48-bit or 57-bit in the
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* canonical address checks; exit if it is ever changed.
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*/
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best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
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if (best && ((best->eax & 0xff00) >> 8) != 48 &&
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((best->eax & 0xff00) >> 8) != 0)
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return -EINVAL;
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if (best) {
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int vaddr_bits = (best->eax & 0xff00) >> 8;
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if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0)
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return -EINVAL;
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}
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/* Update physical-address width */
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vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
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@ -384,7 +387,8 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
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/* cpuid 7.0.ecx*/
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const u32 kvm_cpuid_7_0_ecx_x86_features =
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F(AVX512VBMI) | F(PKU) | 0 /*OSPKE*/ | F(AVX512_VPOPCNTDQ);
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F(AVX512VBMI) | F(LA57) | F(PKU) |
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0 /*OSPKE*/ | F(AVX512_VPOPCNTDQ);
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/* cpuid 7.0.edx*/
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const u32 kvm_cpuid_7_0_edx_x86_features =
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@ -689,16 +689,18 @@ static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
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ulong la;
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u32 lim;
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u16 sel;
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u8 va_bits;
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la = seg_base(ctxt, addr.seg) + addr.ea;
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*max_size = 0;
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switch (mode) {
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case X86EMUL_MODE_PROT64:
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*linear = la;
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if (is_noncanonical_address(la))
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va_bits = ctxt_virt_addr_bits(ctxt);
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if (get_canonical(la, va_bits) != la)
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goto bad;
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*max_size = min_t(u64, ~0u, (1ull << 48) - la);
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*max_size = min_t(u64, ~0u, (1ull << va_bits) - la);
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if (size > *max_size)
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goto bad;
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break;
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@ -1749,8 +1751,8 @@ static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
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sizeof(base3), &ctxt->exception);
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if (ret != X86EMUL_CONTINUE)
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return ret;
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if (is_noncanonical_address(get_desc_base(&seg_desc) |
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((u64)base3 << 32)))
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if (emul_is_noncanonical_address(get_desc_base(&seg_desc) |
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((u64)base3 << 32), ctxt))
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return emulate_gp(ctxt, 0);
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}
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load:
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@ -2841,8 +2843,8 @@ static int em_sysexit(struct x86_emulate_ctxt *ctxt)
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ss_sel = cs_sel + 8;
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cs.d = 0;
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cs.l = 1;
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if (is_noncanonical_address(rcx) ||
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is_noncanonical_address(rdx))
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if (emul_is_noncanonical_address(rcx, ctxt) ||
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emul_is_noncanonical_address(rdx, ctxt))
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return emulate_gp(ctxt, 0);
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break;
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}
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@ -3757,7 +3759,7 @@ static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt)
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if (rc != X86EMUL_CONTINUE)
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return rc;
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if (ctxt->mode == X86EMUL_MODE_PROT64 &&
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is_noncanonical_address(desc_ptr.address))
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emul_is_noncanonical_address(desc_ptr.address, ctxt))
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return emulate_gp(ctxt, 0);
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if (lgdt)
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ctxt->ops->set_gdt(ctxt, &desc_ptr);
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@ -4,7 +4,7 @@
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#define KVM_POSSIBLE_CR0_GUEST_BITS X86_CR0_TS
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#define KVM_POSSIBLE_CR4_GUEST_BITS \
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(X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
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| X86_CR4_OSXMMEXCPT | X86_CR4_PGE)
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| X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_PGE)
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static inline unsigned long kvm_register_read(struct kvm_vcpu *vcpu,
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enum kvm_reg reg)
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@ -122,7 +122,7 @@ module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
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(KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
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#define KVM_CR4_GUEST_OWNED_BITS \
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(X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
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| X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
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| X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
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#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
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#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
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@ -3374,7 +3374,7 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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(!msr_info->host_initiated &&
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!guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
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return 1;
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if (is_noncanonical_address(data & PAGE_MASK) ||
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if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
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(data & MSR_IA32_BNDCFGS_RSVD))
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return 1;
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vmcs_write64(GUEST_BNDCFGS, data);
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@ -7143,7 +7143,7 @@ static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
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* non-canonical form. This is the only check on the memory
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* destination for long mode!
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*/
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exn = is_noncanonical_address(*ret);
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exn = is_noncanonical_address(*ret, vcpu);
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} else if (is_protmode(vcpu)) {
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/* Protected mode: apply checks for segment validity in the
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* following order:
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@ -7948,7 +7948,7 @@ static int handle_invvpid(struct kvm_vcpu *vcpu)
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switch (type) {
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case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
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if (is_noncanonical_address(operand.gla)) {
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if (is_noncanonical_address(operand.gla, vcpu)) {
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nested_vmx_failValid(vcpu,
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VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
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return kvm_skip_emulated_instruction(vcpu);
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@ -769,6 +769,9 @@ int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
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if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
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return 1;
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if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
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return 1;
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if (is_long_mode(vcpu)) {
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if (!(cr4 & X86_CR4_PAE))
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return 1;
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@ -1074,7 +1077,7 @@ int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
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case MSR_KERNEL_GS_BASE:
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case MSR_CSTAR:
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case MSR_LSTAR:
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if (is_noncanonical_address(msr->data))
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if (is_noncanonical_address(msr->data, vcpu))
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return 1;
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break;
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case MSR_IA32_SYSENTER_EIP:
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@ -1091,7 +1094,7 @@ int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
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* value, and that something deterministic happens if the guest
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* invokes 64-bit SYSENTER.
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*/
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msr->data = get_canonical(msr->data);
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msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
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}
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return kvm_x86_ops->set_msr(vcpu, msr);
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}
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@ -97,6 +97,40 @@ static inline u32 bit(int bitno)
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return 1 << (bitno & 31);
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}
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static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu)
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{
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return kvm_read_cr4_bits(vcpu, X86_CR4_LA57) ? 57 : 48;
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}
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static inline u8 ctxt_virt_addr_bits(struct x86_emulate_ctxt *ctxt)
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{
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return (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_LA57) ? 57 : 48;
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}
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static inline u64 get_canonical(u64 la, u8 vaddr_bits)
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{
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return ((int64_t)la << (64 - vaddr_bits)) >> (64 - vaddr_bits);
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}
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static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu)
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{
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#ifdef CONFIG_X86_64
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return get_canonical(la, vcpu_virt_addr_bits(vcpu)) != la;
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#else
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return false;
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#endif
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}
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static inline bool emul_is_noncanonical_address(u64 la,
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struct x86_emulate_ctxt *ctxt)
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{
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#ifdef CONFIG_X86_64
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return get_canonical(la, ctxt_virt_addr_bits(ctxt)) != la;
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#else
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return false;
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#endif
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}
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static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu,
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gva_t gva, gfn_t gfn, unsigned access)
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{
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