[ARM] 5460/1: Orion: reduce namespace pollution
Symbols like SOFT_RESET are way too generic to be exported at large. To avoid this, let's move the mbus bridge register defines into a separate file and include it where needed. This affects mach-kirkwood, mach-loki, mach-mv78xx0 and mach-orion5x simultaneously as they all share code in plat-orion which relies on those defines. Some other defines have been moved to narrower scopes, or simply deleted when they had no user. This fixes compilation problem with mpt2sas on the above listed platforms. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Nicolas Pitre
Russell King
Родитель
ae1036a2f4
Коммит
fdd8b079e3
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@ -23,6 +23,7 @@
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <mach/kirkwood.h>
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#include <mach/bridge-regs.h>
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#include <plat/cache-feroceon-l2.h>
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#include <plat/ehci-orion.h>
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#include <plat/mvsdio.h>
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@ -0,0 +1,42 @@
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/*
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* arch/arm/mach-kirkwood/include/mach/bridge-regs.h
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*
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* Mbus-L to Mbus Bridge Registers
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_BRIDGE_REGS_H
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#define __ASM_ARCH_BRIDGE_REGS_H
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#include <mach/kirkwood.h>
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#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
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#define CPU_RESET 0x00000002
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#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
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#define SOFT_RESET_OUT_EN 0x00000004
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#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
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#define SOFT_RESET 0x00000001
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#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
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#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
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#define BRIDGE_INT_TIMER0 0x0002
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#define BRIDGE_INT_TIMER1 0x0004
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#define BRIDGE_INT_TIMER1_CLR (~0x0004)
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#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
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#define IRQ_CAUSE_LOW_OFF 0x0000
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#define IRQ_MASK_LOW_OFF 0x0004
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#define IRQ_CAUSE_HIGH_OFF 0x0010
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#define IRQ_MASK_HIGH_OFF 0x0014
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#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
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#define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128)
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#define L2_WRITETHROUGH 0x00000010
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#endif
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@ -6,7 +6,7 @@
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* published by the Free Software Foundation.
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*/
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#include <mach/kirkwood.h>
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#include <mach/bridge-regs.h>
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.macro addruart,rx
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mrc p15, 0, \rx, c1, c0
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@ -8,7 +8,7 @@
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* warranty of any kind, whether express or implied.
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*/
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#include <mach/kirkwood.h>
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#include <mach/bridge-regs.h>
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.macro disable_fiq
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.endm
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@ -43,44 +43,6 @@
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#define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000
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#define KIRKWOOD_PCIE_MEM_SIZE SZ_128M
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/*
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* MBUS bridge registers.
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*/
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#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
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#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
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#define CPU_RESET 0x00000002
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#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
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#define SOFT_RESET_OUT_EN 0x00000004
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#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
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#define SOFT_RESET 0x00000001
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#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
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#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
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#define BRIDGE_INT_TIMER0 0x0002
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#define BRIDGE_INT_TIMER1 0x0004
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#define BRIDGE_INT_TIMER1_CLR (~0x0004)
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#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
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#define IRQ_CAUSE_LOW_OFF 0x0000
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#define IRQ_MASK_LOW_OFF 0x0004
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#define IRQ_CAUSE_HIGH_OFF 0x0010
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#define IRQ_MASK_HIGH_OFF 0x0014
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#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
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#define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128)
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#define L2_WRITETHROUGH 0x00000010
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/*
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* Supported devices and revisions.
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*/
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#define MV88F6281_DEV_ID 0x6281
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#define MV88F6281_REV_Z0 0
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#define MV88F6281_REV_A0 2
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#define MV88F6192_DEV_ID 0x6192
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#define MV88F6192_REV_Z0 0
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#define MV88F6192_REV_A0 2
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#define MV88F6180_DEV_ID 0x6180
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#define MV88F6180_REV_A0 2
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/*
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* Register Map
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*/
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@ -99,6 +61,8 @@
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#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100)
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#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100)
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#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
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#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
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#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
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@ -119,5 +83,18 @@
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#define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x90000)
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/*
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* Supported devices and revisions.
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*/
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#define MV88F6281_DEV_ID 0x6281
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#define MV88F6281_REV_Z0 0
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#define MV88F6281_REV_A0 2
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#define MV88F6192_DEV_ID 0x6192
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#define MV88F6192_REV_Z0 0
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#define MV88F6192_REV_A0 2
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#define MV88F6180_DEV_ID 0x6180
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#define MV88F6180_REV_A0 2
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#endif
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@ -9,8 +9,7 @@
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#ifndef __ASM_ARCH_SYSTEM_H
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#define __ASM_ARCH_SYSTEM_H
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#include <mach/hardware.h>
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#include <mach/kirkwood.h>
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#include <mach/bridge-regs.h>
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static inline void arch_idle(void)
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{
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@ -12,6 +12,7 @@
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <mach/bridge-regs.h>
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#include <plat/irq.h>
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#include <asm/gpio.h>
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#include "common.h"
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@ -38,6 +38,7 @@
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/*
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* CPU Address Decode Windows registers
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*/
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#define BRIDGE_REG(x) (BRIDGE_VIRT_BASE | (x))
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#define CPU_WIN_CTRL(n) BRIDGE_REG(0x000 | ((n) << 4))
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#define CPU_WIN_BASE(n) BRIDGE_REG(0x004 | ((n) << 4))
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#define CPU_WIN_REMAP_LO(n) BRIDGE_REG(0x008 | ((n) << 4))
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@ -0,0 +1,33 @@
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/*
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* arch/arm/mach-loki/include/mach/bridge-regs.h
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_BRIDGE_REGS_H
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#define __ASM_ARCH_BRIDGE_REGS_H
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#include <mach/loki.h>
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#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
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#define SOFT_RESET_OUT_EN 0x00000004
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#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
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#define SOFT_RESET 0x00000001
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#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
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#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
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#define BRIDGE_INT_TIMER0 0x0002
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#define BRIDGE_INT_TIMER1 0x0004
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#define BRIDGE_INT_TIMER1_CLR 0x0004
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#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
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#define IRQ_CAUSE_OFF 0x0000
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#define IRQ_MASK_OFF 0x0004
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#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
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#endif
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@ -8,7 +8,7 @@
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* warranty of any kind, whether express or implied.
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*/
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#include <mach/loki.h>
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#include <mach/bridge-regs.h>
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.macro disable_fiq
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.endm
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@ -58,20 +58,6 @@
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#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100)
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#define BRIDGE_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x20000)
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#define BRIDGE_REG(x) (BRIDGE_VIRT_BASE | (x))
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#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
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#define SOFT_RESET_OUT_EN 0x00000004
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#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
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#define SOFT_RESET 0x00000001
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#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
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#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
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#define BRIDGE_INT_TIMER0 0x0002
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#define BRIDGE_INT_TIMER1 0x0004
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#define BRIDGE_INT_TIMER1_CLR 0x0004
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#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
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#define IRQ_CAUSE_OFF 0x0000
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#define IRQ_MASK_OFF 0x0004
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#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
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#define PCIE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x30000)
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@ -9,8 +9,7 @@
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#ifndef __ASM_ARCH_SYSTEM_H
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#define __ASM_ARCH_SYSTEM_H
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#include <mach/hardware.h>
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#include <mach/loki.h>
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#include <mach/bridge-regs.h>
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static inline void arch_idle(void)
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{
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@ -12,6 +12,7 @@
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <mach/bridge-regs.h>
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#include <plat/irq.h>
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#include "common.h"
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@ -20,6 +20,7 @@
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <mach/mv78xx0.h>
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#include <mach/bridge-regs.h>
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#include <plat/cache-feroceon-l2.h>
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#include <plat/ehci-orion.h>
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#include <plat/orion_nand.h>
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@ -0,0 +1,39 @@
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/*
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* arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_BRIDGE_REGS_H
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#define __ASM_ARCH_BRIDGE_REGS_H
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#include <mach/mv78xx0.h>
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#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
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#define L2_WRITETHROUGH 0x00020000
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#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
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#define SOFT_RESET_OUT_EN 0x00000004
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#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
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#define SOFT_RESET 0x00000001
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#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
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#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
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#define BRIDGE_INT_TIMER0 0x0002
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#define BRIDGE_INT_TIMER1 0x0004
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#define BRIDGE_INT_TIMER1_CLR (~0x0004)
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#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
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#define IRQ_CAUSE_ERR_OFF 0x0000
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#define IRQ_CAUSE_LOW_OFF 0x0004
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#define IRQ_CAUSE_HIGH_OFF 0x0008
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#define IRQ_MASK_ERR_OFF 0x000c
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#define IRQ_MASK_LOW_OFF 0x0010
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#define IRQ_MASK_HIGH_OFF 0x0014
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#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
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#endif
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@ -8,7 +8,7 @@
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* warranty of any kind, whether express or implied.
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*/
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#include <mach/mv78xx0.h>
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#include <mach/bridge-regs.h>
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.macro disable_fiq
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.endm
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@ -59,37 +59,6 @@
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* Core-specific peripheral registers.
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*/
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#define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE)
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#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
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#define L2_WRITETHROUGH 0x00020000
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#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
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#define SOFT_RESET_OUT_EN 0x00000004
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#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
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#define SOFT_RESET 0x00000001
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#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
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#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
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#define BRIDGE_INT_TIMER0 0x0002
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#define BRIDGE_INT_TIMER1 0x0004
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#define BRIDGE_INT_TIMER1_CLR (~0x0004)
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#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
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#define IRQ_CAUSE_ERR_OFF 0x0000
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#define IRQ_CAUSE_LOW_OFF 0x0004
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#define IRQ_CAUSE_HIGH_OFF 0x0008
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#define IRQ_MASK_ERR_OFF 0x000c
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#define IRQ_MASK_LOW_OFF 0x0010
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#define IRQ_MASK_HIGH_OFF 0x0014
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#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
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/*
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* Supported devices and revisions.
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*/
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#define MV78X00_Z0_DEV_ID 0x6381
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#define MV78X00_REV_Z0 1
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#define MV78100_DEV_ID 0x7810
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#define MV78100_REV_A0 1
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#define MV78200_DEV_ID 0x7820
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#define MV78200_REV_A0 1
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/*
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* Register Map
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@ -135,5 +104,16 @@
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#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000)
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/*
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* Supported devices and revisions.
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*/
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#define MV78X00_Z0_DEV_ID 0x6381
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#define MV78X00_REV_Z0 1
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#define MV78100_DEV_ID 0x7810
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#define MV78100_REV_A0 1
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#define MV78200_DEV_ID 0x7820
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#define MV78200_REV_A0 1
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#endif
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@ -9,8 +9,7 @@
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#ifndef __ASM_ARCH_SYSTEM_H
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#define __ASM_ARCH_SYSTEM_H
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#include <mach/hardware.h>
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#include <mach/mv78xx0.h>
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#include <mach/bridge-regs.h>
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static inline void arch_idle(void)
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{
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@ -13,7 +13,7 @@
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#include <linux/pci.h>
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#include <linux/irq.h>
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#include <asm/gpio.h>
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#include <mach/mv78xx0.h>
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#include <mach/bridge-regs.h>
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#include <plat/irq.h>
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#include "common.h"
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@ -57,12 +57,14 @@
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/*
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* Helpers to get DDR bank info
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*/
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#define ORION5X_DDR_REG(x) (ORION5X_DDR_VIRT_BASE | (x))
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#define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) << 3))
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#define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) << 3))
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/*
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* CPU Address Decode Windows registers
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||||
*/
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#define ORION5X_BRIDGE_REG(x) (ORION5X_BRIDGE_VIRT_BASE | (x))
|
||||
#define CPU_WIN_CTRL(n) ORION5X_BRIDGE_REG(0x000 | ((n) << 4))
|
||||
#define CPU_WIN_BASE(n) ORION5X_BRIDGE_REG(0x004 | ((n) << 4))
|
||||
#define CPU_WIN_REMAP_LO(n) ORION5X_BRIDGE_REG(0x008 | ((n) << 4))
|
||||
|
|
|
|||
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* arch/arm/mach-orion5x/include/mach/bridge-regs.h
|
||||
*
|
||||
* Orion CPU Bridge Registers
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_BRIDGE_REGS_H
|
||||
#define __ASM_ARCH_BRIDGE_REGS_H
|
||||
|
||||
#include <mach/orion5x.h>
|
||||
|
||||
#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE | 0x100)
|
||||
|
||||
#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE | 0x104)
|
||||
|
||||
#define CPU_RESET_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x108)
|
||||
#define WDT_RESET 0x0002
|
||||
|
||||
#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE | 0x10c)
|
||||
|
||||
#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE | 0x11C)
|
||||
|
||||
#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x110)
|
||||
#define WDT_INT_REQ 0x0008
|
||||
|
||||
#define BRIDGE_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x114)
|
||||
#define BRIDGE_INT_TIMER0 0x0002
|
||||
#define BRIDGE_INT_TIMER1 0x0004
|
||||
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
|
||||
|
||||
#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x200)
|
||||
|
||||
#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x204)
|
||||
|
||||
#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300)
|
||||
|
||||
#endif
|
||||
|
|
@ -8,7 +8,7 @@
|
|||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <mach/orion5x.h>
|
||||
#include <mach/bridge-regs.h>
|
||||
|
||||
.macro disable_fiq
|
||||
.endm
|
||||
|
|
|
|||
|
|
@ -60,6 +60,59 @@
|
|||
#define ORION5X_PCI_MEM_PHYS_BASE 0xe8000000
|
||||
#define ORION5X_PCI_MEM_SIZE SZ_128M
|
||||
|
||||
/*******************************************************************************
|
||||
* Orion Registers Map
|
||||
******************************************************************************/
|
||||
|
||||
#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000)
|
||||
|
||||
#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000)
|
||||
#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000)
|
||||
#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x))
|
||||
#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x0600)
|
||||
#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x1000)
|
||||
#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2000)
|
||||
#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2000)
|
||||
#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2100)
|
||||
#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2100)
|
||||
|
||||
#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x20000)
|
||||
|
||||
#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x30000)
|
||||
|
||||
#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x40000)
|
||||
|
||||
#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x50000)
|
||||
#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x50000)
|
||||
|
||||
#define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x60900)
|
||||
#define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x60900)
|
||||
|
||||
#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x70000)
|
||||
#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x70000)
|
||||
|
||||
#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000)
|
||||
#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000)
|
||||
|
||||
#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000)
|
||||
#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000)
|
||||
|
||||
/*******************************************************************************
|
||||
* Device Bus Registers
|
||||
******************************************************************************/
|
||||
#define MPP_0_7_CTRL ORION5X_DEV_BUS_REG(0x000)
|
||||
#define MPP_8_15_CTRL ORION5X_DEV_BUS_REG(0x004)
|
||||
#define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050)
|
||||
#define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008)
|
||||
#define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010)
|
||||
#define DEV_BANK_0_PARAM ORION5X_DEV_BUS_REG(0x45c)
|
||||
#define DEV_BANK_1_PARAM ORION5X_DEV_BUS_REG(0x460)
|
||||
#define DEV_BANK_2_PARAM ORION5X_DEV_BUS_REG(0x464)
|
||||
#define DEV_BANK_BOOT_PARAM ORION5X_DEV_BUS_REG(0x46c)
|
||||
#define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0)
|
||||
#define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0)
|
||||
#define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4)
|
||||
|
||||
/*******************************************************************************
|
||||
* Supported Devices & Revisions
|
||||
******************************************************************************/
|
||||
|
|
@ -80,85 +133,4 @@
|
|||
#define MV88F6183_DEV_ID 0x6183
|
||||
#define MV88F6183_REV_B0 3
|
||||
|
||||
/*******************************************************************************
|
||||
* Orion Registers Map
|
||||
******************************************************************************/
|
||||
#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000)
|
||||
#define ORION5X_DDR_REG(x) (ORION5X_DDR_VIRT_BASE | (x))
|
||||
|
||||
#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000)
|
||||
#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000)
|
||||
#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x))
|
||||
#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x0600)
|
||||
#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x1000)
|
||||
#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2000)
|
||||
#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2000)
|
||||
#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2100)
|
||||
#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2100)
|
||||
|
||||
#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x20000)
|
||||
#define ORION5X_BRIDGE_REG(x) (ORION5X_BRIDGE_VIRT_BASE | (x))
|
||||
#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300)
|
||||
|
||||
#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x30000)
|
||||
#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x))
|
||||
|
||||
#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x40000)
|
||||
#define ORION5X_PCIE_REG(x) (ORION5X_PCIE_VIRT_BASE | (x))
|
||||
|
||||
#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x50000)
|
||||
#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x50000)
|
||||
#define ORION5X_USB0_REG(x) (ORION5X_USB0_VIRT_BASE | (x))
|
||||
|
||||
#define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x60900)
|
||||
#define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x60900)
|
||||
#define ORION5X_XOR_REG(x) (ORION5X_XOR_VIRT_BASE | (x))
|
||||
|
||||
#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x70000)
|
||||
#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x70000)
|
||||
#define ORION5X_ETH_REG(x) (ORION5X_ETH_VIRT_BASE | (x))
|
||||
|
||||
#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000)
|
||||
#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000)
|
||||
#define ORION5X_SATA_REG(x) (ORION5X_SATA_VIRT_BASE | (x))
|
||||
|
||||
#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000)
|
||||
#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000)
|
||||
#define ORION5X_USB1_REG(x) (ORION5X_USB1_VIRT_BASE | (x))
|
||||
|
||||
/*******************************************************************************
|
||||
* Device Bus Registers
|
||||
******************************************************************************/
|
||||
#define MPP_0_7_CTRL ORION5X_DEV_BUS_REG(0x000)
|
||||
#define MPP_8_15_CTRL ORION5X_DEV_BUS_REG(0x004)
|
||||
#define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050)
|
||||
#define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008)
|
||||
#define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010)
|
||||
#define DEV_BANK_0_PARAM ORION5X_DEV_BUS_REG(0x45c)
|
||||
#define DEV_BANK_1_PARAM ORION5X_DEV_BUS_REG(0x460)
|
||||
#define DEV_BANK_2_PARAM ORION5X_DEV_BUS_REG(0x464)
|
||||
#define DEV_BANK_BOOT_PARAM ORION5X_DEV_BUS_REG(0x46c)
|
||||
#define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0)
|
||||
#define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0)
|
||||
#define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4)
|
||||
|
||||
/***************************************************************************
|
||||
* Orion CPU Bridge Registers
|
||||
**************************************************************************/
|
||||
#define CPU_CONF ORION5X_BRIDGE_REG(0x100)
|
||||
#define CPU_CTRL ORION5X_BRIDGE_REG(0x104)
|
||||
#define CPU_RESET_MASK ORION5X_BRIDGE_REG(0x108)
|
||||
#define WDT_RESET 0x0002
|
||||
#define CPU_SOFT_RESET ORION5X_BRIDGE_REG(0x10c)
|
||||
#define POWER_MNG_CTRL_REG ORION5X_BRIDGE_REG(0x11C)
|
||||
#define BRIDGE_CAUSE ORION5X_BRIDGE_REG(0x110)
|
||||
#define WDT_INT_REQ 0x0008
|
||||
#define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114)
|
||||
#define BRIDGE_INT_TIMER0 0x0002
|
||||
#define BRIDGE_INT_TIMER1 0x0004
|
||||
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
|
||||
#define MAIN_IRQ_CAUSE ORION5X_BRIDGE_REG(0x200)
|
||||
#define MAIN_IRQ_MASK ORION5X_BRIDGE_REG(0x204)
|
||||
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -11,8 +11,7 @@
|
|||
#ifndef __ASM_ARCH_SYSTEM_H
|
||||
#define __ASM_ARCH_SYSTEM_H
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/orion5x.h>
|
||||
#include <mach/bridge-regs.h>
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@
|
|||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <mach/orion5x.h>
|
||||
#include <mach/bridge-regs.h>
|
||||
#include <plat/irq.h>
|
||||
#include "common.h"
|
||||
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@
|
|||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/pci.h>
|
||||
#include <mach/orion5x.h>
|
||||
#include <mach/bridge-regs.h>
|
||||
#include "common.h"
|
||||
#include "mpp.h"
|
||||
|
||||
|
|
|
|||
|
|
@ -196,6 +196,7 @@ static int __init pcie_setup(struct pci_sys_data *sys)
|
|||
/*****************************************************************************
|
||||
* PCI controller
|
||||
****************************************************************************/
|
||||
#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x))
|
||||
#define PCI_MODE ORION5X_PCI_REG(0xd00)
|
||||
#define PCI_CMD ORION5X_PCI_REG(0xc00)
|
||||
#define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14)
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/bridge-regs.h>
|
||||
|
||||
/*
|
||||
* Number of timer ticks per jiffy.
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
#include <linux/uaccess.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <mach/bridge-regs.h>
|
||||
#include <plat/orion5x_wdt.h>
|
||||
|
||||
/*
|
||||
|
|
|
|||
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