powerpc/e500mc: Implement machine check handler.
Most of the MSCR bit assigments are different in e500mc versus e500, and they are now write-one-to-clear. Some e500mc machine check conditions are made recoverable (as long as they aren't stuck on), most notably L1 instruction cache parity errors. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Scott Wood
Kumar Gala
Родитель
99ec28f183
Коммит
fe04b11215
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@ -70,6 +70,7 @@ struct pt_regs;
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extern int machine_check_generic(struct pt_regs *regs);
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extern int machine_check_4xx(struct pt_regs *regs);
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extern int machine_check_440A(struct pt_regs *regs);
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extern int machine_check_e500mc(struct pt_regs *regs);
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extern int machine_check_e500(struct pt_regs *regs);
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extern int machine_check_e200(struct pt_regs *regs);
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extern int machine_check_47x(struct pt_regs *regs);
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@ -4,6 +4,12 @@
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* are not true Book E PowerPCs, they borrowed a number of features
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* before Book E was finalized, and are included here as well. Unfortunatly,
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* they sometimes used different locations than true Book E CPUs did.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation.
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*
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* Copyright 2009-2010 Freescale Semiconductor, Inc.
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*/
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#ifdef __KERNEL__
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#ifndef __ASM_POWERPC_REG_BOOKE_H__
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@ -88,6 +94,7 @@
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#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
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#define SPRN_IVOR36 0x214 /* Interrupt Vector Offset Register 36 */
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#define SPRN_IVOR37 0x215 /* Interrupt Vector Offset Register 37 */
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#define SPRN_MCARU 0x239 /* Machine Check Address Register Upper */
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#define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */
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#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */
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#define SPRN_MCSR 0x23C /* Machine Check Status Register */
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@ -196,8 +203,11 @@
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#define PPC47x_MCSR_IPR 0x00400000 /* Imprecise Machine Check Exception */
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#ifdef CONFIG_E500
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/* All e500 */
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#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
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#define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */
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/* e500v1/v2 */
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#define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */
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#define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */
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#define MCSR_BUS_IAERR 0x00000080UL /* Instruction Address Error */
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@ -209,12 +219,20 @@
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#define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */
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#define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */
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/* e500 parts may set unused bits in MCSR; mask these off */
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#define MCSR_MASK (MCSR_MCP | MCSR_ICPERR | MCSR_DCP_PERR | \
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MCSR_DCPERR | MCSR_BUS_IAERR | MCSR_BUS_RAERR | \
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MCSR_BUS_WAERR | MCSR_BUS_IBERR | MCSR_BUS_RBERR | \
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MCSR_BUS_WBERR | MCSR_BUS_IPERR | MCSR_BUS_RPERR)
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/* e500mc */
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#define MCSR_DCPERR_MC 0x20000000UL /* D-Cache Parity Error */
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#define MCSR_L2MMU_MHIT 0x04000000UL /* Hit on multiple TLB entries */
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#define MCSR_NMI 0x00100000UL /* Non-Maskable Interrupt */
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#define MCSR_MAV 0x00080000UL /* MCAR address valid */
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#define MCSR_MEA 0x00040000UL /* MCAR is effective address */
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#define MCSR_IF 0x00010000UL /* Instruction Fetch */
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#define MCSR_LD 0x00008000UL /* Load */
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#define MCSR_ST 0x00004000UL /* Store */
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#define MCSR_LDG 0x00002000UL /* Guarded Load */
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#define MCSR_TLBSYNC 0x00000002UL /* Multiple tlbsyncs detected */
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#define MCSR_BSL2_ERR 0x00000001UL /* Backside L2 cache error */
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#endif
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#ifdef CONFIG_E200
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#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
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#define MCSR_CP_PERR 0x20000000UL /* Cache Push Parity Error */
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@ -225,11 +243,6 @@
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#define MCSR_BUS_DRERR 0x00000008UL /* Read Bus Error on data load */
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#define MCSR_BUS_WRERR 0x00000004UL /* Write Bus Error on buffered
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store or cache line push */
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/* e200 parts may set unused bits in MCSR; mask these off */
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#define MCSR_MASK (MCSR_MCP | MCSR_CP_PERR | MCSR_CPERR | \
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MCSR_EXCP_ERR | MCSR_BUS_IRERR | MCSR_BUS_DRERR | \
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MCSR_BUS_WRERR)
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#endif
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/* Bit definitions for the DBSR. */
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@ -1840,7 +1840,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.oprofile_cpu_type = "ppc/e500mc",
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.oprofile_type = PPC_OPROFILE_FSL_EMB,
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.cpu_setup = __setup_cpu_e500mc,
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.machine_check = machine_check_e500,
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.machine_check = machine_check_e500mc,
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.platform = "ppce500mc",
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},
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{ /* default match */
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@ -1,5 +1,6 @@
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/*
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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* Copyright 2007-2010 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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@ -305,7 +306,7 @@ static inline int check_io_access(struct pt_regs *regs)
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#ifndef CONFIG_FSL_BOOKE
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#define get_mc_reason(regs) ((regs)->dsisr)
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#else
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#define get_mc_reason(regs) (mfspr(SPRN_MCSR) & MCSR_MASK)
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#define get_mc_reason(regs) (mfspr(SPRN_MCSR))
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#endif
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#define REASON_FP ESR_FP
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#define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
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@ -421,6 +422,91 @@ int machine_check_47x(struct pt_regs *regs)
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return 0;
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}
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#elif defined(CONFIG_E500)
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int machine_check_e500mc(struct pt_regs *regs)
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{
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unsigned long mcsr = mfspr(SPRN_MCSR);
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unsigned long reason = mcsr;
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int recoverable = 1;
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printk("Machine check in kernel mode.\n");
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printk("Caused by (from MCSR=%lx): ", reason);
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if (reason & MCSR_MCP)
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printk("Machine Check Signal\n");
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if (reason & MCSR_ICPERR) {
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printk("Instruction Cache Parity Error\n");
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/*
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* This is recoverable by invalidating the i-cache.
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*/
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mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
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while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
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;
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/*
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* This will generally be accompanied by an instruction
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* fetch error report -- only treat MCSR_IF as fatal
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* if it wasn't due to an L1 parity error.
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*/
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reason &= ~MCSR_IF;
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}
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if (reason & MCSR_DCPERR_MC) {
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printk("Data Cache Parity Error\n");
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recoverable = 0;
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}
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if (reason & MCSR_L2MMU_MHIT) {
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printk("Hit on multiple TLB entries\n");
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recoverable = 0;
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}
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if (reason & MCSR_NMI)
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printk("Non-maskable interrupt\n");
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if (reason & MCSR_IF) {
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printk("Instruction Fetch Error Report\n");
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recoverable = 0;
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}
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if (reason & MCSR_LD) {
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printk("Load Error Report\n");
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recoverable = 0;
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}
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if (reason & MCSR_ST) {
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printk("Store Error Report\n");
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recoverable = 0;
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}
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if (reason & MCSR_LDG) {
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printk("Guarded Load Error Report\n");
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recoverable = 0;
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}
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if (reason & MCSR_TLBSYNC)
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printk("Simultaneous tlbsync operations\n");
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if (reason & MCSR_BSL2_ERR) {
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printk("Level 2 Cache Error\n");
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recoverable = 0;
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}
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if (reason & MCSR_MAV) {
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u64 addr;
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addr = mfspr(SPRN_MCAR);
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addr |= (u64)mfspr(SPRN_MCARU) << 32;
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printk("Machine Check %s Address: %#llx\n",
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reason & MCSR_MEA ? "Effective" : "Physical", addr);
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}
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mtspr(SPRN_MCSR, mcsr);
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return mfspr(SPRN_MCSR) == 0 && recoverable;
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}
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int machine_check_e500(struct pt_regs *regs)
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{
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unsigned long reason = get_mc_reason(regs);
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