drm/amdgpu/vcn:Remove DPG mode unused steps during vcn start
Remove Dynamic Power Gate mode unused steps during VCN start Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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368d0dd81a
Коммит
fe146873f5
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@ -981,22 +981,6 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
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WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN,
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0, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
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/* stall UMC and register bus before resetting VCPU */
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WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2,
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UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
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/* put LMI, VCPU, RBC etc... into reset */
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WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET,
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UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
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UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
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UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
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UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
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UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
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UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
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UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
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UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
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0xFFFFFFFF, 0);
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/* initialize VCN memory controller */
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WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL,
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(8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
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@ -1039,14 +1023,6 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
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WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0);
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WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0);
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/* take all subblocks out of reset, except VCPU */
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WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET,
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UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 0xFFFFFFFF, 0);
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/* enable VCPU clock */
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WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL,
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UVD_VCPU_CNTL__CLK_EN_MASK, 0xFFFFFFFF, 0);
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/* enable UMC */
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WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2,
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0, UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
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@ -1056,8 +1032,7 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
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/* enable master interrupt */
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WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN,
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(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
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(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 0);
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UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
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vcn_v1_0_clock_gating_dpg_mode(adev, 1);
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/* setup mmUVD_LMI_CTRL */
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@ -1085,7 +1060,6 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
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tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
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tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
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tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
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tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
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tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
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tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
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WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
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