Allwinner clocks changes for 4.1
The usual round of clock changes for the Allwinner SoCs. There is nothing really standing out here, but a few changes and fixes, most notably to allow the AHB clock to be parented to a PLL, instead of the CPU clock to avoid any AHB rate change due to cpufreq. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJVEyS7AAoJEBx+YmzsjxAgKRIP/3cn2AYWL25NGB2vd61hYQuK zHMHqqGyybr+8nxCd2ue4ztBLUTMZz3BA+siaYG7KzOUmSCpHZb6ic2RlqWGZMbX CmBW09YNiMtXvIaViYXH8ltVy/Ug8abwpRVkPjWf8jcbN9beGb34mrYstUBa4Cmh 9clMaMTAvhD0KqmrlHGd/tgyXdZXZPriRLLbUbumF5gatXFpHK2EzJBQMqAzhPE+ Qrn5xoDJMBziJ21cX/4MRnGWILgOy9EioW7TMhUvj7reZniHhkTBiSo/gu6qImTM izkO1GP5rAhVjfEbltvVPIKaFP2cFnxwVwq9sDkhE4cMwb9CWOXhM6vdEFRm9PAG nC/VVjLFaJ3lCyI+jYB5917d+U/F+RwrI07Zwx9+QLzNiyCh9y2DL+kKT6iyzYbY as4Jg4J2MrOk+WesGH49PAT/ciUqnViTMKMMcbu/0chMHIsN7L80h+gH9ktnAkN4 1JmQfL2A85i2NORsb7SFM4P5Gc8c5cxnqbZ4honS4TxLW5CmXI9zISG53j/miBy9 SRutVT6IGseMNhIrWgHxRVVQBpG3QasYZSVOVutK9IDrUJ8L0pgymb7VjtMaAKDK 1dxfl6gdkUIJ1jfjD3ly57eMkikLDWc/ea3VgIUCQoBU8IVJuJuc/miWi0i3qnJo zkLzG1fR0OH+LHtFO42K =k3yP -----END PGP SIGNATURE----- Merge tag 'sunxi-clocks-for-4.1' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Allwinner clocks changes for 4.1 The usual round of clock changes for the Allwinner SoCs. There is nothing really standing out here, but a few changes and fixes, most notably to allow the AHB clock to be parented to a PLL, instead of the CPU clock to avoid any AHB rate change due to cpufreq.
This commit is contained in:
Michael Turquette
Коммит
fe15dedc02
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@ -20,6 +20,7 @@ Required properties:
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"allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23
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"allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
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"allwinner,sun4i-a10-ahb-clk" - for the AHB clock
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"allwinner,sun5i-a13-ahb-clk" - for the AHB clock on A13
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"allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80
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"allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
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"allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
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@ -66,6 +67,8 @@ Required properties:
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"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
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"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
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"allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
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"allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
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"allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
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Required properties for all clocks:
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- reg : shall be the control register address for the clock.
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@ -9,6 +9,7 @@ obj-y += clk-mod0.o
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obj-y += clk-sun8i-mbus.o
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obj-y += clk-sun9i-core.o
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obj-y += clk-sun9i-mmc.o
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obj-y += clk-usb.o
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obj-$(CONFIG_MFD_SUN6I_PRCM) += \
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clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
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@ -481,6 +481,45 @@ static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate,
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*n = DIV_ROUND_UP(div, (*k+1)) - 1;
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}
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/**
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* sun5i_a13_get_ahb_factors() - calculates m, p factors for AHB
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* AHB rate is calculated as follows
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* rate = parent_rate >> p
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*/
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static void sun5i_a13_get_ahb_factors(u32 *freq, u32 parent_rate,
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u8 *n, u8 *k, u8 *m, u8 *p)
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{
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u32 div;
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/* divide only */
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if (parent_rate < *freq)
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*freq = parent_rate;
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/*
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* user manual says valid speed is 8k ~ 276M, but tests show it
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* can work at speeds up to 300M, just after reparenting to pll6
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*/
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if (*freq < 8000)
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*freq = 8000;
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if (*freq > 300000000)
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*freq = 300000000;
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div = order_base_2(DIV_ROUND_UP(parent_rate, *freq));
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/* p = 0 ~ 3 */
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if (div > 3)
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div = 3;
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*freq = parent_rate >> div;
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/* we were called to round the frequency, we can now return */
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if (p == NULL)
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return;
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*p = div;
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}
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/**
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* sun4i_get_apb1_factors() - calculates m, p factors for APB1
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* APB1 rate is calculated as follows
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@ -616,6 +655,11 @@ static struct clk_factors_config sun6i_a31_pll6_config = {
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.n_start = 1,
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};
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static struct clk_factors_config sun5i_a13_ahb_config = {
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.pshift = 4,
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.pwidth = 2,
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};
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static struct clk_factors_config sun4i_apb1_config = {
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.mshift = 0,
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.mwidth = 5,
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@ -676,6 +720,13 @@ static const struct factors_data sun6i_a31_pll6_data __initconst = {
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.name = "pll6x2",
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};
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static const struct factors_data sun5i_a13_ahb_data __initconst = {
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.mux = 6,
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.muxmask = BIT(1) | BIT(0),
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.table = &sun5i_a13_ahb_config,
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.getter = sun5i_a13_get_ahb_factors,
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};
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static const struct factors_data sun4i_apb1_data __initconst = {
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.mux = 24,
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.muxmask = BIT(1) | BIT(0),
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@ -837,59 +888,6 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
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/**
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* sunxi_gates_reset... - reset bits in leaf gate clk registers handling
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*/
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struct gates_reset_data {
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void __iomem *reg;
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spinlock_t *lock;
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struct reset_controller_dev rcdev;
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};
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static int sunxi_gates_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct gates_reset_data *data = container_of(rcdev,
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struct gates_reset_data,
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rcdev);
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unsigned long flags;
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u32 reg;
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spin_lock_irqsave(data->lock, flags);
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reg = readl(data->reg);
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writel(reg & ~BIT(id), data->reg);
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spin_unlock_irqrestore(data->lock, flags);
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return 0;
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}
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static int sunxi_gates_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct gates_reset_data *data = container_of(rcdev,
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struct gates_reset_data,
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rcdev);
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unsigned long flags;
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u32 reg;
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spin_lock_irqsave(data->lock, flags);
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reg = readl(data->reg);
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writel(reg | BIT(id), data->reg);
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spin_unlock_irqrestore(data->lock, flags);
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return 0;
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}
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static struct reset_control_ops sunxi_gates_reset_ops = {
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.assert = sunxi_gates_reset_assert,
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.deassert = sunxi_gates_reset_deassert,
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};
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/**
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* sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
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*/
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@ -898,7 +896,6 @@ static struct reset_control_ops sunxi_gates_reset_ops = {
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struct gates_data {
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DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
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u32 reset_mask;
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};
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static const struct gates_data sun4i_axi_gates_data __initconst = {
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@ -997,26 +994,10 @@ static const struct gates_data sun8i_a23_apb2_gates_data __initconst = {
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.mask = {0x1F0007},
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};
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static const struct gates_data sun4i_a10_usb_gates_data __initconst = {
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.mask = {0x1C0},
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.reset_mask = 0x07,
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};
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static const struct gates_data sun5i_a13_usb_gates_data __initconst = {
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.mask = {0x140},
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.reset_mask = 0x03,
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};
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static const struct gates_data sun6i_a31_usb_gates_data __initconst = {
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.mask = { BIT(18) | BIT(17) | BIT(16) | BIT(10) | BIT(9) | BIT(8) },
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.reset_mask = BIT(2) | BIT(1) | BIT(0),
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};
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static void __init sunxi_gates_clk_setup(struct device_node *node,
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struct gates_data *data)
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{
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struct clk_onecell_data *clk_data;
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struct gates_reset_data *reset_data;
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const char *clk_parent;
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const char *clk_name;
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void __iomem *reg;
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@ -1057,21 +1038,6 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
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clk_data->clk_num = i;
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of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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/* Register a reset controler for gates with reset bits */
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if (data->reset_mask == 0)
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return;
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reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
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if (!reset_data)
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return;
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reset_data->reg = reg;
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reset_data->lock = &clk_lock;
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reset_data->rcdev.nr_resets = __fls(data->reset_mask) + 1;
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reset_data->rcdev.ops = &sunxi_gates_reset_ops;
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reset_data->rcdev.of_node = node;
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reset_controller_register(&reset_data->rcdev);
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}
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@ -1080,13 +1046,20 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
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* sunxi_divs_clk_setup() helper data
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*/
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#define SUNXI_DIVS_MAX_QTY 2
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#define SUNXI_DIVS_MAX_QTY 4
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#define SUNXI_DIVISOR_WIDTH 2
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struct divs_data {
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const struct factors_data *factors; /* data for the factor clock */
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int ndivs; /* number of children */
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int ndivs; /* number of outputs */
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/*
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* List of outputs. Refer to the diagram for sunxi_divs_clk_setup():
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* self or base factor clock refers to the output from the pll
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* itself. The remaining refer to fixed or configurable divider
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* outputs.
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*/
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struct {
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u8 self; /* is it the base factor clock? (only one) */
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u8 fixed; /* is it a fixed divisor? if not... */
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struct clk_div_table *table; /* is it a table based divisor? */
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u8 shift; /* otherwise it's a normal divisor with this shift */
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@ -1109,23 +1082,27 @@ static const struct divs_data pll5_divs_data __initconst = {
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.div = {
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{ .shift = 0, .pow = 0, }, /* M, DDR */
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{ .shift = 16, .pow = 1, }, /* P, other */
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/* No output for the base factor clock */
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}
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};
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static const struct divs_data pll6_divs_data __initconst = {
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.factors = &sun4i_pll6_data,
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.ndivs = 2,
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.ndivs = 4,
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.div = {
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{ .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
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{ .fixed = 2 }, /* P, other */
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{ .self = 1 }, /* base factor clock, 2x */
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{ .fixed = 4 }, /* pll6 / 4, used as ahb input */
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}
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};
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static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
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.factors = &sun6i_a31_pll6_data,
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.ndivs = 1,
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.ndivs = 2,
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.div = {
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{ .fixed = 2 }, /* normal output */
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{ .self = 1 }, /* base factor clock, 2x */
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}
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};
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@ -1156,6 +1133,10 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
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int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
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int flags, clkflags;
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/* if number of children known, use it */
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if (data->ndivs)
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ndivs = data->ndivs;
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/* Set up factor clock that we will be dividing */
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pclk = sunxi_factors_clk_setup(node, data->factors);
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parent = __clk_get_name(pclk);
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@ -1166,7 +1147,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
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if (!clk_data)
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return;
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clks = kzalloc((SUNXI_DIVS_MAX_QTY+1) * sizeof(*clks), GFP_KERNEL);
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clks = kcalloc(ndivs, sizeof(*clks), GFP_KERNEL);
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if (!clks)
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goto free_clkdata;
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@ -1176,15 +1157,17 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
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* our RAM clock! */
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clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
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/* if number of children known, use it */
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if (data->ndivs)
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ndivs = data->ndivs;
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for (i = 0; i < ndivs; i++) {
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if (of_property_read_string_index(node, "clock-output-names",
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i, &clk_name) != 0)
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break;
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/* If this is the base factor clock, only update clks */
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if (data->div[i].self) {
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clk_data->clks[i] = pclk;
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continue;
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}
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gate_hw = NULL;
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rate_hw = NULL;
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rate_ops = NULL;
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@ -1243,9 +1226,6 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
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clk_register_clkdev(clks[i], clk_name, NULL);
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}
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/* The last clock available on the getter is the parent */
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clks[i++] = pclk;
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/* Adjust to the real max */
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clk_data->clk_num = i;
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@ -1269,6 +1249,7 @@ static const struct of_device_id clk_factors_match[] __initconst = {
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{.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
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{.compatible = "allwinner,sun8i-a23-pll1-clk", .data = &sun8i_a23_pll1_data,},
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{.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
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{.compatible = "allwinner,sun5i-a13-ahb-clk", .data = &sun5i_a13_ahb_data,},
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{.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
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{.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
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{}
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@ -1324,9 +1305,6 @@ static const struct of_device_id clk_gates_match[] __initconst = {
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{.compatible = "allwinner,sun9i-a80-apb1-gates-clk", .data = &sun9i_a80_apb1_gates_data,},
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{.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
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{.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,},
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{.compatible = "allwinner,sun4i-a10-usb-clk", .data = &sun4i_a10_usb_gates_data,},
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{.compatible = "allwinner,sun5i-a13-usb-clk", .data = &sun5i_a13_usb_gates_data,},
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{.compatible = "allwinner,sun6i-a31-usb-clk", .data = &sun6i_a31_usb_gates_data,},
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{}
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};
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@ -1348,15 +1326,15 @@ static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
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{
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unsigned int i;
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/* Register divided output clocks */
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of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup);
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/* Register factor clocks */
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of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
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/* Register divider clocks */
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of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
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/* Register divided output clocks */
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of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup);
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/* Register mux clocks */
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of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
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@ -1385,6 +1363,7 @@ static void __init sun4i_a10_init_clocks(struct device_node *node)
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CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks);
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static const char *sun5i_critical_clocks[] __initdata = {
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"cpu",
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"pll5_ddr",
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"ahb_sdram",
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};
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@ -0,0 +1,233 @@
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/*
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* Copyright 2013-2015 Emilio López
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*
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* Emilio López <emilio@elopez.com.ar>
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*
|
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/reset-controller.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
|
||||
/**
|
||||
* sunxi_usb_reset... - reset bits in usb clk registers handling
|
||||
*/
|
||||
|
||||
struct usb_reset_data {
|
||||
void __iomem *reg;
|
||||
spinlock_t *lock;
|
||||
struct clk *clk;
|
||||
struct reset_controller_dev rcdev;
|
||||
};
|
||||
|
||||
static int sunxi_usb_reset_assert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
struct usb_reset_data *data = container_of(rcdev,
|
||||
struct usb_reset_data,
|
||||
rcdev);
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
|
||||
clk_prepare_enable(data->clk);
|
||||
spin_lock_irqsave(data->lock, flags);
|
||||
|
||||
reg = readl(data->reg);
|
||||
writel(reg & ~BIT(id), data->reg);
|
||||
|
||||
spin_unlock_irqrestore(data->lock, flags);
|
||||
clk_disable_unprepare(data->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sunxi_usb_reset_deassert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
struct usb_reset_data *data = container_of(rcdev,
|
||||
struct usb_reset_data,
|
||||
rcdev);
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
|
||||
clk_prepare_enable(data->clk);
|
||||
spin_lock_irqsave(data->lock, flags);
|
||||
|
||||
reg = readl(data->reg);
|
||||
writel(reg | BIT(id), data->reg);
|
||||
|
||||
spin_unlock_irqrestore(data->lock, flags);
|
||||
clk_disable_unprepare(data->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct reset_control_ops sunxi_usb_reset_ops = {
|
||||
.assert = sunxi_usb_reset_assert,
|
||||
.deassert = sunxi_usb_reset_deassert,
|
||||
};
|
||||
|
||||
/**
|
||||
* sunxi_usb_clk_setup() - Setup function for usb gate clocks
|
||||
*/
|
||||
|
||||
#define SUNXI_USB_MAX_SIZE 32
|
||||
|
||||
struct usb_clk_data {
|
||||
u32 clk_mask;
|
||||
u32 reset_mask;
|
||||
bool reset_needs_clk;
|
||||
};
|
||||
|
||||
static void __init sunxi_usb_clk_setup(struct device_node *node,
|
||||
const struct usb_clk_data *data,
|
||||
spinlock_t *lock)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct usb_reset_data *reset_data;
|
||||
const char *clk_parent;
|
||||
const char *clk_name;
|
||||
void __iomem *reg;
|
||||
int qty;
|
||||
int i = 0;
|
||||
int j = 0;
|
||||
|
||||
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
|
||||
if (IS_ERR(reg))
|
||||
return;
|
||||
|
||||
clk_parent = of_clk_get_parent_name(node, 0);
|
||||
if (!clk_parent)
|
||||
return;
|
||||
|
||||
/* Worst-case size approximation and memory allocation */
|
||||
qty = find_last_bit((unsigned long *)&data->clk_mask,
|
||||
SUNXI_USB_MAX_SIZE);
|
||||
|
||||
clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
|
||||
if (!clk_data)
|
||||
return;
|
||||
|
||||
clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
|
||||
if (!clk_data->clks) {
|
||||
kfree(clk_data);
|
||||
return;
|
||||
}
|
||||
|
||||
for_each_set_bit(i, (unsigned long *)&data->clk_mask,
|
||||
SUNXI_USB_MAX_SIZE) {
|
||||
of_property_read_string_index(node, "clock-output-names",
|
||||
j, &clk_name);
|
||||
clk_data->clks[i] = clk_register_gate(NULL, clk_name,
|
||||
clk_parent, 0,
|
||||
reg, i, 0, lock);
|
||||
WARN_ON(IS_ERR(clk_data->clks[i]));
|
||||
|
||||
j++;
|
||||
}
|
||||
|
||||
/* Adjust to the real max */
|
||||
clk_data->clk_num = i;
|
||||
|
||||
of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
|
||||
/* Register a reset controller for usb with reset bits */
|
||||
if (data->reset_mask == 0)
|
||||
return;
|
||||
|
||||
reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
|
||||
if (!reset_data)
|
||||
return;
|
||||
|
||||
if (data->reset_needs_clk) {
|
||||
reset_data->clk = of_clk_get(node, 0);
|
||||
if (IS_ERR(reset_data->clk)) {
|
||||
pr_err("Could not get clock for reset controls\n");
|
||||
kfree(reset_data);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
reset_data->reg = reg;
|
||||
reset_data->lock = lock;
|
||||
reset_data->rcdev.nr_resets = __fls(data->reset_mask) + 1;
|
||||
reset_data->rcdev.ops = &sunxi_usb_reset_ops;
|
||||
reset_data->rcdev.of_node = node;
|
||||
reset_controller_register(&reset_data->rcdev);
|
||||
}
|
||||
|
||||
static const struct usb_clk_data sun4i_a10_usb_clk_data __initconst = {
|
||||
.clk_mask = BIT(8) | BIT(7) | BIT(6),
|
||||
.reset_mask = BIT(2) | BIT(1) | BIT(0),
|
||||
};
|
||||
|
||||
static DEFINE_SPINLOCK(sun4i_a10_usb_lock);
|
||||
|
||||
static void __init sun4i_a10_usb_setup(struct device_node *node)
|
||||
{
|
||||
sunxi_usb_clk_setup(node, &sun4i_a10_usb_clk_data, &sun4i_a10_usb_lock);
|
||||
}
|
||||
CLK_OF_DECLARE(sun4i_a10_usb, "allwinner,sun4i-a10-usb-clk", sun4i_a10_usb_setup);
|
||||
|
||||
static const struct usb_clk_data sun5i_a13_usb_clk_data __initconst = {
|
||||
.clk_mask = BIT(8) | BIT(6),
|
||||
.reset_mask = BIT(1) | BIT(0),
|
||||
};
|
||||
|
||||
static void __init sun5i_a13_usb_setup(struct device_node *node)
|
||||
{
|
||||
sunxi_usb_clk_setup(node, &sun5i_a13_usb_clk_data, &sun4i_a10_usb_lock);
|
||||
}
|
||||
CLK_OF_DECLARE(sun5i_a13_usb, "allwinner,sun5i-a13-usb-clk", sun5i_a13_usb_setup);
|
||||
|
||||
static const struct usb_clk_data sun6i_a31_usb_clk_data __initconst = {
|
||||
.clk_mask = BIT(18) | BIT(17) | BIT(16) | BIT(10) | BIT(9) | BIT(8),
|
||||
.reset_mask = BIT(2) | BIT(1) | BIT(0),
|
||||
};
|
||||
|
||||
static void __init sun6i_a31_usb_setup(struct device_node *node)
|
||||
{
|
||||
sunxi_usb_clk_setup(node, &sun6i_a31_usb_clk_data, &sun4i_a10_usb_lock);
|
||||
}
|
||||
CLK_OF_DECLARE(sun6i_a31_usb, "allwinner,sun6i-a31-usb-clk", sun6i_a31_usb_setup);
|
||||
|
||||
static const struct usb_clk_data sun9i_a80_usb_mod_data __initconst = {
|
||||
.clk_mask = BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1),
|
||||
.reset_mask = BIT(19) | BIT(18) | BIT(17),
|
||||
.reset_needs_clk = 1,
|
||||
};
|
||||
|
||||
static DEFINE_SPINLOCK(a80_usb_mod_lock);
|
||||
|
||||
static void __init sun9i_a80_usb_mod_setup(struct device_node *node)
|
||||
{
|
||||
sunxi_usb_clk_setup(node, &sun9i_a80_usb_mod_data, &a80_usb_mod_lock);
|
||||
}
|
||||
CLK_OF_DECLARE(sun9i_a80_usb_mod, "allwinner,sun9i-a80-usb-mod-clk", sun9i_a80_usb_mod_setup);
|
||||
|
||||
static const struct usb_clk_data sun9i_a80_usb_phy_data __initconst = {
|
||||
.clk_mask = BIT(10) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1),
|
||||
.reset_mask = BIT(21) | BIT(20) | BIT(19) | BIT(18) | BIT(17),
|
||||
.reset_needs_clk = 1,
|
||||
};
|
||||
|
||||
static DEFINE_SPINLOCK(a80_usb_phy_lock);
|
||||
|
||||
static void __init sun9i_a80_usb_phy_setup(struct device_node *node)
|
||||
{
|
||||
sunxi_usb_clk_setup(node, &sun9i_a80_usb_phy_data, &a80_usb_phy_lock);
|
||||
}
|
||||
CLK_OF_DECLARE(sun9i_a80_usb_phy, "allwinner,sun9i-a80-usb-phy-clk", sun9i_a80_usb_phy_setup);
|
||||
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