drm/i915: Read PSR caps/intermediate freqs/etc. only once on eDP
Currently we re-read a bunch of static eDP panel caps from the DPCD
over and over again. Let's do it only once to save some time and effort.
v2: Make thing less confusing with intel_edp_init_dpcd() (Chris)
Move no_aux_handshake setup in there as well
v3: Move tps3/rate printout to intel_dp_long_pulse() so that
we'll still get them on eDP as well
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v1)
Link: http://patchwork.freedesktop.org/patch/msgid/1469800359-7087-1-git-send-email-ville.syrjala@linux.intel.com
This commit is contained in:
Ville Syrjälä
Родитель
1dd5b6f202
Коммит
fe5a66f91c
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@ -3395,20 +3395,94 @@ intel_dp_link_down(struct intel_dp *intel_dp)
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}
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static bool
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intel_dp_get_dpcd(struct intel_dp *intel_dp)
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intel_dp_read_dpcd(struct intel_dp *intel_dp)
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{
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struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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struct drm_device *dev = dig_port->base.base.dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
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sizeof(intel_dp->dpcd)) < 0)
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return false; /* aux transfer failed */
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DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
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if (intel_dp->dpcd[DP_DPCD_REV] == 0)
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return false; /* DPCD not present */
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return intel_dp->dpcd[DP_DPCD_REV] != 0;
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}
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static bool
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intel_edp_init_dpcd(struct intel_dp *intel_dp)
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{
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struct drm_i915_private *dev_priv =
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to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
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/* this function is meant to be called only once */
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WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
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if (!intel_dp_read_dpcd(intel_dp))
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return false;
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if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
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dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
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DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
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/* Check if the panel supports PSR */
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drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
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intel_dp->psr_dpcd,
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sizeof(intel_dp->psr_dpcd));
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if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
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dev_priv->psr.sink_support = true;
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DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
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}
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if (INTEL_GEN(dev_priv) >= 9 &&
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(intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
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uint8_t frame_sync_cap;
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dev_priv->psr.sink_support = true;
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drm_dp_dpcd_read(&intel_dp->aux,
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DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
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&frame_sync_cap, 1);
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dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
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/* PSR2 needs frame sync as well */
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dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
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DRM_DEBUG_KMS("PSR2 %s on sink",
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dev_priv->psr.psr2_support ? "supported" : "not supported");
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}
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/* Read the eDP Display control capabilities registers */
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if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
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drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
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intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd) ==
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sizeof(intel_dp->edp_dpcd)))
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DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
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intel_dp->edp_dpcd);
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/* Intermediate frequency support */
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if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */
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__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
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int i;
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drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
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sink_rates, sizeof(sink_rates));
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for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
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int val = le16_to_cpu(sink_rates[i]);
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if (val == 0)
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break;
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/* Value read is in kHz while drm clock is saved in deca-kHz */
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intel_dp->sink_rates[i] = (val * 200) / 10;
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}
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intel_dp->num_sink_rates = i;
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}
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return true;
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}
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static bool
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intel_dp_get_dpcd(struct intel_dp *intel_dp)
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{
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if (!intel_dp_read_dpcd(intel_dp))
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return false;
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if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
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&intel_dp->sink_count, 1) < 0)
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@ -3431,68 +3505,6 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
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if (!is_edp(intel_dp) && !intel_dp->sink_count)
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return false;
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/* Check if the panel supports PSR */
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memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
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if (is_edp(intel_dp)) {
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drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
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intel_dp->psr_dpcd,
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sizeof(intel_dp->psr_dpcd));
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if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
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dev_priv->psr.sink_support = true;
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DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
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}
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if (INTEL_INFO(dev)->gen >= 9 &&
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(intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
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uint8_t frame_sync_cap;
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dev_priv->psr.sink_support = true;
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drm_dp_dpcd_read(&intel_dp->aux,
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DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
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&frame_sync_cap, 1);
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dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
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/* PSR2 needs frame sync as well */
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dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
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DRM_DEBUG_KMS("PSR2 %s on sink",
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dev_priv->psr.psr2_support ? "supported" : "not supported");
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}
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/* Read the eDP Display control capabilities registers */
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memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));
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if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
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(drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
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intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
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sizeof(intel_dp->edp_dpcd)))
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DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
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intel_dp->edp_dpcd);
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}
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DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
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yesno(intel_dp_source_supports_hbr2(intel_dp)),
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yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
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/* Intermediate frequency support */
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if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp v1.4 or higher */
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__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
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int i;
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drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
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sink_rates, sizeof(sink_rates));
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for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
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int val = le16_to_cpu(sink_rates[i]);
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if (val == 0)
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break;
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/* Value read is in kHz while drm clock is saved in deca-kHz */
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intel_dp->sink_rates[i] = (val * 200) / 10;
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}
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intel_dp->num_sink_rates = i;
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}
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intel_dp_print_rates(intel_dp);
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if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
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DP_DWN_STRM_PORT_PRESENT))
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return true; /* native DP sink */
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@ -4252,6 +4264,12 @@ intel_dp_long_pulse(struct intel_connector *intel_connector)
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if (intel_encoder->type != INTEL_OUTPUT_EDP)
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intel_encoder->type = INTEL_OUTPUT_DP;
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DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
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yesno(intel_dp_source_supports_hbr2(intel_dp)),
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yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
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intel_dp_print_rates(intel_dp);
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intel_dp_probe_oui(intel_dp);
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ret = intel_dp_probe_mst(intel_dp);
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@ -5413,14 +5431,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
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pps_unlock(intel_dp);
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/* Cache DPCD and EDID for edp. */
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has_dpcd = intel_dp_get_dpcd(intel_dp);
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has_dpcd = intel_edp_init_dpcd(intel_dp);
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if (has_dpcd) {
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if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
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dev_priv->no_aux_handshake =
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intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
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DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
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} else {
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if (!has_dpcd) {
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/* if this fails, presume the device is a ghost */
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DRM_INFO("failed to retrieve link info, disabling eDP\n");
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goto out_vdd_off;
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