net/mlx4_core: Respond to operation request by firmware
This commit adds new firmware command and new firmware event. The firmware raises the MLX4_EVENT_TYPE_OP_REQUIRED event in order to signal the driver it needs to perform an administrative operation throughout the MLX4_CMD_GET_OP_REQ command. At the moment the supported operation is adding/removing multicast entries which are used by the firmware for handling NCSI traffic in B0 steering mode. Also, had to swap the order of mlx4_init_mcg_table() and mlx4_init_eq_table() to make sure that driver will get events only after resources are initialized to handle it. Signed-off-by: Yevgeny Petrilin <yevgenyp@mellanox.com> Signed-off-by: Jack Morgenstein <jackm@dev.mellanox.com> Signed-off-by: Eugenia Emantayev <eugenia@mellanox.com> Signed-off-by: Amir Vadai <amirv@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Родитель
2d4b646613
Коммит
fe6f700d6c
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@ -809,6 +809,15 @@ int MLX4_CMD_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave,
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return -EPERM;
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}
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int MLX4_CMD_GET_OP_REQ_wrapper(struct mlx4_dev *dev, int slave,
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struct mlx4_vhcr *vhcr,
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struct mlx4_cmd_mailbox *inbox,
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struct mlx4_cmd_mailbox *outbox,
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struct mlx4_cmd_info *cmd)
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{
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return -EPERM;
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}
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int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
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struct mlx4_vhcr *vhcr,
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struct mlx4_cmd_mailbox *inbox,
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@ -1251,6 +1260,15 @@ static struct mlx4_cmd_info cmd_info[] = {
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.verify = NULL,
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.wrapper = MLX4_CMD_UPDATE_QP_wrapper
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},
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{
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.opcode = MLX4_CMD_GET_OP_REQ,
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.has_inbox = false,
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.has_outbox = false,
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.out_is_imm = false,
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.encode_slave_id = false,
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.verify = NULL,
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.wrapper = MLX4_CMD_GET_OP_REQ_wrapper,
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},
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{
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.opcode = MLX4_CMD_CONF_SPECIAL_QP,
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.has_inbox = false,
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@ -79,6 +79,7 @@ enum {
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(1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE) | \
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(1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) | \
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(1ull << MLX4_EVENT_TYPE_CMD) | \
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(1ull << MLX4_EVENT_TYPE_OP_REQUIRED) | \
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(1ull << MLX4_EVENT_TYPE_COMM_CHANNEL) | \
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(1ull << MLX4_EVENT_TYPE_FLR_EVENT) | \
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(1ull << MLX4_EVENT_TYPE_FATAL_WARNING))
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@ -629,6 +630,14 @@ static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq)
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mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn);
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break;
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case MLX4_EVENT_TYPE_OP_REQUIRED:
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atomic_inc(&priv->opreq_count);
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/* FW commands can't be executed from interrupt context
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* working in deferred task
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*/
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queue_work(mlx4_wq, &priv->opreq_task);
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break;
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case MLX4_EVENT_TYPE_COMM_CHANNEL:
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if (!mlx4_is_master(dev)) {
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mlx4_warn(dev, "Received comm channel event "
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@ -1705,3 +1705,107 @@ int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
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MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
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}
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EXPORT_SYMBOL_GPL(mlx4_wol_write);
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enum {
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ADD_TO_MCG = 0x26,
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};
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void mlx4_opreq_action(struct work_struct *work)
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{
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struct mlx4_priv *priv = container_of(work, struct mlx4_priv,
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opreq_task);
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struct mlx4_dev *dev = &priv->dev;
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int num_tasks = atomic_read(&priv->opreq_count);
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struct mlx4_cmd_mailbox *mailbox;
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struct mlx4_mgm *mgm;
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u32 *outbox;
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u32 modifier;
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u16 token;
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u16 type_m;
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u16 type;
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int err;
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u32 num_qps;
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struct mlx4_qp qp;
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int i;
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u8 rem_mcg;
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u8 prot;
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#define GET_OP_REQ_MODIFIER_OFFSET 0x08
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#define GET_OP_REQ_TOKEN_OFFSET 0x14
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#define GET_OP_REQ_TYPE_OFFSET 0x1a
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#define GET_OP_REQ_DATA_OFFSET 0x20
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mailbox = mlx4_alloc_cmd_mailbox(dev);
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if (IS_ERR(mailbox)) {
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mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n");
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return;
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}
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outbox = mailbox->buf;
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while (num_tasks) {
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err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
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MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
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MLX4_CMD_NATIVE);
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if (err) {
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mlx4_err(dev, "Failed to retreive required operation: %d\n",
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err);
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return;
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}
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MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET);
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MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET);
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MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET);
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type_m = type >> 12;
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type &= 0xfff;
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switch (type) {
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case ADD_TO_MCG:
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if (dev->caps.steering_mode ==
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MLX4_STEERING_MODE_DEVICE_MANAGED) {
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mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n");
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err = EPERM;
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break;
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}
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mgm = (struct mlx4_mgm *)((u8 *)(outbox) +
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GET_OP_REQ_DATA_OFFSET);
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num_qps = be32_to_cpu(mgm->members_count) &
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MGM_QPN_MASK;
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rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1;
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prot = ((u8 *)(&mgm->members_count))[0] >> 6;
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for (i = 0; i < num_qps; i++) {
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qp.qpn = be32_to_cpu(mgm->qp[i]);
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if (rem_mcg)
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err = mlx4_multicast_detach(dev, &qp,
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mgm->gid,
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prot, 0);
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else
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err = mlx4_multicast_attach(dev, &qp,
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mgm->gid,
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mgm->gid[5]
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, 0, prot,
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NULL);
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if (err)
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break;
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}
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break;
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default:
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mlx4_warn(dev, "Bad type for required operation\n");
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err = EINVAL;
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break;
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}
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err = mlx4_cmd(dev, 0, ((u32) err | cpu_to_be32(token) << 16),
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1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
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MLX4_CMD_NATIVE);
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if (err) {
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mlx4_err(dev, "Failed to acknowledge required request: %d\n",
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err);
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goto out;
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}
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memset(outbox, 0, 0xffc);
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num_tasks = atomic_dec_return(&priv->opreq_count);
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}
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out:
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mlx4_free_cmd_mailbox(dev, mailbox);
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}
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@ -220,5 +220,6 @@ int mlx4_MAP_ICM_AUX(struct mlx4_dev *dev, struct mlx4_icm *icm);
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int mlx4_UNMAP_ICM_AUX(struct mlx4_dev *dev);
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int mlx4_NOP(struct mlx4_dev *dev);
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int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg);
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void mlx4_opreq_action(struct work_struct *work);
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#endif /* MLX4_FW_H */
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@ -1692,11 +1692,19 @@ static int mlx4_setup_hca(struct mlx4_dev *dev)
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goto err_xrcd_table_free;
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}
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if (!mlx4_is_slave(dev)) {
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err = mlx4_init_mcg_table(dev);
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if (err) {
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mlx4_err(dev, "Failed to initialize multicast group table, aborting.\n");
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goto err_mr_table_free;
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}
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}
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err = mlx4_init_eq_table(dev);
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if (err) {
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mlx4_err(dev, "Failed to initialize "
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"event queue table, aborting.\n");
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goto err_mr_table_free;
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goto err_mcg_table_free;
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}
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err = mlx4_cmd_use_events(dev);
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@ -1746,19 +1754,10 @@ static int mlx4_setup_hca(struct mlx4_dev *dev)
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goto err_srq_table_free;
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}
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if (!mlx4_is_slave(dev)) {
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err = mlx4_init_mcg_table(dev);
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if (err) {
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mlx4_err(dev, "Failed to initialize "
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"multicast group table, aborting.\n");
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goto err_qp_table_free;
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}
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}
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err = mlx4_init_counters_table(dev);
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if (err && err != -ENOENT) {
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mlx4_err(dev, "Failed to initialize counters table, aborting.\n");
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goto err_mcg_table_free;
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goto err_qp_table_free;
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}
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if (!mlx4_is_slave(dev)) {
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@ -1803,9 +1802,6 @@ static int mlx4_setup_hca(struct mlx4_dev *dev)
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err_counters_table_free:
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mlx4_cleanup_counters_table(dev);
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err_mcg_table_free:
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mlx4_cleanup_mcg_table(dev);
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err_qp_table_free:
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mlx4_cleanup_qp_table(dev);
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@ -1821,6 +1817,10 @@ err_cmd_poll:
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err_eq_table_free:
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mlx4_cleanup_eq_table(dev);
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err_mcg_table_free:
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if (!mlx4_is_slave(dev))
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mlx4_cleanup_mcg_table(dev);
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err_mr_table_free:
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mlx4_cleanup_mr_table(dev);
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@ -2197,6 +2197,9 @@ static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data)
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}
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}
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atomic_set(&priv->opreq_count, 0);
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INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
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/*
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* Now reset the HCA before we touch the PCI capabilities or
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* attempt a firmware command, since a boot ROM may have left
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@ -2315,12 +2318,12 @@ err_port:
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mlx4_cleanup_port_info(&priv->port[port]);
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mlx4_cleanup_counters_table(dev);
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mlx4_cleanup_mcg_table(dev);
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mlx4_cleanup_qp_table(dev);
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mlx4_cleanup_srq_table(dev);
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mlx4_cleanup_cq_table(dev);
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mlx4_cmd_use_polling(dev);
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mlx4_cleanup_eq_table(dev);
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mlx4_cleanup_mcg_table(dev);
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mlx4_cleanup_mr_table(dev);
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mlx4_cleanup_xrcd_table(dev);
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mlx4_cleanup_pd_table(dev);
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@ -2403,12 +2406,12 @@ static void mlx4_remove_one(struct pci_dev *pdev)
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RES_TR_FREE_SLAVES_ONLY);
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mlx4_cleanup_counters_table(dev);
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mlx4_cleanup_mcg_table(dev);
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mlx4_cleanup_qp_table(dev);
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mlx4_cleanup_srq_table(dev);
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mlx4_cleanup_cq_table(dev);
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mlx4_cmd_use_polling(dev);
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mlx4_cleanup_eq_table(dev);
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mlx4_cleanup_mcg_table(dev);
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mlx4_cleanup_mr_table(dev);
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mlx4_cleanup_xrcd_table(dev);
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mlx4_cleanup_pd_table(dev);
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@ -39,19 +39,8 @@
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#include "mlx4.h"
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#define MGM_QPN_MASK 0x00FFFFFF
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#define MGM_BLCK_LB_BIT 30
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static const u8 zero_gid[16]; /* automatically initialized to 0 */
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struct mlx4_mgm {
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__be32 next_gid_index;
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__be32 members_count;
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u32 reserved[2];
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u8 gid[16];
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__be32 qp[MLX4_MAX_QP_PER_MGM];
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};
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int mlx4_get_mgm_entry_size(struct mlx4_dev *dev)
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{
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return 1 << dev->oper_log_mgm_entry_size;
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@ -554,6 +554,17 @@ struct mlx4_mfunc {
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struct mlx4_mfunc_master_ctx master;
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};
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#define MGM_QPN_MASK 0x00FFFFFF
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#define MGM_BLCK_LB_BIT 30
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struct mlx4_mgm {
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__be32 next_gid_index;
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__be32 members_count;
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u32 reserved[2];
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u8 gid[16];
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__be32 qp[MLX4_MAX_QP_PER_MGM];
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};
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struct mlx4_cmd {
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struct pci_pool *pool;
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void __iomem *hcr;
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@ -802,6 +813,8 @@ struct mlx4_priv {
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u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
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__be64 slave_node_guids[MLX4_MFUNC_MAX];
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atomic_t opreq_count;
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struct work_struct opreq_task;
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};
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static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
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@ -69,6 +69,7 @@ enum {
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MLX4_CMD_SET_ICM_SIZE = 0xffd,
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/*master notify fw on finish for slave's flr*/
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MLX4_CMD_INFORM_FLR_DONE = 0x5b,
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MLX4_CMD_GET_OP_REQ = 0x59,
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/* TPT commands */
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MLX4_CMD_SW2HW_MPT = 0xd,
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@ -207,6 +207,7 @@ enum mlx4_event {
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MLX4_EVENT_TYPE_CMD = 0x0a,
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MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
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MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
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MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a,
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MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
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MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
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MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
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