ARM: SoC fixes for 3.11-rc
This is a largeish batch of fixes, mostly because I missed -rc2 due to travel/vacation. So in number these are a bit more than ideal unless you amortize them over two -rcs. Quick breakdown: - Defconfig updates - Making multi_v7_defconfig useful on more hardware to encourage single-image usage - Davinci and nomadik updates due to new code merged this merge window - Fixes for UART on Samsung platforms, both PM and clock-related - A handful of warning fixes from defconfig builds, including for max8925 backlight and pxamci (both with appropriate acks) - Exynos5440 fixes for LPAE configuration, PM - ...plus a bunch of other smaller changes all over the place I expect to switch to regressions-or-severe-bugs-only fixes from here on out. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJR8cSDAAoJEIwa5zzehBx3dgsQAIRYV0xKDWYUgzvLGx1Gn/eC tUw5JeT13eSyEzPL8vAHyMFkI/N7yUzExMjzULPsDXiKHCkRDosLqwxNRFCSVBEv vp6ipoa75t+l7sys4lOoTVZGY+Pt0SJDIs1jpkTzWPt+BtFanKpaOFJN0hCMZh1j x0ls+TX4UUsl7MhxtTSEHSMIjt+8bz4rxE6shQOSRePGHkQKrsS1VrFAIC+u1x5b bkAU3KdLCu5i4qNSU5Niqg2VgRWzxrkR1lQiY8e0BtGqmret9itYFsRWwdZ0qrLQ Q6aYnR6O/uWH1i2g+Fcl+R4FJo96hy7KqbI0wJmgKlpG5nRQWhCXyYWo86xjw97G JOA4EHyV+wcmQIo7ZwjYRae7fJYQeRBdUT6/rVnlW++Hi7ZeHI2DLyNLkwG7iXat iD3OPgzsQ2beK5QTB6fL8iTv+q4o4hXHFDmFukjPYdR3NPHNaJ+uuaI78rUAblmc RoQ38UzSL82kiseaFP8b7sU9P1JF2hopPDLA7rdSyKBCLczEhzXvgXG1XJVwOdmA FTBf1g9taawLAxzaJOC82wYrTCLWX2dzv3DeCbaEpzYq1nblJrqYLerQ6Rb0c5xy V7a+h4aQhLsZvA2Qu7NGBD0wv47d7r5UAPUS1i4Em1Yi+syrBNY4XCiJhBH0fZc5 k4PXz5wVMhpyVLrX6bVd =XOG3 -----END PGP SIGNATURE----- Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Olof Johansson: "This is a largeish batch of fixes, mostly because I missed -rc2 due to travel/vacation. So in number these are a bit more than ideal unless you amortize them over two -rcs. Quick breakdown: - Defconfig updates - Making multi_v7_defconfig useful on more hardware to encourage single-image usage - Davinci and nomadik updates due to new code merged this merge window - Fixes for UART on Samsung platforms, both PM and clock-related - A handful of warning fixes from defconfig builds, including for max8925 backlight and pxamci (both with appropriate acks) - Exynos5440 fixes for LPAE configuration, PM - ...plus a bunch of other smaller changes all over the place I expect to switch to regressions-or-severe-bugs-only fixes from here on out" * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (37 commits) mfd: max8925: fix dt code for backlight ARM: omap5: Only select errata 798181 if SMP ARM: EXYNOS: Update CONFIG_ARCH_NR_GPIO for Exynos ARM: EXYNOS: Fix low level debug support ARM: SAMSUNG: Save/restore only selected uart's registers ARM: SAMSUNG: Add SAMSUNG_PM config option to select pm ARM: S3C24XX: Add missing clkdev entries for s3c2440 UART ARM: multi_v7_defconfig: Select USB chipidea driver ARM: pxa: propagate errors from regulator_enable() to pxamci ARM: zynq: fix compilation warning ARM: keystone: fix compilation warning ARM: highbank: Only touch common coherency control register fields ARM: footbridge: fix overlapping PCI mappings dmaengine: shdma: fix a build failure on platforms with no DMA support ARM: STi: Set correct ARM ERRATAs. ARM: dts: STi: Fix pinconf setup for STiH416 serial2 ARM: nomadik: configure for NO_HZ and HRTIMERS ARM: nomadik: update defconfig base ARM: nomadik: Update MMC defconfigs ARM: davinci: defconfig: enable EDMA driver ...
This commit is contained in:
Коммит
fef36a7a31
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@ -98,6 +98,7 @@ clocks and IDs.
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fpm 83
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mpll_osc_sel 84
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mpll_sel 85
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spll_gate 86
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Examples:
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@ -1600,8 +1600,7 @@ config LOCAL_TIMERS
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config ARCH_NR_GPIO
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int
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default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
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default 512 if SOC_OMAP5
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default 512 if ARCH_KEYSTONE
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default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5
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default 392 if ARCH_U8500
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default 352 if ARCH_VT8500
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default 288 if ARCH_SUNXI
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@ -147,7 +147,7 @@
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reg = <0x0a>;
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VDDA-supply = <®_3p3v>;
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VDDIO-supply = <®_3p3v>;
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clocks = <&saif0>;
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};
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pcf8563: rtc@51 {
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@ -195,7 +195,7 @@
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reg = <0x0a>;
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VDDA-supply = <®_3p3v>;
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VDDIO-supply = <®_3p3v>;
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clocks = <&saif0>;
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};
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at24@51 {
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@ -184,7 +184,7 @@
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reg = <0x0a>;
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VDDA-supply = <®_3p3v>;
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VDDIO-supply = <®_3p3v>;
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clocks = <&saif0>;
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};
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eeprom: eeprom@51 {
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@ -837,6 +837,7 @@
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compatible = "fsl,imx28-saif";
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reg = <0x80042000 0x2000>;
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interrupts = <59 80>;
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#clock-cells = <0>;
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clocks = <&clks 53>;
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dmas = <&dma_apbx 4>;
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dma-names = "rx-tx";
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@ -61,6 +61,16 @@
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mux-int-port = <2>;
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mux-ext-port = <3>;
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};
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clocks {
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clk_26M: codec_clock {
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compatible = "fixed-clock";
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reg=<0>;
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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gpios = <&gpio4 26 1>;
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};
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};
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};
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&esdhc1 {
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@ -229,6 +239,7 @@
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MX51_PAD_EIM_A27__GPIO2_21 0x5
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MX51_PAD_CSPI1_SS0__GPIO4_24 0x85
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MX51_PAD_CSPI1_SS1__GPIO4_25 0x85
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MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000
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>;
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};
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};
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@ -255,7 +266,7 @@
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sgtl5000: codec@0a {
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compatible = "fsl,sgtl5000";
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reg = <0x0a>;
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clock-frequency = <26000000>;
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clocks = <&clk_26M>;
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VDDA-supply = <&vdig_reg>;
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VDDIO-supply = <&vvideo_reg>;
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};
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@ -27,7 +27,7 @@
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backlight {
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compatible = "pwm-backlight";
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pwms = <&pwm2 0 50000 0 0>;
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pwms = <&pwm2 0 50000>;
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brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>;
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default-brightness-level = <10>;
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enable-gpios = <&gpio7 7 0>;
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@ -725,15 +725,15 @@
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uart1 {
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pinctrl_uart1_1: uart1grp-1 {
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fsl,pins = <
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MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1c5
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MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1c5
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MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
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MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
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>;
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};
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pinctrl_uart1_2: uart1grp-2 {
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fsl,pins = <
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MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1c5
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MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5
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MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
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MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
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>;
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};
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@ -748,8 +748,8 @@
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uart2 {
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pinctrl_uart2_1: uart2grp-1 {
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fsl,pins = <
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MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
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MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
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MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
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MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
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>;
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};
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@ -766,17 +766,17 @@
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uart3 {
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pinctrl_uart3_1: uart3grp-1 {
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fsl,pins = <
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MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
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MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
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MX53_PAD_PATA_DA_1__UART3_CTS 0x1c5
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MX53_PAD_PATA_DA_2__UART3_RTS 0x1c5
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MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
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MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
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MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
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MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
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>;
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};
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pinctrl_uart3_2: uart3grp-2 {
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fsl,pins = <
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MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
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MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
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MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
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MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
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>;
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};
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@ -785,8 +785,8 @@
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uart4 {
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pinctrl_uart4_1: uart4grp-1 {
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fsl,pins = <
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MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1c5
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MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1c5
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MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4
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MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4
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>;
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};
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};
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@ -794,8 +794,8 @@
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uart5 {
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pinctrl_uart5_1: uart5grp-1 {
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fsl,pins = <
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MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1c5
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MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1c5
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MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1e4
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MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1e4
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>;
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};
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};
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@ -166,6 +166,15 @@
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reg = <0x9000 0x100>;
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st,bank-name = "PIO31";
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};
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serial2-oe {
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pinctrl_serial2_oe: serial2-1 {
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st,pins {
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output-enable = <&PIO11 3 ALT2 OUT>;
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};
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};
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};
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};
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pin-controller-rear {
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@ -218,7 +227,6 @@
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st,pins {
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tx = <&PIO17 4 ALT2 OUT>;
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rx = <&PIO17 5 ALT2 IN>;
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output-enable = <&PIO11 3 ALT2 OUT>;
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};
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};
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};
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@ -79,7 +79,7 @@
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interrupts = <0 197 0>;
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clocks = <&CLK_S_ICN_REG_0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_serial2>;
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pinctrl-0 = <&pinctrl_serial2 &pinctrl_serial2_oe>;
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};
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/* SBC_UART1 */
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@ -47,6 +47,12 @@
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regulator-max-microvolt = <3150000>;
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};
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vmmc2: regulator-vmmc2 {
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compatible = "ti,twl4030-vmmc2";
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regulator-min-microvolt = <1850000>;
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regulator-max-microvolt = <3150000>;
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};
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vusb1v5: regulator-vusb1v5 {
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compatible = "ti,twl4030-vusb1v5";
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};
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@ -442,8 +442,8 @@
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compatible = "fsl,mvf600-fec";
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reg = <0x400d0000 0x1000>;
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interrupts = <0 78 0x04>;
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clocks = <&clks VF610_CLK_ENET>,
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<&clks VF610_CLK_ENET>,
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clocks = <&clks VF610_CLK_ENET0>,
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<&clks VF610_CLK_ENET0>,
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<&clks VF610_CLK_ENET>;
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clock-names = "ipg", "ahb", "ptp";
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status = "disabled";
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@ -453,8 +453,8 @@
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compatible = "fsl,mvf600-fec";
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reg = <0x400d1000 0x1000>;
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interrupts = <0 79 0x04>;
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clocks = <&clks VF610_CLK_ENET>,
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<&clks VF610_CLK_ENET>,
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clocks = <&clks VF610_CLK_ENET1>,
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<&clks VF610_CLK_ENET1>,
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<&clks VF610_CLK_ENET>;
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clock-names = "ipg", "ahb", "ptp";
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status = "disabled";
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@ -26,7 +26,6 @@
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/edma.h>
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#include <linux/err.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_dma.h>
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@ -102,6 +102,8 @@ CONFIG_SND_SOC=m
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CONFIG_SND_DAVINCI_SOC=m
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# CONFIG_HID_SUPPORT is not set
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# CONFIG_USB_SUPPORT is not set
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CONFIG_DMADEVICES=y
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CONFIG_TI_EDMA=y
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CONFIG_EXT2_FS=y
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CONFIG_EXT3_FS=y
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CONFIG_XFS_FS=m
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@ -162,6 +162,8 @@ CONFIG_LEDS_TRIGGERS=y
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CONFIG_LEDS_TRIGGER_TIMER=m
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CONFIG_LEDS_TRIGGER_HEARTBEAT=m
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CONFIG_RTC_CLASS=y
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CONFIG_DMADEVICES=y
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CONFIG_TI_EDMA=y
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CONFIG_EXT2_FS=y
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CONFIG_EXT3_FS=y
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CONFIG_XFS_FS=m
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@ -53,6 +53,7 @@ CONFIG_IP_PNP=y
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CONFIG_IP_PNP_DHCP=y
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CONFIG_DEVTMPFS=y
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CONFIG_DEVTMPFS_MOUNT=y
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CONFIG_OMAP_OCP2SCP=y
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CONFIG_BLK_DEV_SD=y
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CONFIG_ATA=y
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CONFIG_SATA_AHCI_PLATFORM=y
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@ -61,6 +62,7 @@ CONFIG_SATA_MV=y
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CONFIG_NETDEVICES=y
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CONFIG_SUN4I_EMAC=y
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CONFIG_NET_CALXEDA_XGMAC=y
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CONFIG_KS8851=y
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CONFIG_SMSC911X=y
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CONFIG_STMMAC_ETH=y
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CONFIG_MDIO_SUN4I=y
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@ -89,6 +91,7 @@ CONFIG_I2C_DESIGNWARE_PLATFORM=y
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CONFIG_I2C_SIRF=y
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CONFIG_I2C_TEGRA=y
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CONFIG_SPI=y
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CONFIG_SPI_OMAP24XX=y
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CONFIG_SPI_PL022=y
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CONFIG_SPI_SIRF=y
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CONFIG_SPI_TEGRA114=y
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|
@ -111,11 +114,12 @@ CONFIG_FB_SIMPLE=y
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CONFIG_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_MXC=y
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CONFIG_USB_EHCI_TEGRA=y
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CONFIG_USB_EHCI_HCD_PLATFORM=y
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CONFIG_USB_ISP1760_HCD=y
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CONFIG_USB_STORAGE=y
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CONFIG_USB_CHIPIDEA=y
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CONFIG_USB_CHIPIDEA_HOST=y
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CONFIG_AB8500_USB=y
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CONFIG_NOP_USB_XCEIV=y
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CONFIG_OMAP_USB2=y
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|
|
|
@ -1,6 +1,8 @@
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# CONFIG_LOCALVERSION_AUTO is not set
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# CONFIG_SWAP is not set
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CONFIG_SYSVIPC=y
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CONFIG_NO_HZ_IDLE=y
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CONFIG_HIGH_RES_TIMERS=y
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CONFIG_IKCONFIG=y
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CONFIG_IKCONFIG_PROC=y
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CONFIG_LOG_BUF_SHIFT=14
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|
@ -48,7 +50,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
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CONFIG_MTD=y
|
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CONFIG_MTD_TESTS=m
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CONFIG_MTD_CMDLINE_PARTS=y
|
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CONFIG_MTD_CHAR=y
|
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CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_NAND_ECC_SMC=y
|
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CONFIG_MTD_NAND=y
|
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|
@ -94,8 +95,10 @@ CONFIG_I2C_GPIO=y
|
|||
CONFIG_I2C_NOMADIK=y
|
||||
CONFIG_DEBUG_GPIO=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_CLKGATE=y
|
||||
CONFIG_MMC_UNSAFE_RESUME=y
|
||||
# CONFIG_MMC_BLOCK_BOUNCE is not set
|
||||
CONFIG_MMC_ARMMMCI=y
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
|
|
|
@ -505,7 +505,7 @@ static struct vpbe_output dm365evm_vpbe_outputs[] = {
|
|||
/*
|
||||
* Amplifiers on the board
|
||||
*/
|
||||
struct ths7303_platform_data ths7303_pdata = {
|
||||
static struct ths7303_platform_data ths7303_pdata = {
|
||||
.ch_1 = 3,
|
||||
.ch_2 = 3,
|
||||
.ch_3 = 3,
|
||||
|
|
|
@ -860,7 +860,7 @@ static struct platform_device dm355_vpbe_display = {
|
|||
},
|
||||
};
|
||||
|
||||
struct venc_platform_data dm355_venc_pdata = {
|
||||
static struct venc_platform_data dm355_venc_pdata = {
|
||||
.setup_pinmux = dm355_vpbe_setup_pinmux,
|
||||
.setup_clock = dm355_venc_setup_clock,
|
||||
};
|
||||
|
|
|
@ -1349,7 +1349,7 @@ static struct platform_device dm365_vpbe_display = {
|
|||
},
|
||||
};
|
||||
|
||||
struct venc_platform_data dm365_venc_pdata = {
|
||||
static struct venc_platform_data dm365_venc_pdata = {
|
||||
.setup_pinmux = dm365_vpbe_setup_pinmux,
|
||||
.setup_clock = dm365_venc_setup_clock,
|
||||
};
|
||||
|
|
|
@ -92,6 +92,7 @@ config SOC_EXYNOS5440
|
|||
bool "SAMSUNG EXYNOS5440"
|
||||
default y
|
||||
depends on ARCH_EXYNOS5
|
||||
select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
|
||||
select ARCH_HAS_OPP
|
||||
select HAVE_ARM_ARCH_TIMER
|
||||
select AUTO_ZRELADDR
|
||||
|
|
|
@ -14,7 +14,7 @@ obj- :=
|
|||
|
||||
obj-$(CONFIG_ARCH_EXYNOS) += common.o
|
||||
|
||||
obj-$(CONFIG_PM) += pm.o
|
||||
obj-$(CONFIG_S5P_PM) += pm.o
|
||||
obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
|
||||
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
|
||||
|
||||
|
|
|
@ -58,7 +58,6 @@ static const char name_exynos5440[] = "EXYNOS5440";
|
|||
|
||||
static void exynos4_map_io(void);
|
||||
static void exynos5_map_io(void);
|
||||
static void exynos5440_map_io(void);
|
||||
static int exynos_init(void);
|
||||
|
||||
static struct cpu_table cpu_ids[] __initdata = {
|
||||
|
@ -95,7 +94,6 @@ static struct cpu_table cpu_ids[] __initdata = {
|
|||
}, {
|
||||
.idcode = EXYNOS5440_SOC_ID,
|
||||
.idmask = EXYNOS5_SOC_MASK,
|
||||
.map_io = exynos5440_map_io,
|
||||
.init = exynos_init,
|
||||
.name = name_exynos5440,
|
||||
},
|
||||
|
@ -149,11 +147,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
|
|||
.pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
|
||||
.length = SZ_64K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S3C_VA_UART,
|
||||
.pfn = __phys_to_pfn(EXYNOS4_PA_UART),
|
||||
.length = SZ_512K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_CMU,
|
||||
.pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
|
||||
|
@ -268,20 +261,6 @@ static struct map_desc exynos5_iodesc[] __initdata = {
|
|||
.pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
|
||||
.length = SZ_64K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S3C_VA_UART,
|
||||
.pfn = __phys_to_pfn(EXYNOS5_PA_UART),
|
||||
.length = SZ_512K,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct map_desc exynos5440_iodesc0[] __initdata = {
|
||||
{
|
||||
.virtual = (unsigned long)S3C_VA_UART,
|
||||
.pfn = __phys_to_pfn(EXYNOS5440_PA_UART0),
|
||||
.length = SZ_512K,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -388,11 +367,6 @@ static void __init exynos5_map_io(void)
|
|||
iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
|
||||
}
|
||||
|
||||
static void __init exynos5440_map_io(void)
|
||||
{
|
||||
iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
|
||||
}
|
||||
|
||||
void __init exynos_init_time(void)
|
||||
{
|
||||
of_clk_init(NULL);
|
||||
|
|
|
@ -97,6 +97,5 @@ struct exynos_pmu_conf {
|
|||
};
|
||||
|
||||
extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
|
||||
extern void s3c_cpu_resume(void);
|
||||
|
||||
#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
|
||||
|
|
|
@ -25,6 +25,7 @@
|
|||
#include <mach/regs-pmu.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/pm.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
|
|
|
@ -15,8 +15,13 @@
|
|||
|
||||
#define PLAT_PHYS_OFFSET UL(0x40000000)
|
||||
|
||||
#ifndef CONFIG_ARM_LPAE
|
||||
/* Maximum of 256MiB in one bank */
|
||||
#define MAX_PHYSMEM_BITS 32
|
||||
#define SECTION_SIZE_BITS 28
|
||||
#else
|
||||
#define MAX_PHYSMEM_BITS 36
|
||||
#define SECTION_SIZE_BITS 31
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_ARCH_MEMORY_H */
|
||||
|
|
|
@ -217,6 +217,9 @@ static __init int exynos_pm_drvinit(void)
|
|||
struct clk *pll_base;
|
||||
unsigned int tmp;
|
||||
|
||||
if (soc_is_exynos5440())
|
||||
return 0;
|
||||
|
||||
s3c_pm_init();
|
||||
|
||||
/* All wakeup disable */
|
||||
|
@ -340,6 +343,9 @@ static struct syscore_ops exynos_pm_syscore_ops = {
|
|||
|
||||
static __init int exynos_pm_syscore_init(void)
|
||||
{
|
||||
if (soc_is_exynos5440())
|
||||
return 0;
|
||||
|
||||
register_syscore_ops(&exynos_pm_syscore_ops);
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -276,8 +276,6 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys)
|
|||
|
||||
sys->mem_offset = DC21285_PCI_MEM;
|
||||
|
||||
pci_ioremap_io(0, DC21285_PCI_IO);
|
||||
|
||||
pci_add_resource_offset(&sys->resources, &res[0], sys->mem_offset);
|
||||
pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
|
||||
|
||||
|
|
|
@ -115,6 +115,7 @@ static int highbank_platform_notifier(struct notifier_block *nb,
|
|||
{
|
||||
struct resource *res;
|
||||
int reg = -1;
|
||||
u32 val;
|
||||
struct device *dev = __dev;
|
||||
|
||||
if (event != BUS_NOTIFY_ADD_DEVICE)
|
||||
|
@ -141,10 +142,10 @@ static int highbank_platform_notifier(struct notifier_block *nb,
|
|||
return NOTIFY_DONE;
|
||||
|
||||
if (of_property_read_bool(dev->of_node, "dma-coherent")) {
|
||||
writel(0xff31, sregs_base + reg);
|
||||
val = readl(sregs_base + reg);
|
||||
writel(val | 0xff01, sregs_base + reg);
|
||||
set_dma_ops(dev, &arm_coherent_dma_ops);
|
||||
} else
|
||||
writel(0, sregs_base + reg);
|
||||
}
|
||||
|
||||
return NOTIFY_OK;
|
||||
}
|
||||
|
|
|
@ -199,7 +199,8 @@ static const char *pcie_axi_sels[] = { "axi", "ahb", };
|
|||
static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_post_div", };
|
||||
static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
|
||||
static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", };
|
||||
static const char *emi_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
|
||||
static const char *emi_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", };
|
||||
static const char *emi_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
|
||||
static const char *vdo_axi_sels[] = { "axi", "ahb", };
|
||||
static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", };
|
||||
static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
|
||||
|
@ -392,7 +393,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
|||
clk[usdhc4_sel] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
|
||||
clk[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
|
||||
clk[emi_sel] = imx_clk_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels));
|
||||
clk[emi_slow_sel] = imx_clk_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_sels, ARRAY_SIZE(emi_sels));
|
||||
clk[emi_slow_sel] = imx_clk_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels));
|
||||
clk[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
|
||||
clk[vpu_axi_sel] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels));
|
||||
clk[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
|
||||
|
|
|
@ -183,6 +183,8 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
|
|||
clk[VF610_CLK_ENET_TS_SEL] = imx_clk_mux("enet_ts_sel", CCM_CSCMR2, 0, 3, enet_ts_sels, 7);
|
||||
clk[VF610_CLK_ENET] = imx_clk_gate("enet", "enet_sel", CCM_CSCDR1, 24);
|
||||
clk[VF610_CLK_ENET_TS] = imx_clk_gate("enet_ts", "enet_ts_sel", CCM_CSCDR1, 23);
|
||||
clk[VF610_CLK_ENET0] = imx_clk_gate2("enet0", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(0));
|
||||
clk[VF610_CLK_ENET1] = imx_clk_gate2("enet1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(1));
|
||||
|
||||
clk[VF610_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7));
|
||||
|
||||
|
|
|
@ -135,7 +135,7 @@
|
|||
#define MX27_INT_GPT4 (NR_IRQS_LEGACY + 4)
|
||||
#define MX27_INT_RTIC (NR_IRQS_LEGACY + 5)
|
||||
#define MX27_INT_CSPI3 (NR_IRQS_LEGACY + 6)
|
||||
#define MX27_INT_SDHC (NR_IRQS_LEGACY + 7)
|
||||
#define MX27_INT_MSHC (NR_IRQS_LEGACY + 7)
|
||||
#define MX27_INT_GPIO (NR_IRQS_LEGACY + 8)
|
||||
#define MX27_INT_SDHC3 (NR_IRQS_LEGACY + 9)
|
||||
#define MX27_INT_SDHC2 (NR_IRQS_LEGACY + 10)
|
||||
|
|
|
@ -49,7 +49,7 @@ static const char *keystone_match[] __initconst = {
|
|||
NULL,
|
||||
};
|
||||
|
||||
void keystone_restart(char mode, const char *cmd)
|
||||
void keystone_restart(enum reboot_mode mode, const char *cmd)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
|
|
|
@ -62,7 +62,7 @@ config SOC_OMAP5
|
|||
select HAVE_SMP
|
||||
select COMMON_CLK
|
||||
select HAVE_ARM_ARCH_TIMER
|
||||
select ARM_ERRATA_798181
|
||||
select ARM_ERRATA_798181 if SMP
|
||||
|
||||
config SOC_AM33XX
|
||||
bool "AM33XX support"
|
||||
|
|
|
@ -15,6 +15,7 @@
|
|||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/clk.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
|
@ -35,6 +36,21 @@ static struct of_device_id omap_dt_match_table[] __initdata = {
|
|||
{ }
|
||||
};
|
||||
|
||||
/*
|
||||
* Create alias for USB host PHY clock.
|
||||
* Remove this when clock phandle can be provided via DT
|
||||
*/
|
||||
static void __init legacy_init_ehci_clk(char *clkname)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = clk_add_alias("main_clk", NULL, clkname, NULL);
|
||||
if (ret) {
|
||||
pr_err("%s:Failed to add main_clk alias to %s :%d\n",
|
||||
__func__, clkname, ret);
|
||||
}
|
||||
}
|
||||
|
||||
static void __init omap_generic_init(void)
|
||||
{
|
||||
omap_sdrc_init(NULL, NULL);
|
||||
|
@ -45,10 +61,15 @@ static void __init omap_generic_init(void)
|
|||
* HACK: call display setup code for selected boards to enable omapdss.
|
||||
* This will be removed when omapdss supports DT.
|
||||
*/
|
||||
if (of_machine_is_compatible("ti,omap4-panda"))
|
||||
if (of_machine_is_compatible("ti,omap4-panda")) {
|
||||
omap4_panda_display_init_of();
|
||||
legacy_init_ehci_clk("auxclk3_ck");
|
||||
|
||||
}
|
||||
else if (of_machine_is_compatible("ti,omap4-sdp"))
|
||||
omap_4430sdp_display_init_of();
|
||||
else if (of_machine_is_compatible("ti,omap5-uevm"))
|
||||
legacy_init_ehci_clk("auxclk1_ck");
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SOC_OMAP2420
|
||||
|
|
|
@ -477,16 +477,24 @@ static int em_x270_usb_hub_init(void)
|
|||
/* USB Hub power-on and reset */
|
||||
gpio_direction_output(usb_hub_reset, 1);
|
||||
gpio_direction_output(GPIO9_USB_VBUS_EN, 0);
|
||||
regulator_enable(em_x270_usb_ldo);
|
||||
err = regulator_enable(em_x270_usb_ldo);
|
||||
if (err)
|
||||
goto err_free_rst_gpio;
|
||||
|
||||
gpio_set_value(usb_hub_reset, 0);
|
||||
gpio_set_value(usb_hub_reset, 1);
|
||||
regulator_disable(em_x270_usb_ldo);
|
||||
regulator_enable(em_x270_usb_ldo);
|
||||
err = regulator_enable(em_x270_usb_ldo);
|
||||
if (err)
|
||||
goto err_free_rst_gpio;
|
||||
|
||||
gpio_set_value(usb_hub_reset, 0);
|
||||
gpio_set_value(GPIO9_USB_VBUS_EN, 1);
|
||||
|
||||
return 0;
|
||||
|
||||
err_free_rst_gpio:
|
||||
gpio_free(usb_hub_reset);
|
||||
err_free_vbus_gpio:
|
||||
gpio_free(GPIO9_USB_VBUS_EN);
|
||||
err_free_usb_ldo:
|
||||
|
@ -592,7 +600,7 @@ err_irq:
|
|||
return err;
|
||||
}
|
||||
|
||||
static void em_x270_mci_setpower(struct device *dev, unsigned int vdd)
|
||||
static int em_x270_mci_setpower(struct device *dev, unsigned int vdd)
|
||||
{
|
||||
struct pxamci_platform_data* p_d = dev->platform_data;
|
||||
|
||||
|
@ -600,10 +608,11 @@ static void em_x270_mci_setpower(struct device *dev, unsigned int vdd)
|
|||
int vdd_uV = (2000 + (vdd - __ffs(MMC_VDD_20_21)) * 100) * 1000;
|
||||
|
||||
regulator_set_voltage(em_x270_sdio_ldo, vdd_uV, vdd_uV);
|
||||
regulator_enable(em_x270_sdio_ldo);
|
||||
return regulator_enable(em_x270_sdio_ldo);
|
||||
} else {
|
||||
regulator_disable(em_x270_sdio_ldo);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void em_x270_mci_exit(struct device *dev, void *data)
|
||||
|
|
|
@ -408,7 +408,7 @@ static int mainstone_mci_init(struct device *dev, irq_handler_t mstone_detect_in
|
|||
return err;
|
||||
}
|
||||
|
||||
static void mainstone_mci_setpower(struct device *dev, unsigned int vdd)
|
||||
static int mainstone_mci_setpower(struct device *dev, unsigned int vdd)
|
||||
{
|
||||
struct pxamci_platform_data* p_d = dev->platform_data;
|
||||
|
||||
|
@ -420,6 +420,7 @@ static void mainstone_mci_setpower(struct device *dev, unsigned int vdd)
|
|||
printk(KERN_DEBUG "%s: off\n", __func__);
|
||||
MST_MSCWR1 &= ~MST_MSCWR1_MMC_ON;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mainstone_mci_exit(struct device *dev, void *data)
|
||||
|
|
|
@ -335,7 +335,7 @@ static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int,
|
|||
return err;
|
||||
}
|
||||
|
||||
static void pcm990_mci_setpower(struct device *dev, unsigned int vdd)
|
||||
static int pcm990_mci_setpower(struct device *dev, unsigned int vdd)
|
||||
{
|
||||
struct pxamci_platform_data *p_d = dev->platform_data;
|
||||
u8 val;
|
||||
|
@ -348,6 +348,7 @@ static void pcm990_mci_setpower(struct device *dev, unsigned int vdd)
|
|||
val &= ~PCM990_CTRL_MMC2PWR;
|
||||
|
||||
pcm990_cpld_writeb(PCM990_CTRL_MMC2PWR, PCM990_CTRL_REG5);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void pcm990_mci_exit(struct device *dev, void *data)
|
||||
|
|
|
@ -258,7 +258,7 @@ err_free_2:
|
|||
return err;
|
||||
}
|
||||
|
||||
static void poodle_mci_setpower(struct device *dev, unsigned int vdd)
|
||||
static int poodle_mci_setpower(struct device *dev, unsigned int vdd)
|
||||
{
|
||||
struct pxamci_platform_data* p_d = dev->platform_data;
|
||||
|
||||
|
@ -270,6 +270,8 @@ static void poodle_mci_setpower(struct device *dev, unsigned int vdd)
|
|||
gpio_set_value(POODLE_GPIO_SD_PWR1, 0);
|
||||
gpio_set_value(POODLE_GPIO_SD_PWR, 0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void poodle_mci_exit(struct device *dev, void *data)
|
||||
|
|
|
@ -598,7 +598,7 @@ static inline void spitz_spi_init(void) {}
|
|||
* NOTE: The card detect interrupt isn't debounced so we delay it by 250ms to
|
||||
* give the card a chance to fully insert/eject.
|
||||
*/
|
||||
static void spitz_mci_setpower(struct device *dev, unsigned int vdd)
|
||||
static int spitz_mci_setpower(struct device *dev, unsigned int vdd)
|
||||
{
|
||||
struct pxamci_platform_data* p_d = dev->platform_data;
|
||||
|
||||
|
@ -606,6 +606,8 @@ static void spitz_mci_setpower(struct device *dev, unsigned int vdd)
|
|||
spitz_card_pwr_ctrl(SCOOP_CPR_SD_3V, SCOOP_CPR_SD_3V);
|
||||
else
|
||||
spitz_card_pwr_ctrl(SCOOP_CPR_SD_3V, 0x0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct pxamci_platform_data spitz_mci_platform_data = {
|
||||
|
|
|
@ -734,9 +734,10 @@ static int stargate2_mci_init(struct device *dev,
|
|||
*
|
||||
* Very simple control. Either it is on or off and is controlled by
|
||||
* a gpio pin */
|
||||
static void stargate2_mci_setpower(struct device *dev, unsigned int vdd)
|
||||
static int stargate2_mci_setpower(struct device *dev, unsigned int vdd)
|
||||
{
|
||||
gpio_set_value(SG2_SD_POWER_ENABLE, !!vdd);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void stargate2_mci_exit(struct device *dev, void *data)
|
||||
|
|
|
@ -119,66 +119,101 @@ static struct clk init_clocks_off[] = {
|
|||
}
|
||||
};
|
||||
|
||||
static struct clk init_clocks[] = {
|
||||
{
|
||||
.name = "lcd",
|
||||
.parent = &clk_h,
|
||||
.enable = s3c2410_clkcon_enable,
|
||||
.ctrlbit = S3C2410_CLKCON_LCDC,
|
||||
}, {
|
||||
.name = "gpio",
|
||||
.parent = &clk_p,
|
||||
.enable = s3c2410_clkcon_enable,
|
||||
.ctrlbit = S3C2410_CLKCON_GPIO,
|
||||
}, {
|
||||
.name = "usb-host",
|
||||
.parent = &clk_h,
|
||||
.enable = s3c2410_clkcon_enable,
|
||||
.ctrlbit = S3C2410_CLKCON_USBH,
|
||||
}, {
|
||||
.name = "usb-device",
|
||||
.parent = &clk_h,
|
||||
.enable = s3c2410_clkcon_enable,
|
||||
.ctrlbit = S3C2410_CLKCON_USBD,
|
||||
}, {
|
||||
.name = "timers",
|
||||
.parent = &clk_p,
|
||||
.enable = s3c2410_clkcon_enable,
|
||||
.ctrlbit = S3C2410_CLKCON_PWMT,
|
||||
}, {
|
||||
.name = "uart",
|
||||
.devname = "s3c2410-uart.0",
|
||||
.parent = &clk_p,
|
||||
.enable = s3c2410_clkcon_enable,
|
||||
.ctrlbit = S3C2410_CLKCON_UART0,
|
||||
}, {
|
||||
.name = "uart",
|
||||
.devname = "s3c2410-uart.1",
|
||||
.parent = &clk_p,
|
||||
.enable = s3c2410_clkcon_enable,
|
||||
.ctrlbit = S3C2410_CLKCON_UART1,
|
||||
}, {
|
||||
.name = "uart",
|
||||
.devname = "s3c2410-uart.2",
|
||||
.parent = &clk_p,
|
||||
.enable = s3c2410_clkcon_enable,
|
||||
.ctrlbit = S3C2410_CLKCON_UART2,
|
||||
}, {
|
||||
.name = "rtc",
|
||||
.parent = &clk_p,
|
||||
.enable = s3c2410_clkcon_enable,
|
||||
.ctrlbit = S3C2410_CLKCON_RTC,
|
||||
}, {
|
||||
.name = "watchdog",
|
||||
.parent = &clk_p,
|
||||
.ctrlbit = 0,
|
||||
}, {
|
||||
.name = "usb-bus-host",
|
||||
.parent = &clk_usb_bus,
|
||||
}, {
|
||||
.name = "usb-bus-gadget",
|
||||
.parent = &clk_usb_bus,
|
||||
},
|
||||
static struct clk clk_lcd = {
|
||||
.name = "lcd",
|
||||
.parent = &clk_h,
|
||||
.enable = s3c2410_clkcon_enable,
|
||||
.ctrlbit = S3C2410_CLKCON_LCDC,
|
||||
};
|
||||
|
||||
static struct clk clk_gpio = {
|
||||
.name = "gpio",
|
||||
.parent = &clk_p,
|
||||
.enable = s3c2410_clkcon_enable,
|
||||
.ctrlbit = S3C2410_CLKCON_GPIO,
|
||||
};
|
||||
|
||||
static struct clk clk_usb_host = {
|
||||
.name = "usb-host",
|
||||
.parent = &clk_h,
|
||||
.enable = s3c2410_clkcon_enable,
|
||||
.ctrlbit = S3C2410_CLKCON_USBH,
|
||||
};
|
||||
|
||||
static struct clk clk_usb_device = {
|
||||
.name = "usb-device",
|
||||
.parent = &clk_h,
|
||||
.enable = s3c2410_clkcon_enable,
|
||||
.ctrlbit = S3C2410_CLKCON_USBD,
|
||||
};
|
||||
|
||||
static struct clk clk_timers = {
|
||||
.name = "timers",
|
||||
.parent = &clk_p,
|
||||
.enable = s3c2410_clkcon_enable,
|
||||
.ctrlbit = S3C2410_CLKCON_PWMT,
|
||||
};
|
||||
|
||||
struct clk s3c24xx_clk_uart0 = {
|
||||
.name = "uart",
|
||||
.devname = "s3c2410-uart.0",
|
||||
.parent = &clk_p,
|
||||
.enable = s3c2410_clkcon_enable,
|
||||
.ctrlbit = S3C2410_CLKCON_UART0,
|
||||
};
|
||||
|
||||
struct clk s3c24xx_clk_uart1 = {
|
||||
.name = "uart",
|
||||
.devname = "s3c2410-uart.1",
|
||||
.parent = &clk_p,
|
||||
.enable = s3c2410_clkcon_enable,
|
||||
.ctrlbit = S3C2410_CLKCON_UART1,
|
||||
};
|
||||
|
||||
struct clk s3c24xx_clk_uart2 = {
|
||||
.name = "uart",
|
||||
.devname = "s3c2410-uart.2",
|
||||
.parent = &clk_p,
|
||||
.enable = s3c2410_clkcon_enable,
|
||||
.ctrlbit = S3C2410_CLKCON_UART2,
|
||||
};
|
||||
|
||||
static struct clk clk_rtc = {
|
||||
.name = "rtc",
|
||||
.parent = &clk_p,
|
||||
.enable = s3c2410_clkcon_enable,
|
||||
.ctrlbit = S3C2410_CLKCON_RTC,
|
||||
};
|
||||
|
||||
static struct clk clk_watchdog = {
|
||||
.name = "watchdog",
|
||||
.parent = &clk_p,
|
||||
.ctrlbit = 0,
|
||||
};
|
||||
|
||||
static struct clk clk_usb_bus_host = {
|
||||
.name = "usb-bus-host",
|
||||
.parent = &clk_usb_bus,
|
||||
};
|
||||
|
||||
static struct clk clk_usb_bus_gadget = {
|
||||
.name = "usb-bus-gadget",
|
||||
.parent = &clk_usb_bus,
|
||||
};
|
||||
|
||||
static struct clk *init_clocks[] = {
|
||||
&clk_lcd,
|
||||
&clk_gpio,
|
||||
&clk_usb_host,
|
||||
&clk_usb_device,
|
||||
&clk_timers,
|
||||
&s3c24xx_clk_uart0,
|
||||
&s3c24xx_clk_uart1,
|
||||
&s3c24xx_clk_uart2,
|
||||
&clk_rtc,
|
||||
&clk_watchdog,
|
||||
&clk_usb_bus_host,
|
||||
&clk_usb_bus_gadget,
|
||||
};
|
||||
|
||||
/* s3c2410_baseclk_add()
|
||||
|
@ -195,7 +230,6 @@ int __init s3c2410_baseclk_add(void)
|
|||
{
|
||||
unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
|
||||
unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
|
||||
struct clk *clkp;
|
||||
struct clk *xtal;
|
||||
int ret;
|
||||
int ptr;
|
||||
|
@ -207,8 +241,9 @@ int __init s3c2410_baseclk_add(void)
|
|||
|
||||
/* register clocks from clock array */
|
||||
|
||||
clkp = init_clocks;
|
||||
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
|
||||
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++) {
|
||||
struct clk *clkp = init_clocks[ptr];
|
||||
|
||||
/* ensure that we note the clock state */
|
||||
|
||||
clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
|
||||
|
|
|
@ -166,6 +166,9 @@ static struct clk_lookup s3c2440_clk_lookup[] = {
|
|||
CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
|
||||
CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
|
||||
CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n),
|
||||
CLKDEV_INIT("s3c2440-uart.0", "uart", &s3c24xx_clk_uart0),
|
||||
CLKDEV_INIT("s3c2440-uart.1", "uart", &s3c24xx_clk_uart1),
|
||||
CLKDEV_INIT("s3c2440-uart.2", "uart", &s3c24xx_clk_uart2),
|
||||
CLKDEV_INIT("s3c2440-camif", "camera", &s3c2440_clk_cam_upll),
|
||||
};
|
||||
|
||||
|
|
|
@ -11,8 +11,9 @@ menuconfig ARCH_STI
|
|||
select HAVE_SMP
|
||||
select HAVE_ARM_SCU if SMP
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARM_ERRATA_720789
|
||||
select ARM_ERRATA_754322
|
||||
select ARM_ERRATA_764369
|
||||
select ARM_ERRATA_775420
|
||||
select PL310_ERRATA_753970 if CACHE_PL310
|
||||
select PL310_ERRATA_769419 if CACHE_PL310
|
||||
help
|
||||
|
|
|
@ -91,7 +91,7 @@ static void __init zynq_map_io(void)
|
|||
zynq_scu_map_io();
|
||||
}
|
||||
|
||||
static void zynq_system_reset(char mode, const char *cmd)
|
||||
static void zynq_system_reset(enum reboot_mode mode, const char *cmd)
|
||||
{
|
||||
zynq_slcr_system_reset();
|
||||
}
|
||||
|
|
|
@ -29,6 +29,13 @@ config PLAT_S5P
|
|||
help
|
||||
Base platform code for Samsung's S5P series SoC.
|
||||
|
||||
config SAMSUNG_PM
|
||||
bool
|
||||
depends on PM && (PLAT_S3C24XX || ARCH_S3C64XX || ARCH_S5P64X0 || S5P_PM)
|
||||
default y
|
||||
help
|
||||
Base platform power management code for samsung code
|
||||
|
||||
if PLAT_SAMSUNG
|
||||
|
||||
# boot configurations
|
||||
|
|
|
@ -51,7 +51,7 @@ obj-$(CONFIG_SAMSUNG_DMADEV) += dma-ops.o
|
|||
|
||||
# PM support
|
||||
|
||||
obj-$(CONFIG_PM) += pm.o
|
||||
obj-$(CONFIG_SAMSUNG_PM) += pm.o
|
||||
obj-$(CONFIG_SAMSUNG_PM_GPIO) += pm-gpio.o
|
||||
obj-$(CONFIG_SAMSUNG_PM_CHECK) += pm-check.o
|
||||
|
||||
|
|
|
@ -83,6 +83,11 @@ extern struct clk clk_ext;
|
|||
extern struct clksrc_clk clk_epllref;
|
||||
extern struct clksrc_clk clk_esysclk;
|
||||
|
||||
/* S3C24XX UART clocks */
|
||||
extern struct clk s3c24xx_clk_uart0;
|
||||
extern struct clk s3c24xx_clk_uart1;
|
||||
extern struct clk s3c24xx_clk_uart2;
|
||||
|
||||
/* S3C64XX specific clocks */
|
||||
extern struct clk clk_h2;
|
||||
extern struct clk clk_27m;
|
||||
|
|
|
@ -19,7 +19,7 @@
|
|||
|
||||
struct device;
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
#ifdef CONFIG_SAMSUNG_PM
|
||||
|
||||
extern __init int s3c_pm_init(void);
|
||||
extern __init int s3c64xx_pm_init(void);
|
||||
|
@ -58,8 +58,6 @@ extern unsigned char pm_uart_udivslot; /* true to save UART UDIVSLOT */
|
|||
|
||||
/* from sleep.S */
|
||||
|
||||
extern void s3c_cpu_resume(void);
|
||||
|
||||
extern int s3c2410_cpu_suspend(unsigned long);
|
||||
|
||||
/* sleep save info */
|
||||
|
@ -106,12 +104,14 @@ extern void s3c_pm_do_save(struct sleep_save *ptr, int count);
|
|||
extern void s3c_pm_do_restore(struct sleep_save *ptr, int count);
|
||||
extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count);
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
#ifdef CONFIG_SAMSUNG_PM
|
||||
extern int s3c_irq_wake(struct irq_data *data, unsigned int state);
|
||||
extern int s3c_irqext_wake(struct irq_data *data, unsigned int state);
|
||||
extern void s3c_cpu_resume(void);
|
||||
#else
|
||||
#define s3c_irq_wake NULL
|
||||
#define s3c_irqext_wake NULL
|
||||
#define s3c_cpu_resume NULL
|
||||
#endif
|
||||
|
||||
/* PM debug functions */
|
||||
|
|
|
@ -80,7 +80,7 @@ unsigned char pm_uart_udivslot;
|
|||
|
||||
#ifdef CONFIG_SAMSUNG_PM_DEBUG
|
||||
|
||||
static struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS];
|
||||
static struct pm_uart_save uart_save;
|
||||
|
||||
static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save)
|
||||
{
|
||||
|
@ -101,11 +101,7 @@ static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save)
|
|||
|
||||
static void s3c_pm_save_uarts(void)
|
||||
{
|
||||
struct pm_uart_save *save = uart_save;
|
||||
unsigned int uart;
|
||||
|
||||
for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++)
|
||||
s3c_pm_save_uart(uart, save);
|
||||
s3c_pm_save_uart(CONFIG_DEBUG_S3C_UART, &uart_save);
|
||||
}
|
||||
|
||||
static void s3c_pm_restore_uart(unsigned int uart, struct pm_uart_save *save)
|
||||
|
@ -126,11 +122,7 @@ static void s3c_pm_restore_uart(unsigned int uart, struct pm_uart_save *save)
|
|||
|
||||
static void s3c_pm_restore_uarts(void)
|
||||
{
|
||||
struct pm_uart_save *save = uart_save;
|
||||
unsigned int uart;
|
||||
|
||||
for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++)
|
||||
s3c_pm_restore_uart(uart, save);
|
||||
s3c_pm_restore_uart(CONFIG_DEBUG_S3C_UART, &uart_save);
|
||||
}
|
||||
#else
|
||||
static void s3c_pm_save_uarts(void) { }
|
||||
|
|
|
@ -128,7 +128,7 @@ static inline int pxamci_set_power(struct pxamci_host *host,
|
|||
!!on ^ host->pdata->gpio_power_invert);
|
||||
}
|
||||
if (!host->vcc && host->pdata && host->pdata->setpower)
|
||||
host->pdata->setpower(mmc_dev(host->mmc), vdd);
|
||||
return host->pdata->setpower(mmc_dev(host->mmc), vdd);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -101,33 +101,37 @@ static const struct backlight_ops max8925_backlight_ops = {
|
|||
.get_brightness = max8925_backlight_get_brightness,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
static int max8925_backlight_dt_init(struct platform_device *pdev,
|
||||
struct max8925_backlight_pdata *pdata)
|
||||
static void max8925_backlight_dt_init(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *nproot = pdev->dev.parent->of_node, *np;
|
||||
int dual_string;
|
||||
struct max8925_backlight_pdata *pdata;
|
||||
u32 val;
|
||||
|
||||
if (!nproot || !IS_ENABLED(CONFIG_OF))
|
||||
return;
|
||||
|
||||
pdata = devm_kzalloc(&pdev->dev,
|
||||
sizeof(struct max8925_backlight_pdata),
|
||||
GFP_KERNEL);
|
||||
if (!pdata)
|
||||
return;
|
||||
|
||||
if (!nproot)
|
||||
return -ENODEV;
|
||||
np = of_find_node_by_name(nproot, "backlight");
|
||||
if (!np) {
|
||||
dev_err(&pdev->dev, "failed to find backlight node\n");
|
||||
return -ENODEV;
|
||||
return;
|
||||
}
|
||||
|
||||
of_property_read_u32(np, "maxim,max8925-dual-string", &dual_string);
|
||||
pdata->dual_string = dual_string;
|
||||
return 0;
|
||||
if (!of_property_read_u32(np, "maxim,max8925-dual-string", &val))
|
||||
pdata->dual_string = val;
|
||||
|
||||
pdev->dev.platform_data = pdata;
|
||||
}
|
||||
#else
|
||||
#define max8925_backlight_dt_init(x, y) (-1)
|
||||
#endif
|
||||
|
||||
static int max8925_backlight_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct max8925_chip *chip = dev_get_drvdata(pdev->dev.parent);
|
||||
struct max8925_backlight_pdata *pdata = pdev->dev.platform_data;
|
||||
struct max8925_backlight_pdata *pdata;
|
||||
struct max8925_backlight_data *data;
|
||||
struct backlight_device *bl;
|
||||
struct backlight_properties props;
|
||||
|
@ -170,13 +174,10 @@ static int max8925_backlight_probe(struct platform_device *pdev)
|
|||
platform_set_drvdata(pdev, bl);
|
||||
|
||||
value = 0;
|
||||
if (pdev->dev.parent->of_node && !pdata) {
|
||||
pdata = devm_kzalloc(&pdev->dev,
|
||||
sizeof(struct max8925_backlight_pdata),
|
||||
GFP_KERNEL);
|
||||
max8925_backlight_dt_init(pdev, pdata);
|
||||
}
|
||||
if (!pdev->dev.platform_data)
|
||||
max8925_backlight_dt_init(pdev);
|
||||
|
||||
pdata = pdev->dev.platform_data;
|
||||
if (pdata) {
|
||||
if (pdata->lxw_scl)
|
||||
value |= (1 << 7);
|
||||
|
|
|
@ -158,6 +158,8 @@
|
|||
#define VF610_CLK_GPU_SEL 145
|
||||
#define VF610_CLK_GPU_EN 146
|
||||
#define VF610_CLK_GPU2D 147
|
||||
#define VF610_CLK_END 148
|
||||
#define VF610_CLK_ENET0 148
|
||||
#define VF610_CLK_ENET1 149
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||||
#define VF610_CLK_END 150
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_VF610_H */
|
||||
|
|
|
@ -103,15 +103,15 @@
|
|||
#define IMX6Q_GPR1_EXC_MON_MASK BIT(22)
|
||||
#define IMX6Q_GPR1_EXC_MON_OKAY 0x0
|
||||
#define IMX6Q_GPR1_EXC_MON_SLVE BIT(22)
|
||||
#define IMX6Q_GPR1_MIPI_IPU2_SEL_MASK BIT(21)
|
||||
#define IMX6Q_GPR1_MIPI_IPU2_SEL_GASKET 0x0
|
||||
#define IMX6Q_GPR1_MIPI_IPU2_SEL_IOMUX BIT(21)
|
||||
#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK BIT(20)
|
||||
#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET 0x0
|
||||
#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX BIT(20)
|
||||
#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK BIT(19)
|
||||
#define IMX6Q_GPR1_ENET_CLK_SEL_MASK BIT(21)
|
||||
#define IMX6Q_GPR1_ENET_CLK_SEL_PAD 0
|
||||
#define IMX6Q_GPR1_ENET_CLK_SEL_ANATOP BIT(21)
|
||||
#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK BIT(20)
|
||||
#define IMX6Q_GPR1_MIPI_IPU2_MUX_GASKET 0x0
|
||||
#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX BIT(19)
|
||||
#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20)
|
||||
#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK BIT(19)
|
||||
#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET 0x0
|
||||
#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19)
|
||||
#define IMX6Q_GPR1_PCIE_TEST_PD BIT(18)
|
||||
#define IMX6Q_GPR1_IPU_VPU_MUX_MASK BIT(17)
|
||||
#define IMX6Q_GPR1_IPU_VPU_MUX_IPU1 0x0
|
||||
|
|
|
@ -12,7 +12,7 @@ struct pxamci_platform_data {
|
|||
unsigned long detect_delay_ms; /* delay in millisecond before detecting cards after interrupt */
|
||||
int (*init)(struct device *, irq_handler_t , void *);
|
||||
int (*get_ro)(struct device *);
|
||||
void (*setpower)(struct device *, unsigned int);
|
||||
int (*setpower)(struct device *, unsigned int);
|
||||
void (*exit)(struct device *, void *);
|
||||
int gpio_card_detect; /* gpio detecting card insertion */
|
||||
int gpio_card_ro; /* gpio detecting read only toggle */
|
||||
|
|
|
@ -124,6 +124,10 @@ void shdma_chan_remove(struct shdma_chan *schan);
|
|||
int shdma_init(struct device *dev, struct shdma_dev *sdev,
|
||||
int chan_num);
|
||||
void shdma_cleanup(struct shdma_dev *sdev);
|
||||
#if IS_ENABLED(CONFIG_SH_DMAE_BASE)
|
||||
bool shdma_chan_filter(struct dma_chan *chan, void *arg);
|
||||
#else
|
||||
#define shdma_chan_filter NULL
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
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