mmc: sdhci-msm: Add HS400 platform support
The following msm platform specific changes are added to support HS400. - Allow tuning for HS400 mode. - Configure HS400 timing mode using the VENDOR_SPECIFIC_FUNC register. Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org> Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Venkat Gopalakrishnan
Ulf Hansson
Родитель
b12d44db4b
Коммит
ff06ce4178
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@ -32,6 +32,7 @@
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#define HC_MODE_EN 0x1
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#define CORE_POWER 0x0
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#define CORE_SW_RST BIT(7)
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#define FF_CLK_SW_RST_DIS BIT(13)
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#define CORE_PWRCTL_STATUS 0xdc
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#define CORE_PWRCTL_MASK 0xe0
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@ -65,10 +66,17 @@
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#define CORE_VENDOR_SPEC 0x10c
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#define CORE_CLK_PWRSAVE BIT(1)
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#define CORE_HC_MCLK_SEL_DFLT (2 << 8)
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#define CORE_HC_MCLK_SEL_HS400 (3 << 8)
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#define CORE_HC_MCLK_SEL_MASK (3 << 8)
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#define CORE_HC_SELECT_IN_EN BIT(18)
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#define CORE_HC_SELECT_IN_HS400 (6 << 19)
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#define CORE_HC_SELECT_IN_MASK (7 << 19)
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#define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c
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#define SDHCI_MSM_MIN_CLOCK 400000
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#define CORE_FREQ_100MHZ (100 * 1000 * 1000)
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#define CDR_SELEXT_SHIFT 20
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#define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT)
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@ -87,6 +95,8 @@ struct sdhci_msm_host {
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unsigned long clk_rate;
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struct mmc_host *mmc;
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bool use_14lpp_dll_reset;
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bool tuning_done;
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bool calibration_done;
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};
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/* Platform specific tuning */
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@ -174,8 +184,8 @@ out:
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* Find out the greatest range of consecuitive selected
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* DLL clock output phases that can be used as sampling
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* setting for SD3.0 UHS-I card read operation (in SDR104
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* timing mode) or for eMMC4.5 card read operation (in HS200
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* timing mode).
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* timing mode) or for eMMC4.5 card read operation (in
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* HS400/HS200 timing mode).
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* Select the 3/4 of the range and configure the DLL with the
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* selected DLL clock output phase.
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*/
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@ -424,9 +434,10 @@ static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
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* Tuning is required for SDR104, HS200 and HS400 cards and
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* if clock frequency is greater than 100MHz in these modes.
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*/
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if (host->clock <= 100 * 1000 * 1000 ||
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!((ios.timing == MMC_TIMING_MMC_HS200) ||
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(ios.timing == MMC_TIMING_UHS_SDR104)))
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if (host->clock <= CORE_FREQ_100MHZ ||
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!(ios.timing == MMC_TIMING_MMC_HS400 ||
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ios.timing == MMC_TIMING_MMC_HS200 ||
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ios.timing == MMC_TIMING_UHS_SDR104))
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return 0;
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retry:
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@ -477,6 +488,8 @@ retry:
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rc = -EIO;
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}
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if (!rc)
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msm_host->tuning_done = true;
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return rc;
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}
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@ -484,7 +497,10 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
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unsigned int uhs)
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{
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struct mmc_host *mmc = host->mmc;
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
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u16 ctrl_2;
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u32 config;
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ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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/* Select Bus Speed Mode for host */
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@ -499,6 +515,7 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
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case MMC_TIMING_UHS_SDR50:
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ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
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break;
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case MMC_TIMING_MMC_HS400:
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case MMC_TIMING_MMC_HS200:
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case MMC_TIMING_UHS_SDR104:
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ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
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@ -515,11 +532,29 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
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* provide feedback clock, the mode selection can be any value less
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* than 3'b011 in bits [2:0] of HOST CONTROL2 register.
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*/
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if (host->clock <= 100000000 &&
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(uhs == MMC_TIMING_MMC_HS400 ||
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uhs == MMC_TIMING_MMC_HS200 ||
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uhs == MMC_TIMING_UHS_SDR104))
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ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
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if (host->clock <= CORE_FREQ_100MHZ) {
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if (uhs == MMC_TIMING_MMC_HS400 ||
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uhs == MMC_TIMING_MMC_HS200 ||
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uhs == MMC_TIMING_UHS_SDR104)
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ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
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/*
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* DLL is not required for clock <= 100MHz
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* Thus, make sure DLL it is disabled when not required
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*/
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config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
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config |= CORE_DLL_RST;
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writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
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config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
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config |= CORE_DLL_PDN;
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writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
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/*
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* The DLL needs to be restored and CDCLP533 recalibrated
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* when the clock frequency is set back to 400MHz.
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*/
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msm_host->calibration_done = false;
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}
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dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
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mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
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@ -611,6 +646,7 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
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struct mmc_ios curr_ios = host->mmc->ios;
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u32 config;
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int rc;
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if (!clock) {
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@ -629,6 +665,68 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
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curr_ios.timing == MMC_TIMING_MMC_DDR52 ||
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curr_ios.timing == MMC_TIMING_MMC_HS400)
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clock *= 2;
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/*
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* In general all timing modes are controlled via UHS mode select in
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* Host Control2 register. eMMC specific HS200/HS400 doesn't have
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* their respective modes defined here, hence we use these values.
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*
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* HS200 - SDR104 (Since they both are equivalent in functionality)
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* HS400 - This involves multiple configurations
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* Initially SDR104 - when tuning is required as HS200
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* Then when switching to DDR @ 400MHz (HS400) we use
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* the vendor specific HC_SELECT_IN to control the mode.
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*
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* In addition to controlling the modes we also need to select the
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* correct input clock for DLL depending on the mode.
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*
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* HS400 - divided clock (free running MCLK/2)
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* All other modes - default (free running MCLK)
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*/
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if (curr_ios.timing == MMC_TIMING_MMC_HS400) {
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/* Select the divided clock (free running MCLK/2) */
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config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
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config &= ~CORE_HC_MCLK_SEL_MASK;
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config |= CORE_HC_MCLK_SEL_HS400;
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writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
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/*
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* Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
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* register
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*/
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if (msm_host->tuning_done && !msm_host->calibration_done) {
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/*
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* Write 0x6 to HC_SELECT_IN and 1 to HC_SELECT_IN_EN
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* field in VENDOR_SPEC_FUNC
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*/
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config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
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config |= CORE_HC_SELECT_IN_HS400;
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config |= CORE_HC_SELECT_IN_EN;
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writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
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}
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} else {
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config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
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config &= ~CORE_HC_MCLK_SEL_MASK;
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config |= CORE_HC_MCLK_SEL_DFLT;
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writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
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/*
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* Disable HC_SELECT_IN to be able to use the UHS mode select
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* configuration from Host Control2 register for all other
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* modes.
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* Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
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* in VENDOR_SPEC_FUNC
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*/
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config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
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config &= ~CORE_HC_SELECT_IN_EN;
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config &= ~CORE_HC_SELECT_IN_MASK;
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writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
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}
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/*
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* Make sure above writes impacting free running MCLK are completed
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* before changing the clk_rate at GCC.
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*/
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wmb();
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rc = clk_set_rate(msm_host->clk, clock);
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if (rc) {
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@ -776,6 +874,10 @@ static int sdhci_msm_probe(struct platform_device *pdev)
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/* Set HC_MODE_EN bit in HC_MODE register */
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writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE));
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config = readl_relaxed(msm_host->core_mem + CORE_HC_MODE);
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config |= FF_CLK_SW_RST_DIS;
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writel_relaxed(config, msm_host->core_mem + CORE_HC_MODE);
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host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
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dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
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host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
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