arm64: dts: qcom: msm8996-*: Clean up QUP and UART names
QUP and UART names start from 1. There are 6 QUPs and 2 UARTs per BLSP. Let's not further confuse programmers by stating otherwise. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210228130831.203765-2-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Konrad Dybcio
Bjorn Andersson
Родитель
35a4a8b6e9
Коммит
ff5e2b87a1
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@ -41,14 +41,14 @@
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/ {
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aliases {
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serial0 = &blsp2_uart1;
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serial1 = &blsp2_uart2;
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serial2 = &blsp1_uart1;
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i2c0 = &blsp1_i2c2;
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serial0 = &blsp2_uart2;
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serial1 = &blsp2_uart3;
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serial2 = &blsp1_uart2;
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i2c0 = &blsp1_i2c3;
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i2c1 = &blsp2_i2c1;
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i2c2 = &blsp2_i2c0;
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spi0 = &blsp1_spi0;
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spi1 = &blsp2_spi5;
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i2c2 = &blsp2_i2c1;
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spi0 = &blsp1_spi1;
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spi1 = &blsp2_spi6;
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};
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chosen {
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@ -133,24 +133,24 @@
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};
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};
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&blsp1_i2c2 {
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&blsp1_i2c3 {
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/* On Low speed expansion */
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label = "LS-I2C0";
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status = "okay";
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};
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&blsp1_spi0 {
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&blsp1_spi1 {
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/* On Low speed expansion */
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label = "LS-SPI0";
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status = "okay";
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};
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&blsp1_uart1 {
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&blsp1_uart2 {
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label = "BT-UART";
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status = "okay";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&blsp1_uart1_default>;
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pinctrl-1 = <&blsp1_uart1_sleep>;
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pinctrl-0 = <&blsp1_uart2_default>;
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pinctrl-1 = <&blsp1_uart2_sleep>;
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bluetooth {
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compatible = "qcom,qca6174-bt";
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@ -166,7 +166,7 @@
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status = "okay";
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};
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&blsp2_i2c0 {
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&blsp2_i2c1 {
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/* On High speed expansion */
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label = "HS-I2C2";
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status = "okay";
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@ -178,13 +178,13 @@
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status = "okay";
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};
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&blsp2_spi5 {
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&blsp2_spi6 {
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/* On High speed expansion */
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label = "HS-SPI1";
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status = "okay";
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};
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&blsp2_uart1 {
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&blsp2_uart2 {
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label = "LS-UART1";
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status = "okay";
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pinctrl-names = "default", "sleep";
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@ -192,7 +192,7 @@
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pinctrl-1 = <&blsp2_uart2_2pins_sleep>;
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};
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&blsp2_uart2 {
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&blsp2_uart3 {
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label = "LS-UART0";
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status = "disabled";
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pinctrl-names = "default", "sleep";
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@ -428,7 +428,7 @@
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};
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};
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blsp1_uart1_default: blsp1_uart1_default {
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blsp1_uart2_default: blsp1_uart2_default {
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mux {
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pins = "gpio41", "gpio42", "gpio43", "gpio44";
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function = "blsp_uart2";
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@ -441,7 +441,7 @@
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};
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};
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blsp1_uart1_sleep: blsp1_uart1_sleep {
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blsp1_uart2_sleep: blsp1_uart2_sleep {
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mux {
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pins = "gpio41", "gpio42", "gpio43", "gpio44";
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function = "gpio";
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@ -17,7 +17,7 @@
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qcom,board-id = <0x00010018 0>;
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aliases {
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serial0 = &blsp2_uart1;
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serial0 = &blsp2_uart2;
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};
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chosen {
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@ -81,7 +81,7 @@
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};
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};
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&blsp2_uart1 {
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&blsp2_uart2 {
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status = "okay";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&blsp2_uart2_2pins_default>;
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@ -7,7 +7,7 @@
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/ {
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aliases {
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serial0 = &blsp2_uart1;
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serial0 = &blsp2_uart2;
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};
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chosen {
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@ -2326,7 +2326,7 @@
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bus-width = <4>;
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};
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blsp1_uart1: serial@7570000 {
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blsp1_uart2: serial@7570000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x07570000 0x1000>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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@ -2336,7 +2336,7 @@
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status = "disabled";
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};
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blsp1_spi0: spi@7575000 {
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blsp1_spi1: spi@7575000 {
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compatible = "qcom,spi-qup-v2.2.1";
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reg = <0x07575000 0x600>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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@ -2351,7 +2351,7 @@
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status = "disabled";
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};
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blsp1_i2c2: i2c@7577000 {
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blsp1_i2c3: i2c@7577000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x07577000 0x1000>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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@ -2366,7 +2366,7 @@
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status = "disabled";
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};
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blsp2_uart1: serial@75b0000 {
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blsp2_uart2: serial@75b0000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x075b0000 0x1000>;
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interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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@ -2376,7 +2376,7 @@
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status = "disabled";
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};
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blsp2_uart2: serial@75b1000 {
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blsp2_uart3: serial@75b1000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x075b1000 0x1000>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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@ -2386,7 +2386,7 @@
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status = "disabled";
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};
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blsp2_i2c0: i2c@75b5000 {
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blsp2_i2c1: i2c@75b5000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x075b5000 0x1000>;
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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@ -2401,7 +2401,7 @@
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status = "disabled";
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};
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blsp2_i2c1: i2c@75b6000 {
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blsp2_i2c2: i2c@75b6000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x075b6000 0x1000>;
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interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
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@ -2416,7 +2416,7 @@
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status = "disabled";
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};
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blsp2_spi5: spi@75ba000{
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blsp2_spi6: spi@75ba000{
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compatible = "qcom,spi-qup-v2.2.1";
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reg = <0x075ba000 0x600>;
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interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
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