Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: drm/i915: select framebuffer support automatically drm/i915: add get_vblank_counter function for GM45 drm/i915: capture last_vblank count at IRQ uninstall time too drm/i915: Unlock mutex on i915_gem_fault() error path drm/i915: Quiet the message on get/setparam ioctl with an unknown value. drm/i915: skip LVDS initialization on Apple Mac Mini drm/i915: sync SDVO code with stable userland modesetting driver drm/i915: Unref the object after failing to set tiling mode. drm/i915: add fence register management to execbuf drm/i915: Return error from i915_gem_object_get_fence_reg() when failing. drm/i915: Set up an MTRR covering the GTT at driver load. drm/i915: Skip SDVO/HDMI init when the chipset tells us it's not present. drm/i915: Suppress GEM teardown on X Server exit in KMS mode. drm/radeon: fix ioremap conflict with AGP mappings i915: fix unneeded locking in i915 LVDS get modes code.
This commit is contained in:
Linus Torvalds
Коммит
ff7473300d
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@ -70,7 +70,7 @@ config DRM_I915
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select FB_CFB_FILLRECT
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select FB_CFB_COPYAREA
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select FB_CFB_IMAGEBLIT
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depends on FB
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select FB
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tristate "i915 driver"
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help
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Choose this option if you have a system that has Intel 830M, 845G,
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@ -276,6 +276,7 @@ int drm_irq_uninstall(struct drm_device * dev)
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for (i = 0; i < dev->num_crtcs; i++) {
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DRM_WAKEUP(&dev->vbl_queue[i]);
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dev->vblank_enabled[i] = 0;
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dev->last_vblank[i] = dev->driver->get_vblank_counter(dev, i);
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}
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spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
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@ -171,9 +171,14 @@ EXPORT_SYMBOL(drm_core_ioremap);
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void drm_core_ioremap_wc(struct drm_map *map, struct drm_device *dev)
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{
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map->handle = ioremap_wc(map->offset, map->size);
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if (drm_core_has_AGP(dev) &&
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dev->agp && dev->agp->cant_use_aperture && map->type == _DRM_AGP)
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map->handle = agp_remap(map->offset, map->size, dev);
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else
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map->handle = ioremap_wc(map->offset, map->size);
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}
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EXPORT_SYMBOL(drm_core_ioremap_wc);
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void drm_core_ioremapfree(struct drm_map *map, struct drm_device *dev)
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{
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if (!map->handle || !map->size)
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@ -731,8 +731,11 @@ static int i915_getparam(struct drm_device *dev, void *data,
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case I915_PARAM_HAS_GEM:
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value = dev_priv->has_gem;
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break;
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case I915_PARAM_NUM_FENCES_AVAIL:
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value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
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break;
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default:
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DRM_ERROR("Unknown parameter %d\n", param->param);
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DRM_DEBUG("Unknown parameter %d\n", param->param);
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return -EINVAL;
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}
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@ -764,8 +767,15 @@ static int i915_setparam(struct drm_device *dev, void *data,
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case I915_SETPARAM_ALLOW_BATCHBUFFER:
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dev_priv->allow_batchbuffer = param->value;
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break;
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case I915_SETPARAM_NUM_USED_FENCES:
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if (param->value > dev_priv->num_fence_regs ||
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param->value < 0)
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return -EINVAL;
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/* Userspace can use first N regs */
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dev_priv->fence_reg_start = param->value;
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break;
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default:
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DRM_ERROR("unknown parameter %d\n", param->param);
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DRM_DEBUG("unknown parameter %d\n", param->param);
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return -EINVAL;
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}
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@ -966,10 +976,6 @@ static int i915_load_modeset_init(struct drm_device *dev)
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if (ret)
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goto kfree_devname;
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dev_priv->mm.gtt_mapping =
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io_mapping_create_wc(dev->agp->base,
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dev->agp->agp_info.aper_size * 1024*1024);
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/* Allow hardware batchbuffers unless told otherwise.
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*/
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dev_priv->allow_batchbuffer = 1;
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@ -1081,6 +1087,23 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
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goto free_priv;
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}
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dev_priv->mm.gtt_mapping =
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io_mapping_create_wc(dev->agp->base,
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dev->agp->agp_info.aper_size * 1024*1024);
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/* Set up a WC MTRR for non-PAT systems. This is more common than
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* one would think, because the kernel disables PAT on first
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* generation Core chips because WC PAT gets overridden by a UC
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* MTRR if present. Even if a UC MTRR isn't present.
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*/
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dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
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dev->agp->agp_info.aper_size *
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1024 * 1024,
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MTRR_TYPE_WRCOMB, 1);
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if (dev_priv->mm.gtt_mtrr < 0) {
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DRM_INFO("MTRR allocation failed\n. Graphics "
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"performance may suffer.\n");
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}
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#ifdef CONFIG_HIGHMEM64G
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/* don't enable GEM on PAE - needs agp + set_memory_* interface fixes */
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dev_priv->has_gem = 0;
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@ -1089,6 +1112,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
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dev_priv->has_gem = 1;
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#endif
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dev->driver->get_vblank_counter = i915_get_vblank_counter;
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if (IS_GM45(dev))
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dev->driver->get_vblank_counter = gm45_get_vblank_counter;
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i915_gem_load(dev);
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/* Init HWS */
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@ -1145,8 +1172,14 @@ int i915_driver_unload(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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io_mapping_free(dev_priv->mm.gtt_mapping);
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if (dev_priv->mm.gtt_mtrr >= 0) {
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mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
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dev->agp->agp_info.aper_size * 1024 * 1024);
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dev_priv->mm.gtt_mtrr = -1;
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}
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if (drm_core_check_feature(dev, DRIVER_MODESET)) {
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io_mapping_free(dev_priv->mm.gtt_mapping);
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drm_irq_uninstall(dev);
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}
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@ -112,7 +112,6 @@ static struct drm_driver driver = {
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.suspend = i915_suspend,
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.resume = i915_resume,
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.device_is_agp = i915_driver_device_is_agp,
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.get_vblank_counter = i915_get_vblank_counter,
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.enable_vblank = i915_enable_vblank,
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.disable_vblank = i915_disable_vblank,
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.irq_preinstall = i915_driver_irq_preinstall,
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@ -284,6 +284,7 @@ typedef struct drm_i915_private {
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struct drm_mm gtt_space;
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struct io_mapping *gtt_mapping;
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int gtt_mtrr;
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/**
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* List of objects currently involved in rendering from the
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@ -534,6 +535,7 @@ extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
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extern int i915_enable_vblank(struct drm_device *dev, int crtc);
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extern void i915_disable_vblank(struct drm_device *dev, int crtc);
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extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
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extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
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extern int i915_vblank_swap(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
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@ -601,6 +603,7 @@ int i915_gem_init_object(struct drm_gem_object *obj);
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void i915_gem_free_object(struct drm_gem_object *obj);
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int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
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void i915_gem_object_unpin(struct drm_gem_object *obj);
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int i915_gem_object_unbind(struct drm_gem_object *obj);
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void i915_gem_lastclose(struct drm_device *dev);
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uint32_t i915_get_gem_seqno(struct drm_device *dev);
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void i915_gem_retire_requests(struct drm_device *dev);
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@ -784,6 +787,11 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
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IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev))
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#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev))
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/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
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* rows, which changed the alignment requirements and fence programming.
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*/
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#define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
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IS_I915GM(dev)))
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#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev))
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#define PRIMARY_RINGBUFFER_SIZE (128*1024)
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@ -52,7 +52,7 @@ static void i915_gem_object_free_page_list(struct drm_gem_object *obj);
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static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
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static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
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unsigned alignment);
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static void i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
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static int i915_gem_object_get_fence_reg(struct drm_gem_object *obj, bool write);
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static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
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static int i915_gem_evict_something(struct drm_device *dev);
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static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
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@ -567,6 +567,7 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
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pgoff_t page_offset;
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unsigned long pfn;
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int ret = 0;
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bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
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/* We don't use vmf->pgoff since that has the fake offset */
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page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
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@ -585,8 +586,13 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
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/* Need a new fence register? */
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if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
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obj_priv->tiling_mode != I915_TILING_NONE)
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i915_gem_object_get_fence_reg(obj);
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obj_priv->tiling_mode != I915_TILING_NONE) {
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ret = i915_gem_object_get_fence_reg(obj, write);
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if (ret) {
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mutex_unlock(&dev->struct_mutex);
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return VM_FAULT_SIGBUS;
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}
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}
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pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
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page_offset;
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@ -1211,7 +1217,7 @@ i915_gem_object_wait_rendering(struct drm_gem_object *obj)
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/**
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* Unbinds an object from the GTT aperture.
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*/
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static int
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int
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i915_gem_object_unbind(struct drm_gem_object *obj)
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{
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struct drm_device *dev = obj->dev;
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@ -1445,21 +1451,26 @@ static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_i915_gem_object *obj_priv = obj->driver_private;
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int regnum = obj_priv->fence_reg;
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int tile_width;
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uint32_t val;
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uint32_t pitch_val;
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if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
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(obj_priv->gtt_offset & (obj->size - 1))) {
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WARN(1, "%s: object not 1M or size aligned\n", __func__);
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WARN(1, "%s: object 0x%08x not 1M or size (0x%x) aligned\n",
|
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__func__, obj_priv->gtt_offset, obj->size);
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||||
return;
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||||
}
|
||||
|
||||
if (obj_priv->tiling_mode == I915_TILING_Y && (IS_I945G(dev) ||
|
||||
IS_I945GM(dev) ||
|
||||
IS_G33(dev)))
|
||||
pitch_val = (obj_priv->stride / 128) - 1;
|
||||
if (obj_priv->tiling_mode == I915_TILING_Y &&
|
||||
HAS_128_BYTE_Y_TILING(dev))
|
||||
tile_width = 128;
|
||||
else
|
||||
pitch_val = (obj_priv->stride / 512) - 1;
|
||||
tile_width = 512;
|
||||
|
||||
/* Note: pitch better be a power of two tile widths */
|
||||
pitch_val = obj_priv->stride / tile_width;
|
||||
pitch_val = ffs(pitch_val) - 1;
|
||||
|
||||
val = obj_priv->gtt_offset;
|
||||
if (obj_priv->tiling_mode == I915_TILING_Y)
|
||||
|
|
@ -1483,7 +1494,8 @@ static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
|
|||
|
||||
if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
|
||||
(obj_priv->gtt_offset & (obj->size - 1))) {
|
||||
WARN(1, "%s: object not 1M or size aligned\n", __func__);
|
||||
WARN(1, "%s: object 0x%08x not 1M or size aligned\n",
|
||||
__func__, obj_priv->gtt_offset);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -1503,6 +1515,7 @@ static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
|
|||
/**
|
||||
* i915_gem_object_get_fence_reg - set up a fence reg for an object
|
||||
* @obj: object to map through a fence reg
|
||||
* @write: object is about to be written
|
||||
*
|
||||
* When mapping objects through the GTT, userspace wants to be able to write
|
||||
* to them without having to worry about swizzling if the object is tiled.
|
||||
|
|
@ -1513,8 +1526,8 @@ static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
|
|||
* It then sets up the reg based on the object's properties: address, pitch
|
||||
* and tiling format.
|
||||
*/
|
||||
static void
|
||||
i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
|
||||
static int
|
||||
i915_gem_object_get_fence_reg(struct drm_gem_object *obj, bool write)
|
||||
{
|
||||
struct drm_device *dev = obj->dev;
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
|
|
@ -1527,12 +1540,18 @@ i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
|
|||
WARN(1, "allocating a fence for non-tiled object?\n");
|
||||
break;
|
||||
case I915_TILING_X:
|
||||
WARN(obj_priv->stride & (512 - 1),
|
||||
"object is X tiled but has non-512B pitch\n");
|
||||
if (!obj_priv->stride)
|
||||
return -EINVAL;
|
||||
WARN((obj_priv->stride & (512 - 1)),
|
||||
"object 0x%08x is X tiled but has non-512B pitch\n",
|
||||
obj_priv->gtt_offset);
|
||||
break;
|
||||
case I915_TILING_Y:
|
||||
WARN(obj_priv->stride & (128 - 1),
|
||||
"object is Y tiled but has non-128B pitch\n");
|
||||
if (!obj_priv->stride)
|
||||
return -EINVAL;
|
||||
WARN((obj_priv->stride & (128 - 1)),
|
||||
"object 0x%08x is Y tiled but has non-128B pitch\n",
|
||||
obj_priv->gtt_offset);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -1563,10 +1582,11 @@ try_again:
|
|||
* objects to finish before trying again.
|
||||
*/
|
||||
if (i == dev_priv->num_fence_regs) {
|
||||
ret = i915_gem_object_wait_rendering(reg->obj);
|
||||
ret = i915_gem_object_set_to_gtt_domain(reg->obj, 0);
|
||||
if (ret) {
|
||||
WARN(ret, "wait_rendering failed: %d\n", ret);
|
||||
return;
|
||||
WARN(ret != -ERESTARTSYS,
|
||||
"switch to GTT domain failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
goto try_again;
|
||||
}
|
||||
|
|
@ -1591,6 +1611,8 @@ try_again:
|
|||
i915_write_fence_reg(reg);
|
||||
else
|
||||
i830_write_fence_reg(reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -1631,7 +1653,7 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
|
|||
if (dev_priv->mm.suspended)
|
||||
return -EBUSY;
|
||||
if (alignment == 0)
|
||||
alignment = PAGE_SIZE;
|
||||
alignment = i915_gem_get_gtt_alignment(obj);
|
||||
if (alignment & (PAGE_SIZE - 1)) {
|
||||
DRM_ERROR("Invalid object alignment requested %u\n", alignment);
|
||||
return -EINVAL;
|
||||
|
|
@ -2652,6 +2674,14 @@ i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
|
|||
DRM_ERROR("Failure to bind: %d", ret);
|
||||
return ret;
|
||||
}
|
||||
/*
|
||||
* Pre-965 chips need a fence register set up in order to
|
||||
* properly handle tiled surfaces.
|
||||
*/
|
||||
if (!IS_I965G(dev) &&
|
||||
obj_priv->fence_reg == I915_FENCE_REG_NONE &&
|
||||
obj_priv->tiling_mode != I915_TILING_NONE)
|
||||
i915_gem_object_get_fence_reg(obj, true);
|
||||
}
|
||||
obj_priv->pin_count++;
|
||||
|
||||
|
|
@ -3229,10 +3259,6 @@ i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
|
|||
dev_priv->mm.wedged = 0;
|
||||
}
|
||||
|
||||
dev_priv->mm.gtt_mapping = io_mapping_create_wc(dev->agp->base,
|
||||
dev->agp->agp_info.aper_size
|
||||
* 1024 * 1024);
|
||||
|
||||
mutex_lock(&dev->struct_mutex);
|
||||
dev_priv->mm.suspended = 0;
|
||||
|
||||
|
|
@ -3255,7 +3281,6 @@ int
|
|||
i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
|
||||
struct drm_file *file_priv)
|
||||
{
|
||||
drm_i915_private_t *dev_priv = dev->dev_private;
|
||||
int ret;
|
||||
|
||||
if (drm_core_check_feature(dev, DRIVER_MODESET))
|
||||
|
|
@ -3264,7 +3289,6 @@ i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
|
|||
ret = i915_gem_idle(dev);
|
||||
drm_irq_uninstall(dev);
|
||||
|
||||
io_mapping_free(dev_priv->mm.gtt_mapping);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -3273,6 +3297,9 @@ i915_gem_lastclose(struct drm_device *dev)
|
|||
{
|
||||
int ret;
|
||||
|
||||
if (drm_core_check_feature(dev, DRIVER_MODESET))
|
||||
return;
|
||||
|
||||
ret = i915_gem_idle(dev);
|
||||
if (ret)
|
||||
DRM_ERROR("failed to idle hardware: %d\n", ret);
|
||||
|
|
@ -3294,7 +3321,7 @@ i915_gem_load(struct drm_device *dev)
|
|||
/* Old X drivers will take 0-2 for front, back, depth buffers */
|
||||
dev_priv->fence_reg_start = 3;
|
||||
|
||||
if (IS_I965G(dev))
|
||||
if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
|
||||
dev_priv->num_fence_regs = 16;
|
||||
else
|
||||
dev_priv->num_fence_regs = 8;
|
||||
|
|
|
|||
|
|
@ -173,6 +173,73 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
|
|||
dev_priv->mm.bit_6_swizzle_y = swizzle_y;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Returns the size of the fence for a tiled object of the given size.
|
||||
*/
|
||||
static int
|
||||
i915_get_fence_size(struct drm_device *dev, int size)
|
||||
{
|
||||
int i;
|
||||
int start;
|
||||
|
||||
if (IS_I965G(dev)) {
|
||||
/* The 965 can have fences at any page boundary. */
|
||||
return ALIGN(size, 4096);
|
||||
} else {
|
||||
/* Align the size to a power of two greater than the smallest
|
||||
* fence size.
|
||||
*/
|
||||
if (IS_I9XX(dev))
|
||||
start = 1024 * 1024;
|
||||
else
|
||||
start = 512 * 1024;
|
||||
|
||||
for (i = start; i < size; i <<= 1)
|
||||
;
|
||||
|
||||
return i;
|
||||
}
|
||||
}
|
||||
|
||||
/* Check pitch constriants for all chips & tiling formats */
|
||||
static bool
|
||||
i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
|
||||
{
|
||||
int tile_width;
|
||||
|
||||
/* Linear is always fine */
|
||||
if (tiling_mode == I915_TILING_NONE)
|
||||
return true;
|
||||
|
||||
if (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
|
||||
tile_width = 128;
|
||||
else
|
||||
tile_width = 512;
|
||||
|
||||
/* 965+ just needs multiples of tile width */
|
||||
if (IS_I965G(dev)) {
|
||||
if (stride & (tile_width - 1))
|
||||
return false;
|
||||
return true;
|
||||
}
|
||||
|
||||
/* Pre-965 needs power of two tile widths */
|
||||
if (stride < tile_width)
|
||||
return false;
|
||||
|
||||
if (stride & (stride - 1))
|
||||
return false;
|
||||
|
||||
/* We don't handle the aperture area covered by the fence being bigger
|
||||
* than the object size.
|
||||
*/
|
||||
if (i915_get_fence_size(dev, size) != size)
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
* Sets the tiling mode of an object, returning the required swizzling of
|
||||
* bit 6 of addresses in the object.
|
||||
|
|
@ -191,6 +258,11 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
|
|||
return -EINVAL;
|
||||
obj_priv = obj->driver_private;
|
||||
|
||||
if (!i915_tiling_ok(dev, args->stride, obj->size, args->tiling_mode)) {
|
||||
drm_gem_object_unreference(obj);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
mutex_lock(&dev->struct_mutex);
|
||||
|
||||
if (args->tiling_mode == I915_TILING_NONE) {
|
||||
|
|
@ -207,7 +279,24 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
|
|||
args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
|
||||
}
|
||||
}
|
||||
obj_priv->tiling_mode = args->tiling_mode;
|
||||
if (args->tiling_mode != obj_priv->tiling_mode) {
|
||||
int ret;
|
||||
|
||||
/* Unbind the object, as switching tiling means we're
|
||||
* switching the cache organization due to fencing, probably.
|
||||
*/
|
||||
ret = i915_gem_object_unbind(obj);
|
||||
if (ret != 0) {
|
||||
WARN(ret != -ERESTARTSYS,
|
||||
"failed to unbind object for tiling switch");
|
||||
args->tiling_mode = obj_priv->tiling_mode;
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
drm_gem_object_unreference(obj);
|
||||
|
||||
return ret;
|
||||
}
|
||||
obj_priv->tiling_mode = args->tiling_mode;
|
||||
}
|
||||
obj_priv->stride = args->stride;
|
||||
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
|
|
|
|||
|
|
@ -174,6 +174,19 @@ u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
|
|||
return count;
|
||||
}
|
||||
|
||||
u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
|
||||
{
|
||||
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
||||
int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
|
||||
|
||||
if (!i915_pipe_enabled(dev, pipe)) {
|
||||
DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return I915_READ(reg);
|
||||
}
|
||||
|
||||
irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
|
||||
{
|
||||
struct drm_device *dev = (struct drm_device *) arg;
|
||||
|
|
|
|||
|
|
@ -186,12 +186,12 @@
|
|||
#define FENCE_REG_830_0 0x2000
|
||||
#define I830_FENCE_START_MASK 0x07f80000
|
||||
#define I830_FENCE_TILING_Y_SHIFT 12
|
||||
#define I830_FENCE_SIZE_BITS(size) ((get_order(size >> 19) - 1) << 8)
|
||||
#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
|
||||
#define I830_FENCE_PITCH_SHIFT 4
|
||||
#define I830_FENCE_REG_VALID (1<<0)
|
||||
|
||||
#define I915_FENCE_START_MASK 0x0ff00000
|
||||
#define I915_FENCE_SIZE_BITS(size) ((get_order(size >> 20) - 1) << 8)
|
||||
#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
|
||||
|
||||
#define FENCE_REG_965_0 0x03000
|
||||
#define I965_FENCE_PITCH_SHIFT 2
|
||||
|
|
@ -1371,6 +1371,9 @@
|
|||
#define PIPE_FRAME_LOW_SHIFT 24
|
||||
#define PIPE_PIXEL_MASK 0x00ffffff
|
||||
#define PIPE_PIXEL_SHIFT 0
|
||||
/* GM45+ just has to be different */
|
||||
#define PIPEA_FRMCOUNT_GM45 0x70040
|
||||
#define PIPEA_FLIPCOUNT_GM45 0x70044
|
||||
|
||||
/* Cursor A & B regs */
|
||||
#define CURACNTR 0x70080
|
||||
|
|
@ -1439,6 +1442,9 @@
|
|||
#define PIPEBSTAT 0x71024
|
||||
#define PIPEBFRAMEHIGH 0x71040
|
||||
#define PIPEBFRAMEPIXEL 0x71044
|
||||
#define PIPEB_FRMCOUNT_GM45 0x71040
|
||||
#define PIPEB_FLIPCOUNT_GM45 0x71044
|
||||
|
||||
|
||||
/* Display B control */
|
||||
#define DSPBCNTR 0x71180
|
||||
|
|
|
|||
|
|
@ -755,6 +755,8 @@ static void intel_crtc_mode_set(struct drm_crtc *crtc,
|
|||
case INTEL_OUTPUT_SDVO:
|
||||
case INTEL_OUTPUT_HDMI:
|
||||
is_sdvo = true;
|
||||
if (intel_output->needs_tv_clock)
|
||||
is_tv = true;
|
||||
break;
|
||||
case INTEL_OUTPUT_DVO:
|
||||
is_dvo = true;
|
||||
|
|
@ -1452,6 +1454,7 @@ static int intel_connector_clones(struct drm_device *dev, int type_mask)
|
|||
|
||||
static void intel_setup_outputs(struct drm_device *dev)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
struct drm_connector *connector;
|
||||
|
||||
intel_crt_init(dev);
|
||||
|
|
@ -1463,13 +1466,16 @@ static void intel_setup_outputs(struct drm_device *dev)
|
|||
if (IS_I9XX(dev)) {
|
||||
int found;
|
||||
|
||||
found = intel_sdvo_init(dev, SDVOB);
|
||||
if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
|
||||
intel_hdmi_init(dev, SDVOB);
|
||||
|
||||
found = intel_sdvo_init(dev, SDVOC);
|
||||
if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
|
||||
intel_hdmi_init(dev, SDVOC);
|
||||
if (I915_READ(SDVOB) & SDVO_DETECTED) {
|
||||
found = intel_sdvo_init(dev, SDVOB);
|
||||
if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
|
||||
intel_hdmi_init(dev, SDVOB);
|
||||
}
|
||||
if (!IS_G4X(dev) || (I915_READ(SDVOB) & SDVO_DETECTED)) {
|
||||
found = intel_sdvo_init(dev, SDVOC);
|
||||
if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
|
||||
intel_hdmi_init(dev, SDVOC);
|
||||
}
|
||||
} else
|
||||
intel_dvo_init(dev);
|
||||
|
||||
|
|
|
|||
|
|
@ -82,6 +82,7 @@ struct intel_output {
|
|||
struct intel_i2c_chan *i2c_bus; /* for control functions */
|
||||
struct intel_i2c_chan *ddc_bus; /* for DDC only stuff */
|
||||
bool load_detect_temp;
|
||||
bool needs_tv_clock;
|
||||
void *dev_priv;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@
|
|||
* Jesse Barnes <jesse.barnes@intel.com>
|
||||
*/
|
||||
|
||||
#include <linux/dmi.h>
|
||||
#include <linux/i2c.h>
|
||||
#include "drmP.h"
|
||||
#include "drm.h"
|
||||
|
|
@ -311,10 +312,8 @@ static int intel_lvds_get_modes(struct drm_connector *connector)
|
|||
if (dev_priv->panel_fixed_mode != NULL) {
|
||||
struct drm_display_mode *mode;
|
||||
|
||||
mutex_lock(&dev->mode_config.mutex);
|
||||
mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
|
||||
drm_mode_probed_add(connector, mode);
|
||||
mutex_unlock(&dev->mode_config.mutex);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
|
@ -405,6 +404,16 @@ void intel_lvds_init(struct drm_device *dev)
|
|||
u32 lvds;
|
||||
int pipe;
|
||||
|
||||
/* Blacklist machines that we know falsely report LVDS. */
|
||||
/* FIXME: add a check for the Aopen Mini PC */
|
||||
|
||||
/* Apple Mac Mini Core Duo and Mac Mini Core 2 Duo */
|
||||
if(dmi_match(DMI_PRODUCT_NAME, "Macmini1,1") ||
|
||||
dmi_match(DMI_PRODUCT_NAME, "Macmini2,1")) {
|
||||
DRM_DEBUG("Skipping LVDS initialization for Apple Mac Mini\n");
|
||||
return;
|
||||
}
|
||||
|
||||
intel_output = kzalloc(sizeof(struct intel_output), GFP_KERNEL);
|
||||
if (!intel_output) {
|
||||
return;
|
||||
|
|
@ -458,7 +467,7 @@ void intel_lvds_init(struct drm_device *dev)
|
|||
dev_priv->panel_fixed_mode =
|
||||
drm_mode_duplicate(dev, scan);
|
||||
mutex_unlock(&dev->mode_config.mutex);
|
||||
goto out; /* FIXME: check for quirks */
|
||||
goto out;
|
||||
}
|
||||
mutex_unlock(&dev->mode_config.mutex);
|
||||
}
|
||||
|
|
@ -492,7 +501,7 @@ void intel_lvds_init(struct drm_device *dev)
|
|||
if (dev_priv->panel_fixed_mode) {
|
||||
dev_priv->panel_fixed_mode->type |=
|
||||
DRM_MODE_TYPE_PREFERRED;
|
||||
goto out; /* FIXME: check for quirks */
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -500,38 +509,6 @@ void intel_lvds_init(struct drm_device *dev)
|
|||
if (!dev_priv->panel_fixed_mode)
|
||||
goto failed;
|
||||
|
||||
/* FIXME: detect aopen & mac mini type stuff automatically? */
|
||||
/*
|
||||
* Blacklist machines with BIOSes that list an LVDS panel without
|
||||
* actually having one.
|
||||
*/
|
||||
if (IS_I945GM(dev)) {
|
||||
/* aopen mini pc */
|
||||
if (dev->pdev->subsystem_vendor == 0xa0a0)
|
||||
goto failed;
|
||||
|
||||
if ((dev->pdev->subsystem_vendor == 0x8086) &&
|
||||
(dev->pdev->subsystem_device == 0x7270)) {
|
||||
/* It's a Mac Mini or Macbook Pro.
|
||||
*
|
||||
* Apple hardware is out to get us. The macbook pro
|
||||
* has a real LVDS panel, but the mac mini does not,
|
||||
* and they have the same device IDs. We'll
|
||||
* distinguish by panel size, on the assumption
|
||||
* that Apple isn't about to make any machines with an
|
||||
* 800x600 display.
|
||||
*/
|
||||
|
||||
if (dev_priv->panel_fixed_mode != NULL &&
|
||||
dev_priv->panel_fixed_mode->hdisplay == 800 &&
|
||||
dev_priv->panel_fixed_mode->vdisplay == 600) {
|
||||
DRM_DEBUG("Suspected Mac Mini, ignoring the LVDS\n");
|
||||
goto failed;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
out:
|
||||
drm_sysfs_connector_add(connector);
|
||||
return;
|
||||
|
|
|
|||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -173,6 +173,9 @@ struct intel_sdvo_get_trained_inputs_response {
|
|||
* Returns two struct intel_sdvo_output_flags structures.
|
||||
*/
|
||||
#define SDVO_CMD_GET_IN_OUT_MAP 0x06
|
||||
struct intel_sdvo_in_out_map {
|
||||
u16 in0, in1;
|
||||
};
|
||||
|
||||
/**
|
||||
* Sets the current mapping of SDVO inputs to outputs on the device.
|
||||
|
|
@ -206,7 +209,8 @@ struct intel_sdvo_get_trained_inputs_response {
|
|||
struct intel_sdvo_get_interrupt_event_source_response {
|
||||
u16 interrupt_status;
|
||||
unsigned int ambient_light_interrupt:1;
|
||||
unsigned int pad:7;
|
||||
unsigned int hdmi_audio_encrypt_change:1;
|
||||
unsigned int pad:6;
|
||||
} __attribute__((packed));
|
||||
|
||||
/**
|
||||
|
|
@ -305,23 +309,411 @@ struct intel_sdvo_set_target_input_args {
|
|||
# define SDVO_CLOCK_RATE_MULT_4X (1 << 3)
|
||||
|
||||
#define SDVO_CMD_GET_SUPPORTED_TV_FORMATS 0x27
|
||||
/** 5 bytes of bit flags for TV formats shared by all TV format functions */
|
||||
struct intel_sdvo_tv_format {
|
||||
unsigned int ntsc_m:1;
|
||||
unsigned int ntsc_j:1;
|
||||
unsigned int ntsc_443:1;
|
||||
unsigned int pal_b:1;
|
||||
unsigned int pal_d:1;
|
||||
unsigned int pal_g:1;
|
||||
unsigned int pal_h:1;
|
||||
unsigned int pal_i:1;
|
||||
|
||||
unsigned int pal_m:1;
|
||||
unsigned int pal_n:1;
|
||||
unsigned int pal_nc:1;
|
||||
unsigned int pal_60:1;
|
||||
unsigned int secam_b:1;
|
||||
unsigned int secam_d:1;
|
||||
unsigned int secam_g:1;
|
||||
unsigned int secam_k:1;
|
||||
|
||||
unsigned int secam_k1:1;
|
||||
unsigned int secam_l:1;
|
||||
unsigned int secam_60:1;
|
||||
unsigned int hdtv_std_smpte_240m_1080i_59:1;
|
||||
unsigned int hdtv_std_smpte_240m_1080i_60:1;
|
||||
unsigned int hdtv_std_smpte_260m_1080i_59:1;
|
||||
unsigned int hdtv_std_smpte_260m_1080i_60:1;
|
||||
unsigned int hdtv_std_smpte_274m_1080i_50:1;
|
||||
|
||||
unsigned int hdtv_std_smpte_274m_1080i_59:1;
|
||||
unsigned int hdtv_std_smpte_274m_1080i_60:1;
|
||||
unsigned int hdtv_std_smpte_274m_1080p_23:1;
|
||||
unsigned int hdtv_std_smpte_274m_1080p_24:1;
|
||||
unsigned int hdtv_std_smpte_274m_1080p_25:1;
|
||||
unsigned int hdtv_std_smpte_274m_1080p_29:1;
|
||||
unsigned int hdtv_std_smpte_274m_1080p_30:1;
|
||||
unsigned int hdtv_std_smpte_274m_1080p_50:1;
|
||||
|
||||
unsigned int hdtv_std_smpte_274m_1080p_59:1;
|
||||
unsigned int hdtv_std_smpte_274m_1080p_60:1;
|
||||
unsigned int hdtv_std_smpte_295m_1080i_50:1;
|
||||
unsigned int hdtv_std_smpte_295m_1080p_50:1;
|
||||
unsigned int hdtv_std_smpte_296m_720p_59:1;
|
||||
unsigned int hdtv_std_smpte_296m_720p_60:1;
|
||||
unsigned int hdtv_std_smpte_296m_720p_50:1;
|
||||
unsigned int hdtv_std_smpte_293m_480p_59:1;
|
||||
|
||||
unsigned int hdtv_std_smpte_170m_480i_59:1;
|
||||
unsigned int hdtv_std_iturbt601_576i_50:1;
|
||||
unsigned int hdtv_std_iturbt601_576p_50:1;
|
||||
unsigned int hdtv_std_eia_7702a_480i_60:1;
|
||||
unsigned int hdtv_std_eia_7702a_480p_60:1;
|
||||
unsigned int pad:3;
|
||||
} __attribute__((packed));
|
||||
|
||||
#define SDVO_CMD_GET_TV_FORMAT 0x28
|
||||
|
||||
#define SDVO_CMD_SET_TV_FORMAT 0x29
|
||||
|
||||
/** Returns the resolutiosn that can be used with the given TV format */
|
||||
#define SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT 0x83
|
||||
struct intel_sdvo_sdtv_resolution_request {
|
||||
unsigned int ntsc_m:1;
|
||||
unsigned int ntsc_j:1;
|
||||
unsigned int ntsc_443:1;
|
||||
unsigned int pal_b:1;
|
||||
unsigned int pal_d:1;
|
||||
unsigned int pal_g:1;
|
||||
unsigned int pal_h:1;
|
||||
unsigned int pal_i:1;
|
||||
|
||||
unsigned int pal_m:1;
|
||||
unsigned int pal_n:1;
|
||||
unsigned int pal_nc:1;
|
||||
unsigned int pal_60:1;
|
||||
unsigned int secam_b:1;
|
||||
unsigned int secam_d:1;
|
||||
unsigned int secam_g:1;
|
||||
unsigned int secam_k:1;
|
||||
|
||||
unsigned int secam_k1:1;
|
||||
unsigned int secam_l:1;
|
||||
unsigned int secam_60:1;
|
||||
unsigned int pad:5;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct intel_sdvo_sdtv_resolution_reply {
|
||||
unsigned int res_320x200:1;
|
||||
unsigned int res_320x240:1;
|
||||
unsigned int res_400x300:1;
|
||||
unsigned int res_640x350:1;
|
||||
unsigned int res_640x400:1;
|
||||
unsigned int res_640x480:1;
|
||||
unsigned int res_704x480:1;
|
||||
unsigned int res_704x576:1;
|
||||
|
||||
unsigned int res_720x350:1;
|
||||
unsigned int res_720x400:1;
|
||||
unsigned int res_720x480:1;
|
||||
unsigned int res_720x540:1;
|
||||
unsigned int res_720x576:1;
|
||||
unsigned int res_768x576:1;
|
||||
unsigned int res_800x600:1;
|
||||
unsigned int res_832x624:1;
|
||||
|
||||
unsigned int res_920x766:1;
|
||||
unsigned int res_1024x768:1;
|
||||
unsigned int res_1280x1024:1;
|
||||
unsigned int pad:5;
|
||||
} __attribute__((packed));
|
||||
|
||||
/* Get supported resolution with squire pixel aspect ratio that can be
|
||||
scaled for the requested HDTV format */
|
||||
#define SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT 0x85
|
||||
|
||||
struct intel_sdvo_hdtv_resolution_request {
|
||||
unsigned int hdtv_std_smpte_240m_1080i_59:1;
|
||||
unsigned int hdtv_std_smpte_240m_1080i_60:1;
|
||||
unsigned int hdtv_std_smpte_260m_1080i_59:1;
|
||||
unsigned int hdtv_std_smpte_260m_1080i_60:1;
|
||||
unsigned int hdtv_std_smpte_274m_1080i_50:1;
|
||||
unsigned int hdtv_std_smpte_274m_1080i_59:1;
|
||||
unsigned int hdtv_std_smpte_274m_1080i_60:1;
|
||||
unsigned int hdtv_std_smpte_274m_1080p_23:1;
|
||||
|
||||
unsigned int hdtv_std_smpte_274m_1080p_24:1;
|
||||
unsigned int hdtv_std_smpte_274m_1080p_25:1;
|
||||
unsigned int hdtv_std_smpte_274m_1080p_29:1;
|
||||
unsigned int hdtv_std_smpte_274m_1080p_30:1;
|
||||
unsigned int hdtv_std_smpte_274m_1080p_50:1;
|
||||
unsigned int hdtv_std_smpte_274m_1080p_59:1;
|
||||
unsigned int hdtv_std_smpte_274m_1080p_60:1;
|
||||
unsigned int hdtv_std_smpte_295m_1080i_50:1;
|
||||
|
||||
unsigned int hdtv_std_smpte_295m_1080p_50:1;
|
||||
unsigned int hdtv_std_smpte_296m_720p_59:1;
|
||||
unsigned int hdtv_std_smpte_296m_720p_60:1;
|
||||
unsigned int hdtv_std_smpte_296m_720p_50:1;
|
||||
unsigned int hdtv_std_smpte_293m_480p_59:1;
|
||||
unsigned int hdtv_std_smpte_170m_480i_59:1;
|
||||
unsigned int hdtv_std_iturbt601_576i_50:1;
|
||||
unsigned int hdtv_std_iturbt601_576p_50:1;
|
||||
|
||||
unsigned int hdtv_std_eia_7702a_480i_60:1;
|
||||
unsigned int hdtv_std_eia_7702a_480p_60:1;
|
||||
unsigned int pad:6;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct intel_sdvo_hdtv_resolution_reply {
|
||||
unsigned int res_640x480:1;
|
||||
unsigned int res_800x600:1;
|
||||
unsigned int res_1024x768:1;
|
||||
unsigned int res_1280x960:1;
|
||||
unsigned int res_1400x1050:1;
|
||||
unsigned int res_1600x1200:1;
|
||||
unsigned int res_1920x1440:1;
|
||||
unsigned int res_2048x1536:1;
|
||||
|
||||
unsigned int res_2560x1920:1;
|
||||
unsigned int res_3200x2400:1;
|
||||
unsigned int res_3840x2880:1;
|
||||
unsigned int pad1:5;
|
||||
|
||||
unsigned int res_848x480:1;
|
||||
unsigned int res_1064x600:1;
|
||||
unsigned int res_1280x720:1;
|
||||
unsigned int res_1360x768:1;
|
||||
unsigned int res_1704x960:1;
|
||||
unsigned int res_1864x1050:1;
|
||||
unsigned int res_1920x1080:1;
|
||||
unsigned int res_2128x1200:1;
|
||||
|
||||
unsigned int res_2560x1400:1;
|
||||
unsigned int res_2728x1536:1;
|
||||
unsigned int res_3408x1920:1;
|
||||
unsigned int res_4264x2400:1;
|
||||
unsigned int res_5120x2880:1;
|
||||
unsigned int pad2:3;
|
||||
|
||||
unsigned int res_768x480:1;
|
||||
unsigned int res_960x600:1;
|
||||
unsigned int res_1152x720:1;
|
||||
unsigned int res_1124x768:1;
|
||||
unsigned int res_1536x960:1;
|
||||
unsigned int res_1680x1050:1;
|
||||
unsigned int res_1728x1080:1;
|
||||
unsigned int res_1920x1200:1;
|
||||
|
||||
unsigned int res_2304x1440:1;
|
||||
unsigned int res_2456x1536:1;
|
||||
unsigned int res_3072x1920:1;
|
||||
unsigned int res_3840x2400:1;
|
||||
unsigned int res_4608x2880:1;
|
||||
unsigned int pad3:3;
|
||||
|
||||
unsigned int res_1280x1024:1;
|
||||
unsigned int pad4:7;
|
||||
|
||||
unsigned int res_1280x768:1;
|
||||
unsigned int pad5:7;
|
||||
} __attribute__((packed));
|
||||
|
||||
/* Get supported power state returns info for encoder and monitor, rely on
|
||||
last SetTargetInput and SetTargetOutput calls */
|
||||
#define SDVO_CMD_GET_SUPPORTED_POWER_STATES 0x2a
|
||||
/* Get power state returns info for encoder and monitor, rely on last
|
||||
SetTargetInput and SetTargetOutput calls */
|
||||
#define SDVO_CMD_GET_POWER_STATE 0x2b
|
||||
#define SDVO_CMD_GET_ENCODER_POWER_STATE 0x2b
|
||||
#define SDVO_CMD_SET_ENCODER_POWER_STATE 0x2c
|
||||
# define SDVO_ENCODER_STATE_ON (1 << 0)
|
||||
# define SDVO_ENCODER_STATE_STANDBY (1 << 1)
|
||||
# define SDVO_ENCODER_STATE_SUSPEND (1 << 2)
|
||||
# define SDVO_ENCODER_STATE_OFF (1 << 3)
|
||||
# define SDVO_MONITOR_STATE_ON (1 << 4)
|
||||
# define SDVO_MONITOR_STATE_STANDBY (1 << 5)
|
||||
# define SDVO_MONITOR_STATE_SUSPEND (1 << 6)
|
||||
# define SDVO_MONITOR_STATE_OFF (1 << 7)
|
||||
|
||||
#define SDVO_CMD_SET_TV_RESOLUTION_SUPPORT 0x93
|
||||
#define SDVO_CMD_GET_MAX_PANEL_POWER_SEQUENCING 0x2d
|
||||
#define SDVO_CMD_GET_PANEL_POWER_SEQUENCING 0x2e
|
||||
#define SDVO_CMD_SET_PANEL_POWER_SEQUENCING 0x2f
|
||||
/**
|
||||
* The panel power sequencing parameters are in units of milliseconds.
|
||||
* The high fields are bits 8:9 of the 10-bit values.
|
||||
*/
|
||||
struct sdvo_panel_power_sequencing {
|
||||
u8 t0;
|
||||
u8 t1;
|
||||
u8 t2;
|
||||
u8 t3;
|
||||
u8 t4;
|
||||
|
||||
unsigned int t0_high:2;
|
||||
unsigned int t1_high:2;
|
||||
unsigned int t2_high:2;
|
||||
unsigned int t3_high:2;
|
||||
|
||||
unsigned int t4_high:2;
|
||||
unsigned int pad:6;
|
||||
} __attribute__((packed));
|
||||
|
||||
#define SDVO_CMD_GET_MAX_BACKLIGHT_LEVEL 0x30
|
||||
struct sdvo_max_backlight_reply {
|
||||
u8 max_value;
|
||||
u8 default_value;
|
||||
} __attribute__((packed));
|
||||
|
||||
#define SDVO_CMD_GET_BACKLIGHT_LEVEL 0x31
|
||||
#define SDVO_CMD_SET_BACKLIGHT_LEVEL 0x32
|
||||
|
||||
#define SDVO_CMD_GET_AMBIENT_LIGHT 0x33
|
||||
struct sdvo_get_ambient_light_reply {
|
||||
u16 trip_low;
|
||||
u16 trip_high;
|
||||
u16 value;
|
||||
} __attribute__((packed));
|
||||
#define SDVO_CMD_SET_AMBIENT_LIGHT 0x34
|
||||
struct sdvo_set_ambient_light_reply {
|
||||
u16 trip_low;
|
||||
u16 trip_high;
|
||||
unsigned int enable:1;
|
||||
unsigned int pad:7;
|
||||
} __attribute__((packed));
|
||||
|
||||
/* Set display power state */
|
||||
#define SDVO_CMD_SET_DISPLAY_POWER_STATE 0x7d
|
||||
# define SDVO_DISPLAY_STATE_ON (1 << 0)
|
||||
# define SDVO_DISPLAY_STATE_STANDBY (1 << 1)
|
||||
# define SDVO_DISPLAY_STATE_SUSPEND (1 << 2)
|
||||
# define SDVO_DISPLAY_STATE_OFF (1 << 3)
|
||||
|
||||
#define SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS 0x84
|
||||
struct intel_sdvo_enhancements_reply {
|
||||
unsigned int flicker_filter:1;
|
||||
unsigned int flicker_filter_adaptive:1;
|
||||
unsigned int flicker_filter_2d:1;
|
||||
unsigned int saturation:1;
|
||||
unsigned int hue:1;
|
||||
unsigned int brightness:1;
|
||||
unsigned int contrast:1;
|
||||
unsigned int overscan_h:1;
|
||||
|
||||
unsigned int overscan_v:1;
|
||||
unsigned int position_h:1;
|
||||
unsigned int position_v:1;
|
||||
unsigned int sharpness:1;
|
||||
unsigned int dot_crawl:1;
|
||||
unsigned int dither:1;
|
||||
unsigned int max_tv_chroma_filter:1;
|
||||
unsigned int max_tv_luma_filter:1;
|
||||
} __attribute__((packed));
|
||||
|
||||
/* Picture enhancement limits below are dependent on the current TV format,
|
||||
* and thus need to be queried and set after it.
|
||||
*/
|
||||
#define SDVO_CMD_GET_MAX_FLICKER_FITER 0x4d
|
||||
#define SDVO_CMD_GET_MAX_ADAPTIVE_FLICKER_FITER 0x7b
|
||||
#define SDVO_CMD_GET_MAX_2D_FLICKER_FITER 0x52
|
||||
#define SDVO_CMD_GET_MAX_SATURATION 0x55
|
||||
#define SDVO_CMD_GET_MAX_HUE 0x58
|
||||
#define SDVO_CMD_GET_MAX_BRIGHTNESS 0x5b
|
||||
#define SDVO_CMD_GET_MAX_CONTRAST 0x5e
|
||||
#define SDVO_CMD_GET_MAX_OVERSCAN_H 0x61
|
||||
#define SDVO_CMD_GET_MAX_OVERSCAN_V 0x64
|
||||
#define SDVO_CMD_GET_MAX_POSITION_H 0x67
|
||||
#define SDVO_CMD_GET_MAX_POSITION_V 0x6a
|
||||
#define SDVO_CMD_GET_MAX_SHARPNESS_V 0x6d
|
||||
#define SDVO_CMD_GET_MAX_TV_CHROMA 0x74
|
||||
#define SDVO_CMD_GET_MAX_TV_LUMA 0x77
|
||||
struct intel_sdvo_enhancement_limits_reply {
|
||||
u16 max_value;
|
||||
u16 default_value;
|
||||
} __attribute__((packed));
|
||||
|
||||
#define SDVO_CMD_GET_LVDS_PANEL_INFORMATION 0x7f
|
||||
#define SDVO_CMD_SET_LVDS_PANEL_INFORMATION 0x80
|
||||
# define SDVO_LVDS_COLOR_DEPTH_18 (0 << 0)
|
||||
# define SDVO_LVDS_COLOR_DEPTH_24 (1 << 0)
|
||||
# define SDVO_LVDS_CONNECTOR_SPWG (0 << 2)
|
||||
# define SDVO_LVDS_CONNECTOR_OPENLDI (1 << 2)
|
||||
# define SDVO_LVDS_SINGLE_CHANNEL (0 << 4)
|
||||
# define SDVO_LVDS_DUAL_CHANNEL (1 << 4)
|
||||
|
||||
#define SDVO_CMD_GET_FLICKER_FILTER 0x4e
|
||||
#define SDVO_CMD_SET_FLICKER_FILTER 0x4f
|
||||
#define SDVO_CMD_GET_ADAPTIVE_FLICKER_FITER 0x50
|
||||
#define SDVO_CMD_SET_ADAPTIVE_FLICKER_FITER 0x51
|
||||
#define SDVO_CMD_GET_2D_FLICKER_FITER 0x53
|
||||
#define SDVO_CMD_SET_2D_FLICKER_FITER 0x54
|
||||
#define SDVO_CMD_GET_SATURATION 0x56
|
||||
#define SDVO_CMD_SET_SATURATION 0x57
|
||||
#define SDVO_CMD_GET_HUE 0x59
|
||||
#define SDVO_CMD_SET_HUE 0x5a
|
||||
#define SDVO_CMD_GET_BRIGHTNESS 0x5c
|
||||
#define SDVO_CMD_SET_BRIGHTNESS 0x5d
|
||||
#define SDVO_CMD_GET_CONTRAST 0x5f
|
||||
#define SDVO_CMD_SET_CONTRAST 0x60
|
||||
#define SDVO_CMD_GET_OVERSCAN_H 0x62
|
||||
#define SDVO_CMD_SET_OVERSCAN_H 0x63
|
||||
#define SDVO_CMD_GET_OVERSCAN_V 0x65
|
||||
#define SDVO_CMD_SET_OVERSCAN_V 0x66
|
||||
#define SDVO_CMD_GET_POSITION_H 0x68
|
||||
#define SDVO_CMD_SET_POSITION_H 0x69
|
||||
#define SDVO_CMD_GET_POSITION_V 0x6b
|
||||
#define SDVO_CMD_SET_POSITION_V 0x6c
|
||||
#define SDVO_CMD_GET_SHARPNESS 0x6e
|
||||
#define SDVO_CMD_SET_SHARPNESS 0x6f
|
||||
#define SDVO_CMD_GET_TV_CHROMA 0x75
|
||||
#define SDVO_CMD_SET_TV_CHROMA 0x76
|
||||
#define SDVO_CMD_GET_TV_LUMA 0x78
|
||||
#define SDVO_CMD_SET_TV_LUMA 0x79
|
||||
struct intel_sdvo_enhancements_arg {
|
||||
u16 value;
|
||||
}__attribute__((packed));
|
||||
|
||||
#define SDVO_CMD_GET_DOT_CRAWL 0x70
|
||||
#define SDVO_CMD_SET_DOT_CRAWL 0x71
|
||||
# define SDVO_DOT_CRAWL_ON (1 << 0)
|
||||
# define SDVO_DOT_CRAWL_DEFAULT_ON (1 << 1)
|
||||
|
||||
#define SDVO_CMD_GET_DITHER 0x72
|
||||
#define SDVO_CMD_SET_DITHER 0x73
|
||||
# define SDVO_DITHER_ON (1 << 0)
|
||||
# define SDVO_DITHER_DEFAULT_ON (1 << 1)
|
||||
|
||||
#define SDVO_CMD_SET_CONTROL_BUS_SWITCH 0x7a
|
||||
# define SDVO_CONTROL_BUS_PROM 0x0
|
||||
# define SDVO_CONTROL_BUS_DDC1 0x1
|
||||
# define SDVO_CONTROL_BUS_DDC2 0x2
|
||||
# define SDVO_CONTROL_BUS_DDC3 0x3
|
||||
# define SDVO_CONTROL_BUS_PROM (1 << 0)
|
||||
# define SDVO_CONTROL_BUS_DDC1 (1 << 1)
|
||||
# define SDVO_CONTROL_BUS_DDC2 (1 << 2)
|
||||
# define SDVO_CONTROL_BUS_DDC3 (1 << 3)
|
||||
|
||||
/* HDMI op codes */
|
||||
#define SDVO_CMD_GET_SUPP_ENCODE 0x9d
|
||||
#define SDVO_CMD_GET_ENCODE 0x9e
|
||||
#define SDVO_CMD_SET_ENCODE 0x9f
|
||||
#define SDVO_ENCODE_DVI 0x0
|
||||
#define SDVO_ENCODE_HDMI 0x1
|
||||
#define SDVO_CMD_SET_PIXEL_REPLI 0x8b
|
||||
#define SDVO_CMD_GET_PIXEL_REPLI 0x8c
|
||||
#define SDVO_CMD_GET_COLORIMETRY_CAP 0x8d
|
||||
#define SDVO_CMD_SET_COLORIMETRY 0x8e
|
||||
#define SDVO_COLORIMETRY_RGB256 0x0
|
||||
#define SDVO_COLORIMETRY_RGB220 0x1
|
||||
#define SDVO_COLORIMETRY_YCrCb422 0x3
|
||||
#define SDVO_COLORIMETRY_YCrCb444 0x4
|
||||
#define SDVO_CMD_GET_COLORIMETRY 0x8f
|
||||
#define SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER 0x90
|
||||
#define SDVO_CMD_SET_AUDIO_STAT 0x91
|
||||
#define SDVO_CMD_GET_AUDIO_STAT 0x92
|
||||
#define SDVO_CMD_SET_HBUF_INDEX 0x93
|
||||
#define SDVO_CMD_GET_HBUF_INDEX 0x94
|
||||
#define SDVO_CMD_GET_HBUF_INFO 0x95
|
||||
#define SDVO_CMD_SET_HBUF_AV_SPLIT 0x96
|
||||
#define SDVO_CMD_GET_HBUF_AV_SPLIT 0x97
|
||||
#define SDVO_CMD_SET_HBUF_DATA 0x98
|
||||
#define SDVO_CMD_GET_HBUF_DATA 0x99
|
||||
#define SDVO_CMD_SET_HBUF_TXRATE 0x9a
|
||||
#define SDVO_CMD_GET_HBUF_TXRATE 0x9b
|
||||
#define SDVO_HBUF_TX_DISABLED (0 << 6)
|
||||
#define SDVO_HBUF_TX_ONCE (2 << 6)
|
||||
#define SDVO_HBUF_TX_VSYNC (3 << 6)
|
||||
#define SDVO_CMD_GET_AUDIO_TX_INFO 0x9c
|
||||
|
||||
struct intel_sdvo_encode{
|
||||
u8 dvi_rev;
|
||||
u8 hdmi_rev;
|
||||
} __attribute__ ((packed));
|
||||
|
|
|
|||
|
|
@ -1039,9 +1039,9 @@ static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
|
|||
|
||||
#if __OS_HAS_AGP
|
||||
if (dev_priv->flags & RADEON_IS_AGP) {
|
||||
drm_core_ioremap(dev_priv->cp_ring, dev);
|
||||
drm_core_ioremap(dev_priv->ring_rptr, dev);
|
||||
drm_core_ioremap(dev->agp_buffer_map, dev);
|
||||
drm_core_ioremap_wc(dev_priv->cp_ring, dev);
|
||||
drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
|
||||
drm_core_ioremap_wc(dev->agp_buffer_map, dev);
|
||||
if (!dev_priv->cp_ring->handle ||
|
||||
!dev_priv->ring_rptr->handle ||
|
||||
!dev->agp_buffer_map->handle) {
|
||||
|
|
|
|||
|
|
@ -1054,9 +1054,10 @@ config FB_RIVA_BACKLIGHT
|
|||
|
||||
config FB_I810
|
||||
tristate "Intel 810/815 support (EXPERIMENTAL)"
|
||||
depends on FB && EXPERIMENTAL && PCI && X86_32
|
||||
depends on EXPERIMENTAL && PCI && X86_32
|
||||
select AGP
|
||||
select AGP_INTEL
|
||||
select FB
|
||||
select FB_MODE_HELPERS
|
||||
select FB_CFB_FILLRECT
|
||||
select FB_CFB_COPYAREA
|
||||
|
|
@ -1119,7 +1120,8 @@ config FB_CARILLO_RANCH
|
|||
|
||||
config FB_INTEL
|
||||
tristate "Intel 830M/845G/852GM/855GM/865G/915G/945G/945GM/965G/965GM support (EXPERIMENTAL)"
|
||||
depends on FB && EXPERIMENTAL && PCI && X86
|
||||
depends on EXPERIMENTAL && PCI && X86
|
||||
select FB
|
||||
select AGP
|
||||
select AGP_INTEL
|
||||
select FB_MODE_HELPERS
|
||||
|
|
|
|||
|
|
@ -261,6 +261,7 @@ typedef struct drm_i915_irq_wait {
|
|||
#define I915_PARAM_LAST_DISPATCH 3
|
||||
#define I915_PARAM_CHIPSET_ID 4
|
||||
#define I915_PARAM_HAS_GEM 5
|
||||
#define I915_PARAM_NUM_FENCES_AVAIL 6
|
||||
|
||||
typedef struct drm_i915_getparam {
|
||||
int param;
|
||||
|
|
@ -272,6 +273,7 @@ typedef struct drm_i915_getparam {
|
|||
#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
|
||||
#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
|
||||
#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
|
||||
#define I915_SETPARAM_NUM_USED_FENCES 4
|
||||
|
||||
typedef struct drm_i915_setparam {
|
||||
int param;
|
||||
|
|
|
|||
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Ссылка в новой задаче