dmaengine/dw_dmac: Don't handle block interrupts
Block interrupts give interrupt on completion of every LLI, which is actually too much interrupts. This is just not required for current functioning of dw_dmac. So, just don't handle them at all. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
This commit is contained in:
Родитель
6c618c9de5
Коммит
ff7b05f29f
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@ -192,7 +192,6 @@ static void dwc_initialize(struct dw_dma_chan *dwc)
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/* Enable interrupts */
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channel_set_bit(dw, MASK.XFER, dwc->mask);
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channel_set_bit(dw, MASK.BLOCK, dwc->mask);
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channel_set_bit(dw, MASK.ERROR, dwc->mask);
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dwc->initialized = true;
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@ -329,12 +328,6 @@ static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
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unsigned long flags;
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spin_lock_irqsave(&dwc->lock, flags);
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/*
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* Clear block interrupt flag before scanning so that we don't
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* miss any, and read LLP before RAW_XFER to ensure it is
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* valid if we decide to scan the list.
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*/
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dma_writel(dw, CLEAR.BLOCK, dwc->mask);
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llp = channel_readl(dwc, LLP);
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status_xfer = dma_readl(dw, RAW.XFER);
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@ -470,17 +463,16 @@ EXPORT_SYMBOL(dw_dma_get_dst_addr);
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/* called with dwc->lock held and all DMAC interrupts disabled */
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static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
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u32 status_block, u32 status_err, u32 status_xfer)
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u32 status_err, u32 status_xfer)
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{
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unsigned long flags;
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if (status_block & dwc->mask) {
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if (dwc->mask) {
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void (*callback)(void *param);
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void *callback_param;
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dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
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channel_readl(dwc, LLP));
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dma_writel(dw, CLEAR.BLOCK, dwc->mask);
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callback = dwc->cdesc->period_callback;
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callback_param = dwc->cdesc->period_callback_param;
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@ -520,7 +512,6 @@ static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
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channel_writel(dwc, CTL_LO, 0);
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channel_writel(dwc, CTL_HI, 0);
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dma_writel(dw, CLEAR.BLOCK, dwc->mask);
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dma_writel(dw, CLEAR.ERROR, dwc->mask);
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dma_writel(dw, CLEAR.XFER, dwc->mask);
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@ -537,36 +528,29 @@ static void dw_dma_tasklet(unsigned long data)
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{
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struct dw_dma *dw = (struct dw_dma *)data;
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struct dw_dma_chan *dwc;
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u32 status_block;
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u32 status_xfer;
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u32 status_err;
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int i;
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status_block = dma_readl(dw, RAW.BLOCK);
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status_xfer = dma_readl(dw, RAW.XFER);
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status_err = dma_readl(dw, RAW.ERROR);
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dev_vdbg(dw->dma.dev, "tasklet: status_block=%x status_err=%x\n",
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status_block, status_err);
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dev_vdbg(dw->dma.dev, "tasklet: status_err=%x\n", status_err);
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for (i = 0; i < dw->dma.chancnt; i++) {
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dwc = &dw->chan[i];
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if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
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dwc_handle_cyclic(dw, dwc, status_block, status_err,
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status_xfer);
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dwc_handle_cyclic(dw, dwc, status_err, status_xfer);
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else if (status_err & (1 << i))
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dwc_handle_error(dw, dwc);
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else if ((status_block | status_xfer) & (1 << i))
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else if (status_xfer & (1 << i))
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dwc_scan_descriptors(dw, dwc);
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}
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/*
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* Re-enable interrupts. Block Complete interrupts are only
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* enabled if the INT_EN bit in the descriptor is set. This
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* will trigger a scan before the whole list is done.
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* Re-enable interrupts.
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*/
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channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
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channel_set_bit(dw, MASK.BLOCK, dw->all_chan_mask);
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channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
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}
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@ -583,7 +567,6 @@ static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
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* softirq handler.
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*/
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channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
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channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
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channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
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status = dma_readl(dw, STATUS_INT);
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@ -594,7 +577,6 @@ static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
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/* Try to recover */
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channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
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channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1);
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channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
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channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
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channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
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@ -1068,7 +1050,6 @@ static void dwc_free_chan_resources(struct dma_chan *chan)
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/* Disable interrupts */
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channel_clear_bit(dw, MASK.XFER, dwc->mask);
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channel_clear_bit(dw, MASK.BLOCK, dwc->mask);
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channel_clear_bit(dw, MASK.ERROR, dwc->mask);
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spin_unlock_irqrestore(&dwc->lock, flags);
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@ -1120,7 +1101,6 @@ int dw_dma_cyclic_start(struct dma_chan *chan)
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return -EBUSY;
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}
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dma_writel(dw, CLEAR.BLOCK, dwc->mask);
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dma_writel(dw, CLEAR.ERROR, dwc->mask);
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dma_writel(dw, CLEAR.XFER, dwc->mask);
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@ -1322,7 +1302,6 @@ void dw_dma_cyclic_free(struct dma_chan *chan)
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while (dma_readl(dw, CH_EN) & dwc->mask)
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cpu_relax();
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dma_writel(dw, CLEAR.BLOCK, dwc->mask);
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dma_writel(dw, CLEAR.ERROR, dwc->mask);
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dma_writel(dw, CLEAR.XFER, dwc->mask);
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@ -1347,7 +1326,6 @@ static void dw_dma_off(struct dw_dma *dw)
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dma_writel(dw, CFG, 0);
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channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
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channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
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channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
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channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
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channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
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@ -1449,13 +1427,11 @@ static int __init dw_probe(struct platform_device *pdev)
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/* Clear/disable all interrupts on all channels. */
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dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
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dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
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dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
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dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
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dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
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channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
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channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
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channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
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channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
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channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
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