ARM: dts: rockchip: oder nodes by register address
To create some sort of ordering of nodes, they are suggested to be ordered by their register address. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Heiko Stuebner
Родитель
6e4b3b4b66
Коммит
ff84b90ecd
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@ -40,30 +40,6 @@
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};
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};
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timer@20038000 {
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compatible = "snps,dw-apb-timer-osc";
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reg = <0x20038000 0x100>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
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clock-names = "timer", "pclk";
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};
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timer@2003a000 {
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compatible = "snps,dw-apb-timer-osc";
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reg = <0x2003a000 0x100>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
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clock-names = "timer", "pclk";
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};
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timer@2000e000 {
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compatible = "snps,dw-apb-timer-osc";
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reg = <0x2000e000 0x100>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
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clock-names = "timer", "pclk";
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};
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sram: sram@10080000 {
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compatible = "mmio-sram";
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reg = <0x10080000 0x10000>;
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@ -86,6 +62,30 @@
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#reset-cells = <1>;
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};
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timer@2000e000 {
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compatible = "snps,dw-apb-timer-osc";
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reg = <0x2000e000 0x100>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
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clock-names = "timer", "pclk";
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};
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timer@20038000 {
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compatible = "snps,dw-apb-timer-osc";
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reg = <0x20038000 0x100>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
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clock-names = "timer", "pclk";
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};
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timer@2003a000 {
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compatible = "snps,dw-apb-timer-osc";
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reg = <0x2003a000 0x100>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
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clock-names = "timer", "pclk";
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};
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pinctrl: pinctrl {
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compatible = "rockchip,rk3066a-pinctrl";
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rockchip,grf = <&grf>;
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@ -27,29 +27,6 @@
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clock-output-names = "xin24m";
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};
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scu@1013c000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0x1013c000 0x100>;
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};
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pmu: pmu@20004000 {
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compatible = "rockchip,rk3066-pmu", "syscon";
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reg = <0x20004000 0x100>;
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};
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grf: grf@20008000 {
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compatible = "syscon";
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reg = <0x20008000 0x200>;
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};
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gic: interrupt-controller@1013d000 {
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compatible = "arm,cortex-a9-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x1013d000 0x1000>,
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<0x1013c100 0x0100>;
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};
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L2: l2-cache-controller@10138000 {
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compatible = "arm,pl310-cache";
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reg = <0x10138000 0x1000>;
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@ -57,6 +34,11 @@
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cache-level = <2>;
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};
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scu@1013c000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0x1013c000 0x100>;
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};
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global_timer: global-timer@1013c200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x1013c200 0x20>;
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@ -71,6 +53,14 @@
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clocks = <&cru CORE_PERI>;
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};
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gic: interrupt-controller@1013d000 {
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compatible = "arm,cortex-a9-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x1013d000 0x1000>,
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<0x1013c100 0x0100>;
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};
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uart0: serial@10124000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x10124000 0x400>;
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@ -91,26 +81,6 @@
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status = "disabled";
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};
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uart2: serial@20064000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x20064000 0x400>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <1>;
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clocks = <&cru SCLK_UART2>;
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status = "disabled";
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};
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uart3: serial@20068000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x20068000 0x400>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <1>;
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clocks = <&cru SCLK_UART3>;
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status = "disabled";
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};
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mmc0: dwmmc@10214000 {
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compatible = "rockchip,rk2928-dw-mshc";
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reg = <0x10214000 0x1000>;
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@ -136,4 +106,34 @@
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status = "disabled";
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};
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pmu: pmu@20004000 {
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compatible = "rockchip,rk3066-pmu", "syscon";
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reg = <0x20004000 0x100>;
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};
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grf: grf@20008000 {
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compatible = "syscon";
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reg = <0x20008000 0x200>;
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};
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uart2: serial@20064000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x20064000 0x400>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <1>;
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clocks = <&cru SCLK_UART2>;
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status = "disabled";
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};
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uart3: serial@20068000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x20068000 0x400>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <1>;
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clocks = <&cru SCLK_UART3>;
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status = "disabled";
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};
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};
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