mtd: rawnand: fsl_ifc: fixup SRAM init for newer ctrl versions
Newer versions of the IFC controller use a different method of initializing the internal SRAM: Instead of reading from flash, a bit in the NAND configuration register has to be set in order to trigger the self-initializing process. Signed-off-by: Kurt Kanzenbach <kurt@linutronix.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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@ -30,6 +30,7 @@
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/nand_ecc.h>
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#include <linux/fsl_ifc.h>
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#include <linux/iopoll.h>
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#define ERR_BYTE 0xFF /* Value returned for read
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bytes when read failed */
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@ -769,6 +770,27 @@ static int fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
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uint32_t csor = 0, csor_8k = 0, csor_ext = 0;
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uint32_t cs = priv->bank;
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if (ctrl->version < FSL_IFC_VERSION_1_1_0)
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return 0;
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if (ctrl->version > FSL_IFC_VERSION_1_1_0) {
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u32 ncfgr, status;
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int ret;
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/* Trigger auto initialization */
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ncfgr = ifc_in32(&ifc_runtime->ifc_nand.ncfgr);
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ifc_out32(ncfgr | IFC_NAND_NCFGR_SRAM_INIT_EN, &ifc_runtime->ifc_nand.ncfgr);
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/* Wait until done */
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ret = readx_poll_timeout(ifc_in32, &ifc_runtime->ifc_nand.ncfgr,
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status, !(status & IFC_NAND_NCFGR_SRAM_INIT_EN),
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10, IFC_TIMEOUT_MSECS * 1000);
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if (ret)
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dev_err(priv->dev, "Failed to initialize SRAM!\n");
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return ret;
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}
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/* Save CSOR and CSOR_ext */
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csor = ifc_in32(&ifc_global->csor_cs[cs].csor);
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csor_ext = ifc_in32(&ifc_global->csor_cs[cs].csor_ext);
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@ -825,6 +847,7 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
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struct nand_chip *chip = &priv->chip;
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struct mtd_info *mtd = nand_to_mtd(&priv->chip);
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u32 csor;
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int ret;
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/* Fill in fsl_ifc_mtd structure */
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mtd->dev.parent = priv->dev;
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@ -918,13 +941,9 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
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chip->ecc.algo = NAND_ECC_HAMMING;
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}
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if (ctrl->version >= FSL_IFC_VERSION_1_1_0) {
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int ret;
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ret = fsl_ifc_sram_init(priv);
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if (ret)
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return ret;
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}
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ret = fsl_ifc_sram_init(priv);
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if (ret)
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return ret;
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/*
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* As IFC version 2.0.0 has 16KB of internal SRAM as compared to older
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@ -274,6 +274,8 @@
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*/
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/* Auto Boot Mode */
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#define IFC_NAND_NCFGR_BOOT 0x80000000
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/* SRAM Initialization */
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#define IFC_NAND_NCFGR_SRAM_INIT_EN 0x20000000
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/* Addressing Mode-ROW0+n/COL0 */
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#define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000
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/* Addressing Mode-ROW0+n/COL0+n */
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