dmaengine: sun4i: Add support for cyclic requests with dedicated DMA
Currently the cyclic transfers can be used only with normal DMAs. They can be used by pcm_dmaengine module, which is required for implementing sound with sun4i-hdmi encoder. This is so because the controller can accept audio only from a dedicated DMA. This patch enables them, following the existing style for the scatter/gather type transfers. Signed-off-by: Stefan Mavrodiev <stefan@olimex.com> Acked-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20200110141140.28527-2-stefan@olimex.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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@ -669,43 +669,41 @@ sun4i_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf, size_t len,
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dma_addr_t src, dest;
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u32 endpoints;
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int nr_periods, offset, plength, i;
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u8 ram_type, io_mode, linear_mode;
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if (!is_slave_direction(dir)) {
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dev_err(chan2dev(chan), "Invalid DMA direction\n");
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return NULL;
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}
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if (vchan->is_dedicated) {
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/*
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* As we are using this just for audio data, we need to use
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* normal DMA. There is nothing stopping us from supporting
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* dedicated DMA here as well, so if a client comes up and
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* requires it, it will be simple to implement it.
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*/
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dev_err(chan2dev(chan),
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"Cyclic transfers are only supported on Normal DMA\n");
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return NULL;
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}
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contract = generate_dma_contract();
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if (!contract)
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return NULL;
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contract->is_cyclic = 1;
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/* Figure out the endpoints and the address we need */
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if (vchan->is_dedicated) {
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io_mode = SUN4I_DDMA_ADDR_MODE_IO;
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linear_mode = SUN4I_DDMA_ADDR_MODE_LINEAR;
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ram_type = SUN4I_DDMA_DRQ_TYPE_SDRAM;
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} else {
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io_mode = SUN4I_NDMA_ADDR_MODE_IO;
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linear_mode = SUN4I_NDMA_ADDR_MODE_LINEAR;
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ram_type = SUN4I_NDMA_DRQ_TYPE_SDRAM;
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}
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if (dir == DMA_MEM_TO_DEV) {
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src = buf;
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dest = sconfig->dst_addr;
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endpoints = SUN4I_DMA_CFG_SRC_DRQ_TYPE(SUN4I_NDMA_DRQ_TYPE_SDRAM) |
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SUN4I_DMA_CFG_DST_DRQ_TYPE(vchan->endpoint) |
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SUN4I_DMA_CFG_DST_ADDR_MODE(SUN4I_NDMA_ADDR_MODE_IO);
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endpoints = SUN4I_DMA_CFG_DST_DRQ_TYPE(vchan->endpoint) |
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SUN4I_DMA_CFG_DST_ADDR_MODE(io_mode) |
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SUN4I_DMA_CFG_SRC_DRQ_TYPE(ram_type);
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} else {
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src = sconfig->src_addr;
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dest = buf;
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endpoints = SUN4I_DMA_CFG_SRC_DRQ_TYPE(vchan->endpoint) |
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SUN4I_DMA_CFG_SRC_ADDR_MODE(SUN4I_NDMA_ADDR_MODE_IO) |
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SUN4I_DMA_CFG_DST_DRQ_TYPE(SUN4I_NDMA_DRQ_TYPE_SDRAM);
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endpoints = SUN4I_DMA_CFG_DST_DRQ_TYPE(ram_type) |
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SUN4I_DMA_CFG_SRC_DRQ_TYPE(vchan->endpoint) |
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SUN4I_DMA_CFG_SRC_ADDR_MODE(io_mode);
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}
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/*
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@ -747,8 +745,13 @@ sun4i_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf, size_t len,
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dest = buf + offset;
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/* Make the promise */
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if (vchan->is_dedicated)
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promise = generate_ddma_promise(chan, src, dest,
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plength, sconfig);
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else
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promise = generate_ndma_promise(chan, src, dest,
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plength, sconfig, dir);
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if (!promise) {
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/* TODO: should we free everything? */
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return NULL;
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