Merge branches 'clk-imx6sx', 'clk-imx7d-enet' and 'clk-aspeed-24' into clk-next
* clk-imx6sx: clk: imx6sl: correct ocram_podf clock type clk: imx6sx: disable unnecessary clocks during clock initialization clk: imx6sx: add missing lvds2 clock to the clock tree * clk-imx7d-enet: ARM: dts: imx7: correct enet ipg clock clk: imx7d: correct enet clock CCGR registers clk: imx7d: correct enet phy ref clock gates * clk-aspeed-24: clk: aspeed: Add 24MHz fixed clock
This commit is contained in:
Stephen Boyd
Коммит
fff2e33717
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@ -120,7 +120,7 @@
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
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clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>,
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<&clks IMX7D_ENET_AXI_ROOT_CLK>,
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<&clks IMX7D_ENET2_TIME_ROOT_CLK>,
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<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
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@ -1091,7 +1091,7 @@
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
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clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
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<&clks IMX7D_ENET_AXI_ROOT_CLK>,
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<&clks IMX7D_ENET1_TIME_ROOT_CLK>,
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<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
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@ -14,7 +14,7 @@
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#include <dt-bindings/clock/aspeed-clock.h>
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#define ASPEED_NUM_CLKS 35
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#define ASPEED_NUM_CLKS 36
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#define ASPEED_RESET2_OFFSET 32
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@ -502,6 +502,13 @@ static int aspeed_clk_probe(struct platform_device *pdev)
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return PTR_ERR(hw);
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aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw;
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/* Fixed 24MHz clock */
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hw = clk_hw_register_fixed_rate(NULL, "fixed-24m", "clkin",
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0, 24000000);
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if (IS_ERR(hw))
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return PTR_ERR(hw);
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aspeed_clk_data->hws[ASPEED_CLK_24M] = hw;
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/*
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* TODO: There are a number of clocks that not included in this driver
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* as more information is required:
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@ -330,7 +330,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
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clks[IMX6SL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
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/* name parent_name reg shift width */
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clks[IMX6SL_CLK_OCRAM_PODF] = imx_clk_divider("ocram_podf", "ocram_sel", base + 0x14, 16, 3);
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clks[IMX6SL_CLK_OCRAM_PODF] = imx_clk_busy_divider("ocram_podf", "ocram_sel", base + 0x14, 16, 3, base + 0x48, 0);
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clks[IMX6SL_CLK_PERIPH_CLK2_PODF] = imx_clk_divider("periph_clk2_podf", "periph_clk2_sel", base + 0x14, 27, 3);
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clks[IMX6SL_CLK_PERIPH2_CLK2_PODF] = imx_clk_divider("periph2_clk2_podf", "periph2_clk2_sel", base + 0x14, 0, 3);
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clks[IMX6SL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
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@ -80,7 +80,7 @@ static const char *lvds_sels[] = {
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"arm", "pll1_sys", "dummy", "dummy", "dummy", "dummy", "dummy", "pll5_video_div",
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"dummy", "dummy", "pcie_ref_125m", "dummy", "usbphy1", "usbphy2",
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};
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static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", };
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static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", };
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static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
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static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
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static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
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@ -97,12 +97,7 @@ static int const clks_init_on[] __initconst = {
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IMX6SX_CLK_IPMUX1, IMX6SX_CLK_IPMUX2, IMX6SX_CLK_IPMUX3,
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IMX6SX_CLK_WAKEUP, IMX6SX_CLK_MMDC_P0_FAST, IMX6SX_CLK_MMDC_P0_IPG,
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IMX6SX_CLK_ROM, IMX6SX_CLK_ARM, IMX6SX_CLK_IPG, IMX6SX_CLK_OCRAM,
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IMX6SX_CLK_PER2_MAIN, IMX6SX_CLK_PERCLK, IMX6SX_CLK_M4,
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IMX6SX_CLK_QSPI1, IMX6SX_CLK_QSPI2, IMX6SX_CLK_UART_IPG,
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IMX6SX_CLK_UART_SERIAL, IMX6SX_CLK_I2C3, IMX6SX_CLK_ECSPI5,
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IMX6SX_CLK_CAN1_IPG, IMX6SX_CLK_CAN1_SERIAL, IMX6SX_CLK_CAN2_IPG,
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IMX6SX_CLK_CAN2_SERIAL, IMX6SX_CLK_CANFD, IMX6SX_CLK_EPIT1,
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IMX6SX_CLK_EPIT2,
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IMX6SX_CLK_PER2_MAIN, IMX6SX_CLK_PERCLK, IMX6SX_CLK_TZASC1,
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};
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static const struct clk_div_table clk_enet_ref_table[] = {
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@ -158,8 +153,9 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
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clks[IMX6SX_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0");
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clks[IMX6SX_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1");
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/* Clock source from external clock via CLK1 PAD */
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clks[IMX6SX_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0);
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/* Clock source from external clock via CLK1/2 PAD */
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clks[IMX6SX_CLK_ANACLK1] = of_clk_get_by_name(ccm_node, "anaclk1");
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clks[IMX6SX_CLK_ANACLK2] = of_clk_get_by_name(ccm_node, "anaclk2");
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop");
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base = of_iomap(np, 0);
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@ -228,7 +224,9 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
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clks[IMX6SX_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
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clks[IMX6SX_CLK_LVDS1_OUT] = imx_clk_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x160, 10, BIT(12));
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clks[IMX6SX_CLK_LVDS2_OUT] = imx_clk_gate_exclusive("lvds2_out", "lvds2_sel", base + 0x160, 11, BIT(13));
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clks[IMX6SX_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10));
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clks[IMX6SX_CLK_LVDS2_IN] = imx_clk_gate_exclusive("lvds2_in", "anaclk2", base + 0x160, 13, BIT(11));
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clks[IMX6SX_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
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base + 0xe0, 0, 2, 0, clk_enet_ref_table,
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@ -270,6 +268,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
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/* name reg shift width parent_names num_parents */
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clks[IMX6SX_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
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clks[IMX6SX_CLK_LVDS2_SEL] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
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np = ccm_node;
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base = of_iomap(np, 0);
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@ -26,6 +26,8 @@ static u32 share_count_sai1;
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static u32 share_count_sai2;
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static u32 share_count_sai3;
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static u32 share_count_nand;
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static u32 share_count_enet1;
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static u32 share_count_enet2;
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static const struct clk_div_table test_div_table[] = {
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{ .val = 3, .div = 1, },
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@ -738,7 +740,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
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clks[IMX7D_ENET1_TIME_ROOT_DIV] = imx_clk_divider2("enet1_time_post_div", "enet1_time_pre_div", base + 0xa780, 0, 6);
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clks[IMX7D_ENET2_REF_ROOT_DIV] = imx_clk_divider2("enet2_ref_post_div", "enet2_ref_pre_div", base + 0xa800, 0, 6);
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clks[IMX7D_ENET2_TIME_ROOT_DIV] = imx_clk_divider2("enet2_time_post_div", "enet2_time_pre_div", base + 0xa880, 0, 6);
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clks[IMX7D_ENET_PHY_REF_ROOT_DIV] = imx_clk_divider2("enet_phy_ref_post_div", "enet_phy_ref_pre_div", base + 0xa900, 0, 6);
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clks[IMX7D_ENET_PHY_REF_ROOT_CLK] = imx_clk_divider2("enet_phy_ref_root_clk", "enet_phy_ref_pre_div", base + 0xa900, 0, 6);
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clks[IMX7D_EIM_ROOT_DIV] = imx_clk_divider2("eim_post_div", "eim_pre_div", base + 0xa980, 0, 6);
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clks[IMX7D_NAND_ROOT_CLK] = imx_clk_divider2("nand_root_clk", "nand_pre_div", base + 0xaa00, 0, 6);
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clks[IMX7D_QSPI_ROOT_DIV] = imx_clk_divider2("qspi_post_div", "qspi_pre_div", base + 0xaa80, 0, 6);
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@ -805,6 +807,10 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
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clks[IMX7D_MIPI_DSI_ROOT_CLK] = imx_clk_gate4("mipi_dsi_root_clk", "mipi_dsi_post_div", base + 0x4650, 0);
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clks[IMX7D_MIPI_CSI_ROOT_CLK] = imx_clk_gate4("mipi_csi_root_clk", "mipi_csi_post_div", base + 0x4640, 0);
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clks[IMX7D_MIPI_DPHY_ROOT_CLK] = imx_clk_gate4("mipi_dphy_root_clk", "mipi_dphy_post_div", base + 0x4660, 0);
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clks[IMX7D_ENET1_IPG_ROOT_CLK] = imx_clk_gate2_shared2("enet1_ipg_root_clk", "enet_axi_post_div", base + 0x4700, 0, &share_count_enet1);
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clks[IMX7D_ENET1_TIME_ROOT_CLK] = imx_clk_gate2_shared2("enet1_time_root_clk", "enet1_time_post_div", base + 0x4700, 0, &share_count_enet1);
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clks[IMX7D_ENET2_IPG_ROOT_CLK] = imx_clk_gate2_shared2("enet2_ipg_root_clk", "enet_axi_post_div", base + 0x4710, 0, &share_count_enet2);
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clks[IMX7D_ENET2_TIME_ROOT_CLK] = imx_clk_gate2_shared2("enet2_time_root_clk", "enet2_time_post_div", base + 0x4710, 0, &share_count_enet2);
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clks[IMX7D_SAI1_ROOT_CLK] = imx_clk_gate2_shared2("sai1_root_clk", "sai1_post_div", base + 0x48c0, 0, &share_count_sai1);
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clks[IMX7D_SAI1_IPG_CLK] = imx_clk_gate2_shared2("sai1_ipg_clk", "ipg_root_clk", base + 0x48c0, 0, &share_count_sai1);
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clks[IMX7D_SAI2_ROOT_CLK] = imx_clk_gate2_shared2("sai2_root_clk", "sai2_post_div", base + 0x48d0, 0, &share_count_sai2);
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@ -812,11 +818,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
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clks[IMX7D_SAI3_ROOT_CLK] = imx_clk_gate2_shared2("sai3_root_clk", "sai3_post_div", base + 0x48e0, 0, &share_count_sai3);
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clks[IMX7D_SAI3_IPG_CLK] = imx_clk_gate2_shared2("sai3_ipg_clk", "ipg_root_clk", base + 0x48e0, 0, &share_count_sai3);
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clks[IMX7D_SPDIF_ROOT_CLK] = imx_clk_gate4("spdif_root_clk", "spdif_post_div", base + 0x44d0, 0);
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clks[IMX7D_ENET1_REF_ROOT_CLK] = imx_clk_gate4("enet1_ref_root_clk", "enet1_ref_post_div", base + 0x44e0, 0);
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clks[IMX7D_ENET1_TIME_ROOT_CLK] = imx_clk_gate4("enet1_time_root_clk", "enet1_time_post_div", base + 0x44f0, 0);
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clks[IMX7D_ENET2_REF_ROOT_CLK] = imx_clk_gate4("enet2_ref_root_clk", "enet2_ref_post_div", base + 0x4500, 0);
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clks[IMX7D_ENET2_TIME_ROOT_CLK] = imx_clk_gate4("enet2_time_root_clk", "enet2_time_post_div", base + 0x4510, 0);
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clks[IMX7D_ENET_PHY_REF_ROOT_CLK] = imx_clk_gate4("enet_phy_ref_root_clk", "enet_phy_ref_post_div", base + 0x4520, 0);
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clks[IMX7D_EIM_ROOT_CLK] = imx_clk_gate4("eim_root_clk", "eim_post_div", base + 0x4160, 0);
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clks[IMX7D_NAND_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_rawnand_clk", "nand_root_clk", base + 0x4140, 0, &share_count_nand);
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clks[IMX7D_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_root_clk", base + 0x4140, 0, &share_count_nand);
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@ -38,6 +38,7 @@
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#define ASPEED_CLK_MAC 32
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#define ASPEED_CLK_BCLK 33
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#define ASPEED_CLK_MPLL 34
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#define ASPEED_CLK_24M 35
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#define ASPEED_RESET_XDMA 0
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#define ASPEED_RESET_MCTP 1
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@ -275,6 +275,10 @@
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#define IMX6SX_PLL6_BYPASS 262
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#define IMX6SX_PLL7_BYPASS 263
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#define IMX6SX_CLK_SPDIF_GCLK 264
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#define IMX6SX_CLK_CLK_END 265
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#define IMX6SX_CLK_LVDS2_SEL 265
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#define IMX6SX_CLK_LVDS2_OUT 266
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#define IMX6SX_CLK_LVDS2_IN 267
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#define IMX6SX_CLK_ANACLK2 268
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#define IMX6SX_CLK_CLK_END 269
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#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
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@ -168,7 +168,7 @@
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#define IMX7D_SPDIF_ROOT_SRC 155
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#define IMX7D_SPDIF_ROOT_CG 156
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#define IMX7D_SPDIF_ROOT_DIV 157
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#define IMX7D_ENET1_REF_ROOT_CLK 158
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#define IMX7D_ENET1_IPG_ROOT_CLK 158
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#define IMX7D_ENET1_REF_ROOT_SRC 159
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#define IMX7D_ENET1_REF_ROOT_CG 160
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#define IMX7D_ENET1_REF_ROOT_DIV 161
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@ -176,7 +176,7 @@
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#define IMX7D_ENET1_TIME_ROOT_SRC 163
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#define IMX7D_ENET1_TIME_ROOT_CG 164
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#define IMX7D_ENET1_TIME_ROOT_DIV 165
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#define IMX7D_ENET2_REF_ROOT_CLK 166
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#define IMX7D_ENET2_IPG_ROOT_CLK 166
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#define IMX7D_ENET2_REF_ROOT_SRC 167
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#define IMX7D_ENET2_REF_ROOT_CG 168
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#define IMX7D_ENET2_REF_ROOT_DIV 169
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