ARM: clps711x: Switch CLPS711X subarch to use clk and clocksource driver
This patch removes old support for clk and clocksource support and switches platform to use new drivers. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Alexander Shiyan
Arnd Bergmann
Родитель
7d1311b93e
Коммит
fff74a935e
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@ -19,29 +19,17 @@
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/io.h>
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#include <linux/init.h>
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#include <linux/sizes.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/clk-provider.h>
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#include <linux/sched_clock.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <asm/system_misc.h>
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#include <mach/hardware.h>
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#include "common.h"
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static struct clk *clk_pll, *clk_bus, *clk_uart, *clk_timerl, *clk_timerh,
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*clk_tint, *clk_spi;
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/*
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* This maps the generic CLPS711x registers
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*/
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@ -64,129 +52,11 @@ void __init clps711x_init_irq(void)
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clps711x_intc_init(CLPS711X_PHYS_BASE, SZ_16K);
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}
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static u64 notrace clps711x_sched_clock_read(void)
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{
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return ~readw_relaxed(CLPS711X_VIRT_BASE + TC1D);
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}
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static void clps711x_clockevent_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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disable_irq(IRQ_TC2OI);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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enable_irq(IRQ_TC2OI);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* Not supported */
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_RESUME:
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/* Left event sources disabled, no more interrupts appear */
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break;
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}
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}
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static struct clock_event_device clockevent_clps711x = {
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.name = "clps711x-clockevent",
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.rating = 300,
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.features = CLOCK_EVT_FEAT_PERIODIC,
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.set_mode = clps711x_clockevent_set_mode,
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};
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static irqreturn_t clps711x_timer_interrupt(int irq, void *dev_id)
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{
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clockevent_clps711x.event_handler(&clockevent_clps711x);
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return IRQ_HANDLED;
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}
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static struct irqaction clps711x_timer_irq = {
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.name = "clps711x-timer",
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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.handler = clps711x_timer_interrupt,
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};
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static void add_fixed_clk(struct clk *clk, const char *name, int rate)
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{
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clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
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clk_register_clkdev(clk, name, NULL);
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}
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void __init clps711x_timer_init(void)
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{
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int osc, ext, pll, cpu, bus, timl, timh, uart, spi;
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u32 tmp;
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osc = 3686400;
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ext = 13000000;
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tmp = clps_readl(PLLR) >> 24;
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if (tmp)
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pll = (osc * tmp) / 2;
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else
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pll = 73728000; /* Default value */
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tmp = clps_readl(SYSFLG2);
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if (tmp & SYSFLG2_CKMODE) {
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cpu = ext;
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bus = cpu;
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spi = 135400;
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pll = 0;
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} else {
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cpu = pll;
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if (cpu >= 36864000)
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bus = cpu / 2;
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else
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bus = 36864000 / 2;
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spi = cpu / 576;
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}
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uart = bus / 10;
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if (tmp & SYSFLG2_CKMODE) {
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tmp = clps_readl(SYSCON2);
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if (tmp & SYSCON2_OSTB)
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timh = ext / 26;
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else
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timh = 541440;
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} else
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timh = DIV_ROUND_CLOSEST(cpu, 144);
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timl = DIV_ROUND_CLOSEST(timh, 256);
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/* All clocks are fixed */
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add_fixed_clk(clk_pll, "pll", pll);
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add_fixed_clk(clk_bus, "bus", bus);
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add_fixed_clk(clk_uart, "uart", uart);
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add_fixed_clk(clk_timerl, "timer_lf", timl);
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add_fixed_clk(clk_timerh, "timer_hf", timh);
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add_fixed_clk(clk_tint, "tint", 64);
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add_fixed_clk(clk_spi, "spi", spi);
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pr_info("CPU frequency set at %i Hz.\n", cpu);
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/* Start Timer1 in free running mode (Low frequency) */
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tmp = clps_readl(SYSCON1) & ~(SYSCON1_TC1S | SYSCON1_TC1M);
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clps_writel(tmp, SYSCON1);
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sched_clock_register(clps711x_sched_clock_read, 16, timl);
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clocksource_mmio_init(CLPS711X_VIRT_BASE + TC1D,
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"clps711x_clocksource", timl, 300, 16,
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clocksource_mmio_readw_down);
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/* Set Timer2 prescaler */
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clps_writew(DIV_ROUND_CLOSEST(timh, HZ), TC2D);
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/* Start Timer2 in prescale mode (High frequency)*/
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tmp = clps_readl(SYSCON1) | SYSCON1_TC2M | SYSCON1_TC2S;
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clps_writel(tmp, SYSCON1);
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clockevents_config_and_register(&clockevent_clps711x, timh, 0, 0);
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setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
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clps711x_clk_init(CLPS711X_VIRT_BASE);
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clps711x_clksrc_init(CLPS711X_VIRT_BASE + TC1D,
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CLPS711X_VIRT_BASE + TC2D, IRQ_TC2OI);
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}
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void clps711x_restart(enum reboot_mode mode, const char *cmd)
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@ -16,3 +16,8 @@ extern void clps711x_restart(enum reboot_mode mode, const char *cmd);
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/* drivers/irqchip/irq-clps711x.c */
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void clps711x_intc_init(phys_addr_t, resource_size_t);
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/* drivers/clk/clk-clps711x.c */
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void clps711x_clk_init(void __iomem *base);
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/* drivers/clocksource/clps711x-timer.c */
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void clps711x_clksrc_init(void __iomem *tc1_base, void __iomem *tc2_base,
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unsigned int irq);
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