Граф коммитов

39 Коммитов

Автор SHA1 Сообщение Дата
Vinod Koul 369dbadac1 dmengine: xilinx_dma: convert callback to helper function
Move the xilinx driver to new dmaengine callback

Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-08-08 08:11:43 +05:30
Arnd Bergmann e94570a36b dmaengine: zynqmp_dma: add missing MODULE_LICENSE
We get a warning about the missing MODULE_LICENSE tag for this newly
added driver module:

WARNING: modpost: missing MODULE_LICENSE() in drivers/dma/xilinx/zynqmp_dma.o
see include/linux/module.h for more information

This adds a "GPL" license, matching the "version 2 or later" information in
the comment at the start of the file.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-07-24 11:55:17 +05:30
Kedareswara rao Appana caf5ee94be dmaengine: zynqmp_dma: Fix static checker warning
This patch fixes the below static checker warning
drivers/dma/xilinx/zynqmp_dma.c:973 zynqmp_dma_chan_probe()
        warn: was && intended here instead of ||?

Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-07-24 11:19:22 +05:30
Arnd Bergmann 7cdd3587b8 dmaengine: zynqmp: avoid cast warning
The newly added zynqmp_dma driver produces a warning on 32-bit architectures
when dma_addr_t is 64-bit wide:

drivers/dma/xilinx/zynqmp_dma.c: In function 'zynqmp_dma_config_sg_ll_desc':
drivers/dma/xilinx/zynqmp_dma.c:321:9: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
        ((dma_addr_t)sdesc - (dma_addr_t)chan->desc_pool_v);
         ^
drivers/dma/xilinx/zynqmp_dma.c:321:29: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
        ((dma_addr_t)sdesc - (dma_addr_t)chan->desc_pool_v);

This changes the cast to the more appropriate uintptr_t.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-07-12 10:03:16 +05:30
Kedareswara rao Appana e598e6eb46 dmaengine: xilinx: Fix race condition in axi dma cyclic dma mode
In cyclic DMA mode need to link the tail bd segment
with the head bd segment to process bd's in cyclic.

Current driver is doing this only for tx channel
needs to update the same for rx channel case also.

This patch fixes the same.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-07-12 10:01:36 +05:30
Kedareswara rao Appana b0cc417c16 dmaengine: Add Xilinx zynqmp dma engine driver support
Added the driver for zynqmp dma engine used in Zynq
UltraScale+ MPSoC. This dma controller supports memory to memory
and I/O to I/O buffer transfers.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-07-08 11:25:34 +05:30
Kedareswara rao Appana e131f1ba6f dmaengine: xilinx: Use different channel names for each dma
Current driver assumes that child node channel name is either
"xlnx,axi-vdma-mm2s-channel" or "xlnx,axi-vdma-s2mm-channel"
which is confusing the users of AXI DMA and CDMA.
This patch fixes this issue by using different channel
names for the AXI DMA and AXI CDMA child nodes.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-07-08 10:51:49 +05:30
Kedareswara rao Appana fde57a7c44 dmaengine: xilinx: Rename driver and config
In the existing vdma driver support for
AXI DMA and CDMA got added so the driver is no
longer VDMA specific.

This patch renames the driver and DT binding doc to xilinx_dma
and updates the Kconfig description for all the DMAS.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-07-08 10:51:35 +05:30
Kedareswara rao Appana 1a9e7a03c7 dmaengine: vdma: Add support for mulit-channel dma mode
This patch adds support for AXI DMA multi-channel dma mode
Multichannel mode enables DMA to connect to multiple masters
and slaves on the streaming side.

In Multichannel mode AXI DMA supports 2D transfers.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-07-08 10:50:38 +05:30
Kedareswara rao Appana 9791e71a06 dmaengine: vdma: Add 64 bit addressing support for the axi cdma
The AXI CDMA is a soft ip, which can be programmed to support
32 bit addressing or greater than 32 bit addressing.

When the AXI CDMA ip is configured for 32 bit address space
in simple dma mode the source/destination buffer address is
specified by a single register(18h for Source buffer address and
20h for Destination buffer address). When configured in SG mode
the current descriptor and tail descriptor are specified by a
Single register(08h for curdesc 10h for tail desc).

When the  AXI CDMA core is configured for an address space greater
than 32 then each buffer address or descriptor address is specified by
a combination of two registers.

The first register specifies the LSB 32 bits of address,
while the next register specifies the MSB 32 bits of address.

For example, 08h will specify the LSB 32 bits while 0Ch will
specify the MSB 32 bits of the first start address.
So we need to program two registers at a time.

This patch adds the 64 bit addressing support to the axicdma
IP in the driver.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-06-21 11:05:23 +05:30
Kedareswara rao Appana f0cba685ca dmaengine: vdma: Add 64 bit addressing support for the axi dma
The AXI DMA is a soft ip, which can be programmed to support
32 bit addressing or greater than 32 bit addressing.

When the AXI DMA ip is configured for 32 bit address space
in simple dma mode the buffer address is specified by a single register
(18h for MM2S channel and 48h for S2MM channel). When configured in SG mode
The current descriptor and tail descriptor are specified by a single
Register(08h for curdesc 10h for tail desc for MM2S channel and 38h for
Curdesc and 40h for tail desc for S2MM).

When the  AXI DMA core is configured for an address space greater
than 32 then each buffer address or descriptor address is specified by
a combination of two registers.

The first register specifies the LSB 32 bits of address,
while the next register specifies the MSB 32 bits of address.

For example, 48h will specify the LSB 32 bits while 4Ch will
specify the MSB 32 bits of the first start address.
So we need to program two registers at a time.

This patch adds the 64 bit addressing support for the axidma
IP in the driver.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-06-21 11:05:23 +05:30
Arnd Bergmann f67c3bdabb dmaengine: xilinx-vdma: add some sanity checks
The newly added xilinx_dma_prep_dma_cyclic function sometimes causes
a gcc warning about the use of the segment function in case
we never run into the inner loop of the function:

dma/xilinx/xilinx_vdma.c: In function 'xilinx_dma_prep_dma_cyclic':
dma/xilinx/xilinx_vdma.c:1808:23: error: 'segment' may be used uninitialized in this function [-Werror=maybe-uninitialized]
   segment->hw.control |= XILINX_DMA_BD_SOP;

This can only happen if the period len is zero (which would cause other
problems earlier), or if the buffer is shorter than a period. Neither
of them should ever happen, but by adding an explicit check for these two
cases, we can abort in a more controlled way, and the compiler is
able to see that we never use uninitialized data.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-06-13 22:31:42 +05:30
Kedareswara rao Appana e167a0b6dc dmaengine: vdma: Fix compilation warning in cyclic dma mode
This patch fixes the below compilation warining.
drivers/dma/xilinx/xilinx_vdma.c: In function 'xilinx_dma_prep_dma_cyclic':
drivers/dma/xilinx/xilinx_vdma.c:1808:23: warning: 'segment' may be used
uninitialized in this function [-Wmaybe-uninitialized]
   segment->hw.control |= XILINX_DMA_BD_SOP;

The start of packet (SOP) should be set to the first segment in the desc
chain not for the last segment of the desc chain.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-06-13 11:11:17 +05:30
Kedareswara rao Appana 6214786651 dmaengine: vdma: Use dma_pool_zalloc
dma_pool_zalloc combines dma_pool_alloc and memset 0
this patch updates the driver to use dma_pool_zalloc.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-06-07 11:48:24 +05:30
Kedareswara rao Appana 92d794dfb6 dmaengine: vdma: Add support for cyclic dma mode
This patch adds support for AXI DMA cyclic dma mode.
In cyclic mode, DMA fetches and processes the same
BDs without interruption. The DMA continues to fetch and process
until it is stopped or reset.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-06-07 11:48:24 +05:30
Linus Torvalds a0d3c7c5c0 dmaengine updates for 4.7
This time round the update brings in following changes:
 
  - New tegra driver for ADMA device
  - Support for Xilinx AXI Direct Memory Access Engine and Xilinx AXI Central
    Direct Memory Access Engine and few updates to this driver.
  - New cyclic capability to sun6i and few updates.
  - Slave-sg support in bcm2835.
  - Updates to many drivers like designware, hsu, mv_xor, pxa, edma,
    qcom_hidma & bam.
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Merge tag 'dmaengine-4.7-rc1' of git://git.infradead.org/users/vkoul/slave-dma

Pull dmaengine updates from Vinod Koul:
 "This time round the update brings in following changes:

   - new tegra driver for ADMA device

   - support for Xilinx AXI Direct Memory Access Engine and Xilinx AXI
     Central Direct Memory Access Engine and few updates to this driver

   - new cyclic capability to sun6i and few updates

   - slave-sg support in bcm2835

   - updates to many drivers like designware, hsu, mv_xor, pxa, edma,
     qcom_hidma & bam"

* tag 'dmaengine-4.7-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (84 commits)
  dmaengine: ioatdma: disable relaxed ordering for ioatdma
  dmaengine: of_dma: approximate an average distribution
  dmaengine: core: Use IS_ENABLED() instead of checking for built-in or module
  dmaengine: edma: Re-evaluate errors when ccerr is triggered w/o error event
  dmaengine: qcom_hidma: add support for object hierarchy
  dmaengine: qcom_hidma: add debugfs hooks
  dmaengine: qcom_hidma: implement lower level hardware interface
  dmaengine: vdma: Add clock support
  Documentation: DT: vdma: Add clock support for dmas
  dmaengine: vdma: Add config structure to differentiate dmas
  MAINTAINERS: Update Tegra DMA maintainers
  dmaengine: tegra-adma: Add support for Tegra210 ADMA
  Documentation: DT: Add binding documentation for NVIDIA ADMA
  dmaengine: vdma: Add Support for Xilinx AXI Central Direct Memory Access Engine
  Documentation: DT: vdma: update binding doc for AXI CDMA
  dmaengine: vdma: Add Support for Xilinx AXI Direct Memory Access Engine
  Documentation: DT: vdma: update binding doc for AXI DMA
  dmaengine: vdma: Rename xilinx_vdma_ prefix to xilinx_dma
  dmaengine: slave means at least one of DMA_SLAVE, DMA_CYCLIC
  dmaengine: mv_xor: Allow selecting mv_xor for mvebu only compatible SoC
  ...
2016-05-19 11:47:18 -07:00
Kedareswara rao Appana ba16db36b5 dmaengine: vdma: Add clock support
Added basic clock support for axi dma's.
The clocks are requested at probe and released at remove.

Reviewed-by: Shubhrajyoti Datta <shubhraj@xilinx.com>
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-13 15:00:18 +05:30
Kedareswara rao Appana fb2366675e dmaengine: vdma: Add config structure to differentiate dmas
This patch adds config structure in the driver to differentiate
AXI DMA's and to add more features(clock support etc..) to these DMA's.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-13 15:00:18 +05:30
Kedareswara rao Appana 07b0e7d49c dmaengine: vdma: Add Support for Xilinx AXI Central Direct Memory Access Engine
This patch adds support for the AXI Central Direct Memory Access
(AXI CDMA) core to the existing vdma driver, AXI CDMA is a
soft Xilinx IP core that provides high-bandwidth
Direct Memory Access(DMA) between a memory-mapped
source address and a memory-mapped destination address.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-12 11:58:58 +05:30
Kedareswara rao Appana c0bba3a99f dmaengine: vdma: Add Support for Xilinx AXI Direct Memory Access Engine
This patch adds support for the AXI Direct Memory Access (AXI DMA)
core in the existing vdma driver, AXI DMA Core is a
soft Xilinx IP core that provides high-bandwidth
direct memory access between memory and AXI4-Stream
type target peripherals.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-12 11:58:30 +05:30
Kedareswara rao Appana 42c1a2ede4 dmaengine: vdma: Rename xilinx_vdma_ prefix to xilinx_dma
This patch renames the xilinx_vdma_ prefix to xilinx_dma
for the API's and masks that will be shared b/w three DMA
IP cores.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-12 11:58:30 +05:30
Julia Lawall 2ba4f8abfe dmaengine: vdma: Use dma_pool_zalloc
Dma_pool_zalloc combines dma_pool_alloc and memset 0.  The semantic patch
that makes this transformation is as follows: (http://coccinelle.lip6.fr/)

// <smpl>
@@
expression d,e;
statement S;
@@

        d =
-            dma_pool_alloc
+            dma_pool_zalloc
             (...);
        if (!d) S
-       memset(d, 0, sizeof(*d));
// </smpl>

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-03 12:24:11 +05:30
Kedareswara rao Appana 48a59edc63 dmaengine: vdma: Fix checkpatch.pl warnings
This patch fixes the below checkpatch.pl warnings.

WARNING: void function return statements are not generally useful
+	return;
+}

WARNING: void function return statements are not generally useful
+	return;
+}

WARNING: Missing a blank line after declarations
+		u32 errors = status & XILINX_VDMA_DMASR_ALL_ERR_MASK;
+		vdma_ctrl_write(chan, XILINX_VDMA_REG_DMASR,

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Moritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-04-06 08:41:17 -07:00
Kedareswara rao Appana a65cf5125b dmaengine: vdma: Fix race condition in Non-SG mode
When VDMA is configured in  Non-sg mode
Users can queue descriptors greater than h/w configured frames.

Current driver allows the user to queue descriptors upto h/w configured.
Which is wrong for non-sg mode configuration.

This patch fixes this issue.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-04-06 08:41:15 -07:00
Kedareswara rao Appana b72db4005f dmaengine: vdma: Add 64 bit addressing support to the driver
This VDMA  is a soft ip, which can be programmed to support
32 bit addressing or greater than 32 bit addressing.

When the VDMA ip is configured for 32 bit address space
the buffer address is specified by a single register
(0x5C for MM2S and 0xAC for S2MM channel).

When the  VDMA core is configured for an address space greater
than 32 then each buffer address is specified by a combination of
two registers.

The first register specifies the LSB 32 bits of address,
while the next register specifies the MSB 32 bits of address.

For example, 5Ch will specify the LSB 32 bits while 60h will
specify the MSB 32 bits of the first start address.
So we need to program two registers at a time.

This patch adds the 64 bit addressing support to the vdma driver.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-04-06 08:41:14 -07:00
Franck Jullien 330ed4da2c dmaengine: vdma: don't crash when bad channel is requested
When client request a non existing channel from of_dma_xilinx_xlate
we get a NULL pointer dereferencing. This patch fix this problem.

Signed-off-by: Franck Jullien <franck.jullien@odyssee-systemes.fr>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-04-05 11:10:57 -07:00
Kedareswara rao Appana 694906348d dmaengine: xilinx_vdma: Remove unnecessary variable initializations
This patch removes the unnecessary variable initializations
in the driver.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-03-04 20:33:13 +05:30
Kedareswara rao Appana 9495f26482 dmaengine: xilinx_vdma: Use readl_poll_timeout instead of do while loop's
It is sometimes necessary to poll a memory-mapped register until its
value satisfies some condition use convenience macros
that do this instead of do while loop's.

This patch updates the same in the driver.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-03-03 21:02:38 +05:30
Kedareswara rao Appana 26c5e36931 dmaengine: xilinx_vdma: Simplify spin lock handling
This patch simplifies the spin lock handling in the driver
by moving locking out of xilinx_dma_start_transfer() API
and xilinx_dma_update_completed_cookie() API.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-03-03 21:02:38 +05:30
Kedareswara rao Appana e2b538a77d dmaengine: xilinx_vdma: Fix issues with non-parking mode
This patch fixes issues with the Non-parking mode(Cirular mode).
With the  existing driver in cirular mode if we submit frames less than h/w
configured we simply end-up having misconfigured vdma h/w.
This patch fixes this issue by configuring the frame count register.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-03-03 21:02:38 +05:30
Kedareswara rao Appana 7096f36e53 dmaengine: xilinx_vdma: Improve SG engine handling
The current driver allows user to queue up multiple segments
on to a single transaction descriptor. User will submit this single desc
and in the issue_pending() we decode multiple segments and submit to SG HW engine.
We free up the allocated_desc when it is submitted to the HW.

Existing code prevents the user to prepare multiple trasactions at same time as
we are overwrite with the allocated_desc.

The best utilization of HW SG engine would happen if we collate the pending
list when we start dma this patch updates the same.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-03-03 21:02:38 +05:30
Luis de Bethencourt ad577e4642 dmaengine: xilinx: Fix module autoload for OF platform driver
This platform driver has a OF device ID table but the OF module
alias information is not created so module autoloading won't work.

Signed-off-by: Luis de Bethencourt <luisbg@osg.samsung.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Moritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-01 07:35:39 +05:30
Kedareswara rao Appana 937abe88ae dmaengine: xilinx-dma: move header file to common location
This patch moves the xilinx_dma.h header file
to the include/linux/dma.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-03-17 16:23:21 +05:30
Maxime Ripard ba7140462f dmaengine: xilinx: Split device_control
Split the device_control callback of the Xilinx VDMA driver to make use of the
newly introduced callbacks, that will eventually be used to retrieve slave
capabilities.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-12-22 12:33:21 +05:30
Srikanth Thokala 6d80f45f50 dmaengine: xilinx: vdma: icg should be difference of stride and hsize
This patch modifies the icg field to match the description
as mentioned in the DMA Linux framework.

Signed-off-by: Srikanth Thokala <sthokal@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-11-06 13:11:47 +05:30
Srikanth Thokala a5e48e243b dmaengine: xilinx: vdma: Allow only one chunk in a line
This patch adds a sanity check to see if frame_size is 1.

Signed-off-by: Srikanth Thokala <sthokal@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-11-06 13:11:47 +05:30
Srikanth Thokala 049c0d577d dmaengine: xilinx: vdma: Check if the segment list is empty in a descriptor
The segment list in a descriptor should be checked for empty, else
it will try to access invalid address for the first call.  This
patch fixes this issue.

Signed-off-by: Srikanth Thokala <sthokal@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-11-06 13:11:47 +05:30
Michal Simek 29a4bb1431 dma: xilinx: Remove .owner field for driver
There is no need to init .owner field.

Based on the patch from Peter Griffin <peter.griffin@linaro.org>
"mmc: remove .owner field for drivers using module_platform_driver"

This patch removes the superflous .owner field for drivers which
use the module_platform_driver API, as this is overriden in
platform_driver_register anyway."

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Levente Kurusa <lkurusa@redhat.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-08-19 22:36:50 +05:30
Srikanth Thokala 9cd4360de6 dma: Add Xilinx AXI Video Direct Memory Access Engine driver support
This is the driver for the AXI Video Direct Memory Access (AXI
VDMA) core, which is a soft Xilinx IP core that provides high-
bandwidth direct memory access between memory and AXI4-Stream
type video target peripherals. The core provides efficient two
dimensional DMA operations with independent asynchronous read
and write channel operation.

This module works on Zynq (ARM Based SoC) and Microblaze platforms.

Signed-off-by: Srikanth Thokala <sthokal@xilinx.com>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Reviewed-by: Levente Kurusa <levex@linux.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-04-30 10:44:13 +05:30