Граф коммитов

5233 Коммитов

Автор SHA1 Сообщение Дата
Lad Prabhakar c4c4637eb5 pinctrl: renesas: Add RZ/G2L pin and gpio controller driver
Add support for pin and gpio controller driver for RZ/G2L SoC.

Based on a patch in the BSP by Hien Huynh <hien.huynh.px@renesas.com>.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210727112328.18809-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-08-13 12:09:04 +02:00
Sam Protsenko cdd3d945dc pinctrl: samsung: Add Exynos850 SoC specific data
Add Samsung Exynos850 SoC specific data to enable pinctrl support for
all platforms based on Exynos850.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20210811114827.27322-3-semen.protsenko@linaro.org
[krzysztof: lower-case the hex-numbers]
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-08-13 09:39:42 +02:00
Marc Zyngier a9cb09b7be pinctrl: Bulk conversion to generic_handle_domain_irq()
Wherever possible, replace constructs that match either
generic_handle_irq(irq_find_mapping()) or
generic_handle_irq(irq_linear_revmap()) to a single call to
generic_handle_domain_irq().

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
2021-08-12 11:39:39 +01:00
Mario Limonciello c4b68e5139 pinctrl: amd: Fix an issue with shutdown when system set to s0ix
IRQs are getting armed on shutdown causing the system to immediately
wake back up.

Link: https://lkml.org/lkml/2021/8/2/1114
Reported-by: nix.or.die@googlemail.com
Acked-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Tested-by: Gabriel Craciunescu <nix.or.die@gmail.com>
CC: Raul E Rangel <rrangel@chromium.org>
Fixes: d62bd5ce12 ("pinctrl: amd: Implement irq_set_wake")
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Link: https://lore.kernel.org/r/20210809201513.12367-1-mario.limonciello@amd.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-12 11:16:40 +02:00
Lakshmi Sowjanya D ffd4e73935 pinctrl: Add Intel Keem Bay pinctrl driver
About Intel Keem Bay:
-------------------
Intel Keem Bay is a computer vision AI accelerator SoC based on ARM CPU.
Documentation of Keem Bay: Documentation/vpu/vpu-stack-overview.rst.

Pinctrl IP:
----------
The SoC has a customised pinmux controller IP which controls pin
multiplexing and configuration.

Keem Bay pinctrl IP is not based on and have nothing in common with the
existing pinctrl drivers. The registers used are incompatible with the
existing drivers, so it requires a new driver.

Add pinctrl driver to enable pin control support in the Intel Keem Bay SoC.

Co-developed-by: Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
Signed-off-by: Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
Co-developed-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
Signed-off-by: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
Reviewed-by: Mark Gross <mgross@linux.intel.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20210806142527.29113-3-lakshmi.sowjanya.d@intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-11 15:13:14 +02:00
Linus Walleij 86e5fbcaf7 intel-pinctrl for v5.14-2
* Fix the software mapping of GPIOs on Intel Tiger Lake-H
 
 The following is an automated git shortlog grouped by driver:
 
 tigerlake:
  -  Fix GPIO mapping for newer version of software
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Merge tag 'intel-pinctrl-v5.14-2' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into fixes

intel-pinctrl for v5.14-2

* Fix the software mapping of GPIOs on Intel Tiger Lake-H

The following is an automated git shortlog grouped by driver:

tigerlake:
 -  Fix GPIO mapping for newer version of software
2021-08-11 15:10:32 +02:00
Yang Yingliang 3fb5c90452 pinctrl: zynqmp: Drop pinctrl_unregister for devm_ registered device
It's not necessary to unregister pin controller device registered
with devm_pinctrl_register() and using pinctrl_unregister() leads
to a double free.

Fixes: fa99e70138 ("pinctrl: zynqmp: some code cleanups")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210729071905.3235953-1-yangyingliang@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-11 15:09:22 +02:00
Damien Le Moal 31697ef7f3 pinctrl: k210: Fix k210_fpioa_probe()
In k210_fpioa_probe(), add missing calls to clk_disable_unprepare() in
case of error after cenabling the clk and pclk clocks. Also add missing
error handling when enabling pclk.

Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Fixes: d4c34d09ab ("pinctrl: Add RISC-V Canaan Kendryte K210 FPIOA driver")
Cc: <stable@vger.kernel.org>
Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
Link: https://lore.kernel.org/r/20210806004311.52859-1-damien.lemoal@wdc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-11 15:03:53 +02:00
Paul Cercueil 6626a76ef8 pinctrl: ingenic: Add .max_register in regmap_config
Compute the max register from the GPIO chip offset and number of GPIO
chips.

This permits to read all registers from debugfs.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com>
Link: https://lore.kernel.org/r/20210717174836.14776-3-paul@crapouillou.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-11 10:24:06 +02:00
Paul Cercueil 7261851e93 pinctrl: ingenic: Fix bias config for X2000(E)
The ingenic_set_bias() function's "bias" argument is not a
"enum pin_config_param", so its value should not be compared against
values of that enum.

This should fix the bias config not working on the X2000(E) SoCs.

Fixes: 943e0da153 ("pinctrl: Ingenic: Add pinctrl driver for X2000.")
Cc: <stable@vger.kernel.org> # v5.12
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com>
Link: https://lore.kernel.org/r/20210717174836.14776-2-paul@crapouillou.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-11 10:24:06 +02:00
Paul Cercueil d5e9314039 pinctrl: ingenic: Fix incorrect pull up/down info
Fix the pull up/down info for both the JZ4760 and JZ4770 SoCs, as the
previous values sometimes contradicted what's written in the programming
manual.

Fixes: b5c23aa465 ("pinctrl: add a pinctrl driver for the Ingenic jz47xx SoCs")
Cc: <stable@vger.kernel.org> # v4.12
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com>
Link: https://lore.kernel.org/r/20210717174836.14776-1-paul@crapouillou.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-11 10:24:06 +02:00
周琰杰 (Zhou Yanjie) 2a18211b8c pinctrl: Ingenic: Add pinctrl driver for X2100.
Add support for probing the pinctrl-ingenic driver on the
X2100 SoC from Ingenic.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Link: https://lore.kernel.org/r/1627108604-91304-5-git-send-email-zhouyanjie@wanyeetech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-11 10:22:18 +02:00
周琰杰 (Zhou Yanjie) b638e0f18d pinctrl: Ingenic: Add SSI pins support for JZ4755 and JZ4760.
Add SSI pins support for the JZ4755 SoC and the
JZ4760 SoC from Ingenic.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Link: https://lore.kernel.org/r/1627108604-91304-3-git-send-email-zhouyanjie@wanyeetech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-11 10:22:17 +02:00
周琰杰 (Zhou Yanjie) 28c1caaf49 pinctrl: Ingenic: Improve the code.
1.Rename the original "dmicx" ABIs to "dmic-ifx", since these devices
  have only one DMIC module which has multiple input interfaces. The
  original naming is easy to make users mistakenly think that the
  device has multiple dmic modules. Currently, in the mainline, no
  other devicetree out there is using the "sfc" ABI, so we should be
  able to replace it safely.
2.Rename the original "ssix-ce0" ABIs to "ssix-ce", since the X2000
  have only one ce pin. The original naming is easy to make users
  mistakenly think that the device has multiple ce pins. Currently,
  in the mainline, no other devicetree out there is using the
  "ssix-ce0" ABIs, so we should be able to replace it safely.
3.Split the original "sfc" ABI into "sfc-data", "sfc-ce", "sfc-clk"
  to increase the flexibility when configuring the pins. Currently,
  in the mainline, no other devicetree out there is using the "sfc"
  ABI, so we should be able to replace it safely.
4.There is more than one compatible string in the match table, so
  renaming "ingenic_xxxx_of_match[]" to "ingenic_xxxx_of_matches"
  is more reasonable, and remove the unnecessary commas in
  "ingenic_gpio_of_matches[]" to reduce code size as much as possible.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Link: https://lore.kernel.org/r/1627108604-91304-2-git-send-email-zhouyanjie@wanyeetech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-11 10:22:17 +02:00
Randy Dunlap 5fa9d19b3f pinctrl: aspeed: placate kernel-doc warnings
Eliminate kernel-doc warnings in drivers/pinctrl/aspeed by using
proper kernel-doc notation.

Fixes these kernel-doc warnings:

drivers/pinctrl/aspeed/pinmux-aspeed.c:61: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
    * Query the enabled or disabled state for a mux function's signal on a pin
drivers/pinctrl/aspeed/pinctrl-aspeed.c:135: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
    * Search for the signal expression needed to enable the pin's signal for the

Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Reported-by: kernel test robot <lkp@intel.com>
Cc: Aditya Srivastava <yashsri421@gmail.com>
Cc: Andrew Jeffery <andrew@aj.id.au>
Cc: linux-aspeed@lists.ozlabs.org
Cc: openbmc@lists.ozlabs.org
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20210723034840.8752-1-rdunlap@infradead.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-10 15:29:44 +02:00
Andre Przywara d1dee81416 pinctrl: sunxi: Don't underestimate number of functions
When we are building all the various pinctrl structures for the
Allwinner pinctrl devices, we do some estimation about the maximum
number of distinct function (names) that we will need.

So far we take the number of pins as an upper bound, even though we
can actually have up to four special functions per pin. This wasn't a
problem until now, since we indeed have typically far more pins than
functions, and most pins share common functions.

However the H616 "-r" pin controller has only two pins, but four
functions, so we run over the end of the array when we are looking for
a matching function name in sunxi_pinctrl_add_function - there is no
NULL sentinel left that would terminate the loop:

[    8.200648] Unable to handle kernel paging request at virtual address fffdff7efbefaff5
[    8.209179] Mem abort info:
....
[    8.368456] Call trace:
[    8.370925]  __pi_strcmp+0x90/0xf0
[    8.374559]  sun50i_h616_r_pinctrl_probe+0x1c/0x28
[    8.379557]  platform_probe+0x68/0xd8

Do an actual worst case allocation (4 functions per pin, three common
functions and the sentinel) for the initial array allocation. This is
now heavily overestimating the number of functions in the common case,
but we will reallocate this array later with the actual number of
functions, so it's only temporarily.

Fixes: 561c1cf17c ("pinctrl: sunxi: Add support for the Allwinner H616-R pin controller")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20210722132548.22121-1-andre.przywara@arm.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-10 14:55:35 +02:00
Marc Zyngier 1b73e588f4 pinctrl: stmfx: Fix hazardous u8[] to unsigned long cast
Casting a small array of u8 to an unsigned long is *never* OK:

- it does funny thing when the array size is less than that of a long,
  as it accesses random places in the stack
- it makes everything even more fun with a BE kernel

Fix this by building the unsigned long used as a bitmap byte by byte,
in a way that works across endianess and has no undefined behaviours.

An extra BUILD_BUG_ON() catches the unlikely case where the array
would be larger than a single unsigned long.

Fixes: 1490d9f841 ("pinctrl: Add STMFX GPIO expander Pinctrl/GPIO driver")
Signed-off-by: Marc Zyngier <maz@kernel.org>
Cc: stable@vger.kernel.org
Cc: Amelie Delaunay <amelie.delaunay@foss.st.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Link: https://lore.kernel.org/r/20210725180830.250218-1-maz@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-10 14:47:59 +02:00
Alexandre Torgue a022135a19 pinctrl: stm32: Add STM32MP135 SoC support
STM32MP135 SoC embeds 9 GPIO banks of 16 gpios each. Those GPIO
banks contain same features as STM32MP157 GPIO banks except that
each GPIO line of the STM32MP135 can be secured.

Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Acked-by: Arnd Bergmann <arnd@arndb.de
Link: https://lore.kernel.org/r/20210723132810.25728-3-alexandre.torgue@foss.st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-10 14:45:27 +02:00
Zhen Lei 2ac48d0d48 pinctrl: single: Move test PCS_HAS_PINCONF in pcs_parse_bits_in_pinctrl_entry() to the beginning
The value of pcs->flags is not overwritten in function
pcs_parse_bits_in_pinctrl_entry() and its subfunctions, so moving this
check to the beginning of the function eliminates unnecessary rollback
operations.

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20210722033930.4034-3-thunder.leizhen@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-10 14:42:56 +02:00
Zhen Lei d789a490d3 pinctrl: single: Fix error return code in pcs_parse_bits_in_pinctrl_entry()
Fix to return -ENOTSUPP instead of 0 when PCS_HAS_PINCONF is true, which
is the same as that returned in pcs_parse_pinconf().

Fixes: 4e7e8017a8 ("pinctrl: pinctrl-single: enhance to configure multiple pins of different modules")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Link: https://lore.kernel.org/r/20210722033930.4034-2-thunder.leizhen@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-10 14:42:55 +02:00
Bjorn Andersson 182700f258 pinctrl: qcom: spmi-gpio: Add pmc8180 & pmc8180c
The SC8180x platform comes with PMC8180 and PMC8180c, add support for
the GPIO controller in these PMICs.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210629003851.1787673-1-bjorn.andersson@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-10 14:37:36 +02:00
Andy Shevchenko 2f658f7a39 pinctrl: tigerlake: Fix GPIO mapping for newer version of software
The software mapping for GPIO, which initially comes from Microsoft,
is subject to change by respective Windows and firmware developers.
Due to the above the driver had been written and published way ahead
of the schedule, and thus the numbering schema used in it is outdated.

Fix the numbering schema in accordance with the real products on market.

Fixes: 653d96455e ("pinctrl: tigerlake: Add support for Tiger Lake-H")
Reported-and-tested-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
Reported-by: Riccardo Mori <patacca@autistici.org>
Reported-and-tested-by: Lovesh <lovesh.bond@gmail.com>
BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=213463
BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=213579
BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=213857
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2021-08-04 18:47:50 +03:00
Jaehyoung Choi 70115558ab pinctrl: samsung: Fix pinctrl bank pin count
Commit 1abd18d1a5 ("pinctrl: samsung: Register pinctrl before GPIO")
changes the order of GPIO and pinctrl registration: now pinctrl is
registered before GPIO. That means gpio_chip->ngpio is not set when
samsung_pinctrl_register() called, and one cannot rely on that value
anymore. Use `pin_bank->nr_pins' instead of `pin_bank->gpio_chip.ngpio'
to fix mentioned inconsistency.

Fixes: 1abd18d1a5 ("pinctrl: samsung: Register pinctrl before GPIO")
Signed-off-by: Jaehyoung Choi <jkkkkk.choi@samsung.com>
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20210730192905.7173-1-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-08-02 15:22:18 +02:00
Iskren Chernev 4b77f1dff5 drivers: qcom: pinctrl: Add pinctrl driver for sm6115
Based on CAF implementation with egpio/wake_reg support removed.

Similar function names were merged to reduce total number of functions.

Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210723192352.546902-3-iskren.chernev@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-31 23:23:06 +02:00
Linus Walleij d7eb35beda pinctrl: renesas: Updates for v5.15
- Add bias support for the R-Car D3 SoC,
   - Miscellaneous fixes and improvements.
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Merge tag 'renesas-pinctrl-for-v5.15-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: renesas: Updates for v5.15

  - Add bias support for the R-Car D3 SoC,
  - Miscellaneous fixes and improvements.
2021-07-30 16:11:37 +02:00
Sai Krishna Potthuri cdd5732554 pinctrl: pinctrl-zynq: Add support for 'power-source' parameter
Add support for generic pin parameter 'power-source'.
To maintain the backward compatibility, 'io-standard' parameter is still
supported in the driver.

Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Link: https://lore.kernel.org/r/1626868353-96475-4-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-30 14:40:42 +02:00
Jiaxun Yang 6ceb3c6406 pinctrl: pistachio: Make it as an option
So it will be avilable for generic MIPS kernel.

--

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
v3: Depend on OF as well
Link: https://lore.kernel.org/r/20210721030134.10562-7-jiaxun.yang@flygoat.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-30 14:37:36 +02:00
Fabio Estevam 2fefcf2400 pinctrl: imx8dxl: Constify imx_pinctrl_soc_info
The imx_pinctrl_soc_info structure content is never changed, so it can be
declared as 'const', like it is done on all other i.MX pinctrl drivers.

Make it 'const' in this driver too.

Reported-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Link: https://lore.kernel.org/r/20210716131341.3370620-1-festevam@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-30 12:06:02 +02:00
Fabio Estevam b013dc8a02 pinctrl: imx8qxp: Constify imx_pinctrl_soc_info
The imx_pinctrl_soc_info structure content is never changed, so it can be
declared as 'const', like it is done on all other i.MX pinctrl drivers.

Make it 'const' in this driver too.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Link: https://lore.kernel.org/r/20210713122513.3112941-2-festevam@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-30 12:03:47 +02:00
Fabio Estevam ff128cdb7f pinctrl: imx8mn: Constify imx_pinctrl_soc_info
The imx_pinctrl_soc_info structure content is never changed, so it can be
declared as 'const', like it is done on all other i.MX pinctrl drivers.

Make it 'const' in this driver too.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Link: https://lore.kernel.org/r/20210713122513.3112941-1-festevam@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-30 12:03:47 +02:00
Geert Uytterhoeven 91d1be9fb7 pinctrl: renesas: Fix pin control matching on R-Car H3e-2G
As R-Car H3 ES1.x (R8A77950) and R-Car ES2.0+ (R8A77951) use the same
compatible value, the pin control driver relies on soc_device_match()
with soc_id = "r8a7795" and the (non)matching of revision = "ES1.*" to
match with and distinguish between the two SoC variants.  The
corresponding entries in the normal of_match_table are present only to
make the optional sanity checks work.

The R-Car H3e-2G (R8A779M1) SoC is a different grading of the R-Car H3
ES3.0 (R8A77951) SoC.  It uses the same compatible values for individual
devices, but has an additional compatible value for the root node.
When running on an R-Car H3e-2G SoC, soc_device_match() with soc_id =
"r8a7795" does not return a match.  Hence the pin control driver falls
back to the normal of_match_table, and, as the R8A77950 entry is listed
first, incorrectly uses the sub-driver for R-Car H3 ES1.x.

Fix this by moving the entry for R8A77951 before the entry for R8A77950.
Simplify sh_pfc_quirk_match() to only handle R-Car H3 ES1,x, as R-Car H3
ES2.0+ can now be matched using the normal of_match_table as well.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/6cdc5bfa424461105779b56f455387e03560cf66.1626707688.git.geert+renesas@glider.be
2021-07-27 09:29:02 +02:00
Fabio Estevam af0ca06f87 pinctrl: imx8ulp: Initialize pin_reg
The initialization of pin_reg is missing, causing the following build
warning:

drivers/pinctrl/freescale/pinctrl-imx8ulp.c:228:35: warning: 'pin_reg' is used uninitialized in this function [-Wuninitialized]

Initialize pin_reg the same way as it is done on vf610 and imx7ulp
to fix the problem.

Fixes: 16b343e8e0 ("pinctrl: imx8ulp: Add pinctrl driver support")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Link: https://lore.kernel.org/r/20210723203242.88845-1-festevam@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-23 22:52:47 +02:00
Bhupesh Sharma 79e2311c87 pinctrl: qcom/pinctrl-spmi-gpio: Add compatible for pmic-gpio on SA8155p-adp
SA8155p-adp PMIC (PMM8155AU) exposes 10 GPIOs.

Add support for the same in the pinctrl driver.

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Link: https://lore.kernel.org/r/20210629123407.82561-5-bhupesh.sharma@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-23 18:20:32 +02:00
Bhupesh Sharma 4afc2a0c62 pinctrl: qcom/pinctrl-spmi-gpio: Arrange compatibles alphabetically
Arrange the compatibles inside qcom pinctrl-spmi gpio driver
alphabetically.

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Link: https://lore.kernel.org/r/20210629123407.82561-4-bhupesh.sharma@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-23 18:20:32 +02:00
kernel test robot 1ac1f6459d pinctrl: mediatek: fix platform_no_drv_owner.cocci warnings
drivers/pinctrl/mediatek/pinctrl-mt8365.c:488:3-8: No need to set .owner here. The core will do it.

 Remove .owner field if calls are used which set it automatically

Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci

Fixes: e94d8b6fb8 ("pinctrl: mediatek: add support for mt8365 SoC")
CC: Fabien Parent <fparent@baylibre.com>
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/r/20210626051550.GA37544@d0c207d51ce8
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-23 18:11:30 +02:00
Anson Huang 16b343e8e0 pinctrl: imx8ulp: Add pinctrl driver support
Add i.MX8ULP pinctrl driver support.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Link: https://lore.kernel.org/r/20210607061041.2654568-2-ping.bai@nxp.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-23 18:04:05 +02:00
Marek Behún baf8d6899b pinctrl: armada-37xx: Correct PWM pins definitions
The PWM pins on North Bridge on Armada 37xx can be configured into PWM
or GPIO functions. When in PWM function, each pin can also be configured
to drive low on 0 and tri-state on 1 (LED mode).

The current definitions handle this by declaring two pin groups for each
pin:
- group "pwmN" with functions "pwm" and "gpio"
- group "ledN_od" ("od" for open drain) with functions "led" and "gpio"

This is semantically incorrect. The correct definition for each pin
should be one group with three functions: "pwm", "led" and "gpio".

Change the "pwmN" groups to support "led" function.

Remove "ledN_od" groups. This cannot break backwards compatibility with
older device trees: no device tree uses it since there is no PWM driver
for this SOC yet. Also "ledN_od" groups are not even documented.

Fixes: b835d69530 ("pinctrl: armada-37xx: swap polarity on LED group")
Signed-off-by: Marek Behún <kabel@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210719112938.27594-1-kabel@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-23 17:54:42 +02:00
Jason Wang 29d45a642d pinctrl: bcm2835: Replace BUG with BUG_ON
The if condition followed by BUG can be replaced to BUG_ON which is
more compact and formal in linux source.

Signed-off-by: Jason Wang <wangborong@cdjrlc.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Link: https://lore.kernel.org/r/20210624064913.41788-1-wangborong@cdjrlc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-23 17:47:00 +02:00
Konrad Dybcio 41353ae7a1 pinctrl: qcom: Add MDM9607 pinctrl driver
Add a pinctrl driver to allow for managing SoC pins.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210624191743.617073-2-konrad.dybcio@somainline.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-23 17:44:13 +02:00
Hsin-Yi Wang 798a315fc3 pinctrl: mediatek: Fix fallback behavior for bias_set_combo
Some pin doesn't support PUPD register, if it fails and fallbacks with
bias_set_combo case, it will call mtk_pinconf_bias_set_pupd_r1_r0() to
modify the PUPD pin again.

Since the general bias set are either PU/PD or PULLSEL/PULLEN, try
bias_set or bias_set_rev1 for the other fallback case. If the pin
doesn't support neither PU/PD nor PULLSEL/PULLEN, it will return
-ENOTSUPP.

Fixes: 81bd1579b4 ("pinctrl: mediatek: Fix fallback call path")
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
Link: https://lore.kernel.org/r/20210701080955.2660294-1-hsinyi@chromium.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-23 17:41:56 +02:00
Arnd Bergmann 32ec396017 pinctrl: qcom: fix GPIOLIB dependencies
Enabling the PINCTRL_SM8350 symbol without GPIOLIB or SCM causes a build
failure:

WARNING: unmet direct dependencies detected for PINCTRL_MSM
  Depends on [m]: PINCTRL [=y] && (ARCH_QCOM [=y] || COMPILE_TEST [=y]) && GPIOLIB [=y] && (QCOM_SCM [=m] || !QCOM_SCM [=m])
  Selected by [y]:
  - PINCTRL_SM8350 [=y] && PINCTRL [=y] && (ARCH_QCOM [=y] || COMPILE_TEST [=y]) && GPIOLIB [=y] && OF [=y]
aarch64-linux-ld: drivers/pinctrl/qcom/pinctrl-msm.o: in function `msm_gpio_irq_set_type':
pinctrl-msm.c:(.text.msm_gpio_irq_set_type+0x1c8): undefined reference to `qcom_scm_io_readl'

The main problem here is the 'select PINCTRL_MSM', which needs to be a
'depends on' as it is for all the other front-ends. As the GPIOLIB
dependency is now implied by that, symbol, remove the duplicate
dependencies in the process.

Fixes: d5d348a327 ("pinctrl: qcom: Add SM8350 pinctrl driver")
Fixes: 376f9e34c1 ("drivers: pinctrl: qcom: fix Kconfig dependency on GPIOLIB")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210723091400.1669716-1-arnd@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-23 11:51:19 +02:00
Geert Uytterhoeven e9d66bdbc5 pinctrl: renesas: r8a77995: Add bias pinconf support
Implement support for pull-up (most pins, excl. DU_DOTCLKIN0) and
pull-down (most pins, excl. JTAG) handling for the R-Car D3 SoC, using
some parts from the common R-Car bias handling, which requires making
rcar_pin_to_bias_reg() public.

R-Car D3 needs special handling for the NFRE# (GP_3_0) and NFWE#
(GP_3_1) pins.  Unlike all other pins, they are controlled by different
bits in the LSI pin pull-up/down control register (PUD2) than in the LSI
pin pull-enable register (PUEN2).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/04aad2b0bf82a32fb08e5e21e4ac1fb03452724f.1625064076.git.geert+renesas@glider.be
2021-07-13 09:43:34 +02:00
Geert Uytterhoeven 7ebaa41047 pinctrl: renesas: rcar: Avoid changing PUDn when disabling bias
When disabling pin bias, there is no need to touch the LSI pin
pull-up/down control register (PUDn), which selects between pull-up and
pull-down.  Just disabling the pull-up/down function through the LSI pin
pull-enable register (PUENn) is sufficient.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/071ec644de2555da593a4531ef5d3e4d79cf997d.1625064076.git.geert+renesas@glider.be
2021-07-13 09:43:23 +02:00
Linus Torvalds a32b344e6f This is the bulk of pin control changes for the v5.14 kernel:
New drivers:
 
 - Last merge window we created a driver for the Ralink RT2880.
   We are now moving the Ralink SoC pin control drivers out of the MIPS
   architecture code and into the pin control subsystem. This concerns
   RT288X, MT7620, RT305X, RT3883 and MT7621.
 
 - Qualcomm SM6125 SoC pin control driver.
 
 - Qualcomm spmi-gpio support for PM7325.
 
 - Qualcomm spmi-mpp also handles PMI8994 (just a compatible string)
 
 - Mediatek MT8365 SoC pin controller.
 
 - New device HID for the AMD GPIO controller.
 
 Improvements:
 
 - Pin bias config support for a slew of Renesas pin controllers.
 
 - Incremental improvements and non-urgent bug fixes to the Renesas
   SoC drivers.
 
 - Implement irq_set_wake on the AMD pin controller so we can wake
   up from external pin events.
 
 Misc:
 
 - Devicetree bindings for the Apple M1 pin controller, we will probably
   see a proper driver for this soon as well.
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Merge tag 'pinctrl-v5.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v5.14 kernel. Not so
  much going on. No core changes, just drivers.

  The most interesting would be that MIPS Ralink is migrating to pin
  control and we have some bindings but not yet code for the Apple M1
  pin controller.

  New drivers:

   - Last merge window we created a driver for the Ralink RT2880. We are
     now moving the Ralink SoC pin control drivers out of the MIPS
     architecture code and into the pin control subsystem. This concerns
     RT288X, MT7620, RT305X, RT3883 and MT7621.

   - Qualcomm SM6125 SoC pin control driver.

   - Qualcomm spmi-gpio support for PM7325.

   - Qualcomm spmi-mpp also handles PMI8994 (just a compatible string)

   - Mediatek MT8365 SoC pin controller.

   - New device HID for the AMD GPIO controller.

  Improvements:

   - Pin bias config support for a slew of Renesas pin controllers.

   - Incremental improvements and non-urgent bug fixes to the Renesas
     SoC drivers.

   - Implement irq_set_wake on the AMD pin controller so we can wake up
     from external pin events.

  Misc:

   - Devicetree bindings for the Apple M1 pin controller, we will
     probably see a proper driver for this soon as well"

* tag 'pinctrl-v5.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (54 commits)
  pinctrl: ralink: rt305x: add missing include
  pinctrl: stm32: check for IRQ MUX validity during alloc()
  pinctrl: zynqmp: some code cleanups
  drivers: qcom: pinctrl: Add pinctrl driver for sm6125
  dt-bindings: pinctrl: qcom: sm6125: Document SM6125 pinctrl driver
  dt-bindings: pinctrl: mcp23s08: add documentation for reset-gpios
  pinctrl: mcp23s08: Add optional reset GPIO
  pinctrl: mediatek: fix mode encoding
  pinctrl: mcp23s08: Fix missing unlock on error in mcp23s08_irq()
  pinctrl: bcm: Constify static pinmux_ops
  pinctrl: bcm: Constify static pinctrl_ops
  pinctrl: ralink: move RT288X SoC pinmux config into a new 'pinctrl-rt288x.c' file
  pinctrl: ralink: move MT7620 SoC pinmux config into a new 'pinctrl-mt7620.c' file
  pinctrl: ralink: move RT305X SoC pinmux config into a new 'pinctrl-rt305x.c' file
  pinctrl: ralink: move RT3883 SoC pinmux config into a new 'pinctrl-rt3883.c' file
  pinctrl: ralink: move MT7621 SoC pinmux config into a new 'pinctrl-mt7621.c' file
  pinctrl: ralink: move ralink architecture pinmux header into the driver
  pinctrl: single: config: enable the pin's input
  pinctrl: mtk: Fix mt8365 Kconfig dependency
  pinctrl: mcp23s08: fix race condition in irq handler
  ...
2021-07-01 16:57:14 -07:00
Sergio Paracuellos bfa50166cd pinctrl: ralink: rt305x: add missing include
Header 'rt305x.h' is ralink architecture dependent file where
other general definitions which are in 'ralink_regs.h' are
being used. This 'rt305x.h' is only being included in two
different files: 'rt305x.c' and 'pinctrl-rt305x.c'. When
file 'pinctrl-rt305x.c' is being compiled definitions in
'ralink_regs.h' are need to build it properly. Hence, add
missing include 'ralink_regs.h' in 'pinctrl-rt305x.c'
source to avoid compilation problems.

Fixes: 3a1b0ca5a8 ("pinctrl: ralink: move RT305X SoC pinmux config into a new 'pinctrl-rt305x.c' file")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210629143407.14703-1-sergio.paracuellos@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-30 02:38:56 +02:00
Fabien Dessenne db0f032512 pinctrl: stm32: check for IRQ MUX validity during alloc()
Considering the following irq_domain_ops call chain:
- .alloc() is called when a clients calls platform_get_irq() or
  gpiod_to_irq()
- .activate() is called next, when the clients calls
  request_threaded_irq()
Check for the IRQ MUX conflict during the first stage (alloc instead of
activate). This avoids to provide the client with an IRQ that can't be
used.

Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Link: https://lore.kernel.org/r/20210617144602.2557619-1-fabien.dessenne@foss.st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-26 01:52:35 +02:00
Sai Krishna Potthuri fa99e70138 pinctrl: zynqmp: some code cleanups
Some minor code cleanups and updates which includes
- Mention module name under help in Kconfig.
- Remove extra lines and duplicate Pin range checks.
- Replace 'return ret' with 'return 0' in success path.
- Copyright year update.
- use devm_pinctrl_register() instead pinctrl_register() in probe.

Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Link: https://lore.kernel.org/r/1624273214-66849-1-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-26 01:44:19 +02:00
Fabien Dessenne 67e2996f72 pinctrl: stm32: fix the reported number of GPIO lines per bank
Each GPIO bank supports a variable number of lines which is usually 16, but
is less in some cases : this is specified by the last argument of the
"gpio-ranges" bank node property.
Report to the framework, the actual number of lines, so the libgpiod
gpioinfo command lists the actually existing GPIO lines.

Fixes: 1dc9d28915 ("pinctrl: stm32: add possibility to use gpio-ranges to declare bank range")
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Link: https://lore.kernel.org/r/20210617144629.2557693-1-fabien.dessenne@foss.st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-18 14:56:54 +02:00
Martin Botka 0c3ae641a2 drivers: qcom: pinctrl: Add pinctrl driver for sm6125
This patch adds pinctrl driver for sm6125.

Signed-off-by: Martin Botka <martin.botka@somainline.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210614172713.558192-2-martin.botka@somainline.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-18 11:21:45 +02:00
Andy Shevchenko 76b7f8fae3 pinctrl: microchip-sgpio: Put fwnode in error case during ->probe()
device_for_each_child_node() bumps a reference counting of a returned variable.
We have to balance it whenever we return to the caller.

Fixes: 7e5ea974e6 ("pinctrl: pinctrl-microchip-sgpio: Add pinctrl driver for Microsemi Serial GPIO")
Cc: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20210606191940.29312-1-andy.shevchenko@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-18 11:17:47 +02:00
Linus Walleij 2f792ec782 pinctrl: renesas: Updates for v5.14 (take two)
- Add bias support for the R-Car H2, V2H, E2, V3M, and V3H, and
     RZ/G1C, RZ/G1H, and RZ/G1E SoCs.
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Merge tag 'renesas-pinctrl-for-v5.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: renesas: Updates for v5.14 (take two)

  - Add bias support for the R-Car H2, V2H, E2, V3M, and V3H, and
    RZ/G1C, RZ/G1H, and RZ/G1E SoCs.
2021-06-12 02:04:12 +02:00
Andreas Kaessens 4e73bfa3ee pinctrl: mcp23s08: Add optional reset GPIO
The MCP23x port expander RESET# line can be connected to a host GPIO.
The optional reset-gpio must be set to LOW if the reset is asserted
at probing time.

On page 5 in the datasheet [0] the "Device Active After Reset high"
time is specified at 0 µs. Therefore no waiting is needed after the
reset transition.

[0] https://ww1.microchip.com/downloads/en/DeviceDoc/20001952C.pdf

Signed-off-by: Andreas Kaessens <akaessens@gmail.com>
Signed-off-by: Darian Biastoch <d.biastoch@gmail.com>
Link: https://lore.kernel.org/r/20210610132438.3085841-1-akaessens@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-12 01:58:10 +02:00
Linus Walleij ca199e1952 intel-pinctrl for v5.14-1
* Enabling pin controller on Intel Alder Lake-M
 
 The following is an automated git shortlog grouped by driver:
 
 tigerlake:
  -  Add Alder Lake-M ACPI ID
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Merge tag 'intel-pinctrl-v5.14-1' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel

intel-pinctrl for v5.14-1

* Enabling pin controller on Intel Alder Lake-M

The following is an automated git shortlog grouped by driver:

tigerlake:
 -  Add Alder Lake-M ACPI ID
2021-06-09 15:31:05 +02:00
Matthias Brugger 21c423a651 pinctrl: mediatek: fix mode encoding
Pin modes are encoded in the SoC data structure. Use that value to set
IES SMT.

Cc: Fabien Parent <fparent@baylibre.com>
Cc: Sean Wang <sean.wang@kernel.org>
Cc: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Cc: linux-mediatek@lists.infradead.org
Fixes: 696beef775 ("pinctrl: mediatek: move bit assignment")
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Link: https://lore.kernel.org/r/20210608150656.29007-1-matthias.bgg@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-09 15:30:45 +02:00
Zou Wei 884af72c90 pinctrl: mcp23s08: Fix missing unlock on error in mcp23s08_irq()
Add the missing unlock before return from function mcp23s08_irq()
in the error handling case.

v1-->v2:
   remove the "return IRQ_HANDLED" line

Fixes: 897120d41e ("pinctrl: mcp23s08: fix race condition in irq handler")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Zou Wei <zou_wei@huawei.com>
Link: https://lore.kernel.org/r/1623134048-56051-1-git-send-email-zou_wei@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-09 15:30:44 +02:00
Bjorn Andersson 30e9857a13 pinctrl: qcom: Make it possible to select SC8180x TLMM
It's currently not possible to select the SC8180x TLMM driver, due to it
selecting PINCTRL_MSM, rather than depending on the same. Fix this.

Fixes: 97423113ec ("pinctrl: qcom: Add sc8180x TLMM driver")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210608180702.2064253-1-bjorn.andersson@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-09 13:15:20 +02:00
Rikard Falkeborn 0c68387672 pinctrl: bcm: Constify static pinmux_ops
These are only assigned, either directly or via the bcm63xx_pinctrl_soc
struct, to the pmxops field in the pinctrl_desc struct and never
modified, so make them const to allow the compiler to put them in
read-only memory.

Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Link: https://lore.kernel.org/r/20210605185908.39982-3-rikard.falkeborn@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-09 11:18:33 +02:00
Rikard Falkeborn d977909367 pinctrl: bcm: Constify static pinctrl_ops
These are only assigned, either directly or via the bcm63xx_pinctrl_soc
struct, to the pctlops field in the pinctrl_desc struct and never
modified, so make them const to allow the compiler to put them in
read-only memory.

Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Link: https://lore.kernel.org/r/20210605185908.39982-2-rikard.falkeborn@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-09 11:18:33 +02:00
Sergio Paracuellos a49a8717d8 pinctrl: ralink: move RT288X SoC pinmux config into a new 'pinctrl-rt288x.c' file
Move all related code for SoC RT288X into a new driver located
in 'pinctrl-rt288x.c' source file.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210604115159.8834-7-sergio.paracuellos@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-07 09:17:48 +02:00
Sergio Paracuellos 745ec436de pinctrl: ralink: move MT7620 SoC pinmux config into a new 'pinctrl-mt7620.c' file
Move all related code for SoC MT7620 into a new driver located
in 'pinctrl-mt7620.c' source file.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210604115159.8834-6-sergio.paracuellos@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-07 09:17:47 +02:00
Sergio Paracuellos 3a1b0ca5a8 pinctrl: ralink: move RT305X SoC pinmux config into a new 'pinctrl-rt305x.c' file
Move all related code for SoC RT305X into a new driver located
in 'pinctrl-rt305x.c' source file.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210604115159.8834-5-sergio.paracuellos@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-07 09:17:47 +02:00
Sergio Paracuellos 8b8b0fa21d pinctrl: ralink: move RT3883 SoC pinmux config into a new 'pinctrl-rt3883.c' file
Move all related code for SoC RT3883 into a new driver located
in 'pinctrl-rt3883.c' source file

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210604115159.8834-4-sergio.paracuellos@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-07 09:17:47 +02:00
Sergio Paracuellos e98dd3db96 pinctrl: ralink: move MT7621 SoC pinmux config into a new 'pinctrl-mt7621.c' file
Move all related code for SoC MT7621 into a new driver located
in 'pinctrl-mt7621.c' source file.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210604115159.8834-3-sergio.paracuellos@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-07 09:17:47 +02:00
Sergio Paracuellos 276e552e08 pinctrl: ralink: move ralink architecture pinmux header into the driver
Ralink architecture is making use of the header located in
'arch/mips/include/asm/mach-ralink/pinmux.h' to stablish the
mechanisms to make derived SoCs to set its pin functions and
groups. In order to move all architecture pinmux into a more
accurate place which is 'drivers/pinctrl/ralink' we have to
first of all move this file also there with a small modification
which creates 'rt2880_pinmux_init' function to allow SoCs pinctrl
drivers to pass its configuration to the common code located in
'pinctrl-rt2880.c' file.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210604115159.8834-2-sergio.paracuellos@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-07 09:17:47 +02:00
Sergio Paracuellos eb367d875f pinctrl: ralink: rt2880: avoid to error in calls is pin is already enabled
In 'rt2880_pmx_group_enable' driver is printing an error and returning
-EBUSY if a pin has been already enabled. This begets anoying messages
in the caller when this happens like the following:

rt2880-pinmux pinctrl: pcie is already enabled
mt7621-pci 1e140000.pcie: Error applying setting, reverse things back

To avoid this just print the already enabled message in the pinctrl
driver and return 0 instead to not confuse the user with a real
bad problem.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210604055337.20407-1-sergio.paracuellos@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-07 09:08:53 +02:00
Dario Binacchi 8c987eb15a pinctrl: single: config: enable the pin's input
It enables / disables the input buffer. As explained in the description
of 'enum pin_config_param' this does not affect the pin's ability to
drive output.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Acked-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20210602150420.18202-1-dariobin@libero.it
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-07 09:02:27 +02:00
Linus Walleij 375eede3e3 pinctrl: mtk: Fix mt8365 Kconfig dependency
This SoC needs to select PINCTRL_MTK or we can end up in
kernel compiles that miss some symbols.

Cc: Fabien Parent <fparent@baylibre.com>
Reported-by: kernel test robot <lkp@intel.com>
Fixes: e94d8b6fb8 ("pinctrl: mediatek: add support for mt8365 SoC")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-07 08:56:20 +02:00
Radim Pavlik 897120d41e pinctrl: mcp23s08: fix race condition in irq handler
Checking value of MCP_INTF in mcp23s08_irq suggests that the handler may be
called even when there is no interrupt pending.

But the actual interrupt could happened between reading MCP_INTF and MCP_GPIO.
In this situation we got nothing from MCP_INTF, but the event gets acknowledged
on the expander by reading MCP_GPIO. This leads to losing events.

Fix the problem by not reading any register until we see something in MCP_INTF.

The error was reproduced and fix tested on MCP23017.

Signed-off-by: Radim Pavlik <radim.pavlik@tbs-biometrics.com>
Link: https://lore.kernel.org/r/AM7PR06MB6769E1183F68DEBB252F665ABA3E9@AM7PR06MB6769.eurprd06.prod.outlook.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-07 00:23:58 +02:00
Manivannan Sadhasivam 0e4bf265b1 pinctrl: qcom: Fix duplication in gpio_groups
"gpio52" and "gpio53" are duplicated in gpio_groups, fix them!

Fixes: ac43c44a7a ("pinctrl: qcom: Add SDX55 pincontrol driver")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210526082857.174682-1-manivannan.sadhasivam@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-07 00:18:55 +02:00
Geert Uytterhoeven c3975a73ca pinctrl: renesas: r8a77980: Add bias pinconf support
Implement support for pull-up and pull-down handling for the R-Car V3H
SoC, using the common R-Car bias handling.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/448f47ccd89d9bc8621c7fda8c81508deb05cb82.1619785375.git.geert+renesas@glider.be
2021-05-31 10:50:29 +02:00
Geert Uytterhoeven b764833e36 pinctrl: renesas: r8a77970: Add bias pinconf support
Implement support for pull-up (most pins, excl. DU_DOTCLKIN and EXTALR)
and pull-down (most pins, excl. JTAG) handling for the R-Car V3M SoC,
using the common R-Car bias handling.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/bcfad447624d874258a45a92554574b8fe9f712f.1619785375.git.geert+renesas@glider.be
2021-05-31 10:50:28 +02:00
Geert Uytterhoeven 009f502238 pinctrl: renesas: r8a7794: Add bias pinconf support
Implement support for pull-up (most pins) and pull-down (ASEBRK#/ACK)
handling for R-Car E2 and RZ/G1E SoCs, using the common R-Car bias
handling.

Note that on RZ/G1E, the "ASEBRK#/ACK" pin is called "ACK", but the code
doesn't handle that naming difference.  Hence users should use the R-Car
naming in DTS files.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/f78da2ba937ce98ae9196f4ee54149a5214fd545.1619785375.git.geert+renesas@glider.be
2021-05-31 10:50:28 +02:00
Geert Uytterhoeven 35477d7e90 pinctrl: renesas: r8a7792: Add bias pinconf support
Implement support for pull-up (most pins) and pull-down (EDBGREQ)
handling for the R-Car V2H SoC, using the common R-Car bias handling.

Note that the R-Car V2H Hardware User's Manual Rev. 1.00 says that
the LSI Pin Pull-Up Control Register 11 (PUPR11) controls pull-ups for
the {SCK,WS,SDATA}[01] pins.  These are assumed to be typos, as R-Car
V2H has only Serial Sound Interface channels 3 and 4.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/48d2abdd63ee43ed99cb32ed4a5f4d76ba563162.1619785375.git.geert+renesas@glider.be
2021-05-31 10:50:28 +02:00
Geert Uytterhoeven 2be3d60242 pinctrl: renesas: r8a7790: Add bias pinconf support
Implement support for pull-up (most pins) and pull-down (ASEBRK#/ACK)
handling for R-Car H2 and RZ/G1H SoCs, using the common R-Car bias
handling.

Note that on RZ/G1H, the "ASEBRK#/ACK" pin is called "ACK", but the code
doesn't handle that naming difference.  Hence users should use the R-Car
naming in DTS files.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/dde6e0b36a4e4494039a3466df208b5ec5c594ee.1619785375.git.geert+renesas@glider.be
2021-05-31 10:50:28 +02:00
Geert Uytterhoeven fd6850132f pinctrl: renesas: r8a77470: Add bias pinconf support
Implement support for pull-up (most pins) and pull-down (ASEBRK#/ACK)
handling for the RZ/G1C SoC, using the common R-Car bias handling.

Note that on RZ/G1C, the "ASEBRK#/ACK" pin is called "ACK", but the code
doesn't handle that naming difference.  Hence users should use the R-Car
naming in DTS files.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/18c8ebf9fa9e239253a723857e9dffeec775db7e.1619785375.git.geert+renesas@glider.be
2021-05-31 10:50:28 +02:00
Linus Walleij 50bdc4d441 pinctrl: renesas: Updates for v5.14
- Minor fixes and improvements.
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Merge tag 'renesas-pinctrl-for-v5.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: renesas: Updates for v5.14

  - Minor fixes and improvements.
2021-05-28 14:24:41 +02:00
Linus Walleij 696beef775 pinctrl: mediatek: move bit assignment
The bit needs offset to be defined which happens some lines
below. Looks like a bug. The kernel test robot complains:

drivers/pinctrl/mediatek/pinctrl-mtk-common.c:137:12:
warning: variable 'offset' is uninitialized when used here [-Wuninitialized]
           bit = BIT(offset & pctl->devdata->mode_mask);
                     ^~~~~~

Fix it up by reverting to what was done before.

Cc: Fabien Parent <fparent@baylibre.com>
Cc: Sean Wang <sean.wang@kernel.org>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Cc: linux-mediatek@lists.infradead.org
Fixes: 9f940d8ecf ("pinctrl: mediatek: don't hardcode mode encoding in common code")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-05-28 11:19:10 +02:00
Phil Elwell 4bc80da533 pinctrl: bcm2835: Accept fewer than expected IRQs
The downstream .dts files only request two GPIO IRQs. Truncate the
array of parent IRQs when irq_of_parse_and_map returns 0.

Signed-off-by: Phil Elwell <phil@raspberrypi.com>
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Link: https://lore.kernel.org/r/20210521090158.26932-1-iivanov@suse.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-05-28 02:56:13 +02:00
Yang Li b9045af9fb pinctrl: Fix kernel-doc
Fix function name in pinctrl-single.c kernel-doc comment
to remove a warning found by clang_w1.

drivers/pinctrl/pinctrl-single.c:1523: warning: expecting prototype for
pcs_irq_handle(). Prototype was for pcs_irq_chain_handler() instead.

Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
Link: https://lore.kernel.org/r/1621998464-10918-1-git-send-email-yang.lee@linux.alibaba.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-05-28 02:42:10 +02:00
Steven Lee 0b97148459 pinctrl: pinctrl-aspeed-g6: Add sgpio pinctrl settings
AST2600 supports 2 SGPIO master interfaces and 2 SGPIO slave interfaces.
Current pinctrl driver only define the first sgpio master and slave
interfaces.
The second SGPIO master and slave interfaces should be added in
pinctrl driver as well.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20210525055308.31069-4-steven_lee@aspeedtech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-05-28 01:47:53 +02:00
Fabien Parent e94d8b6fb8 pinctrl: mediatek: add support for mt8365 SoC
Add pinctrl driver for MT8365 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Link: https://lore.kernel.org/r/20210519162409.3755679-3-fparent@baylibre.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-05-27 16:50:15 +02:00
Fabien Parent 9f940d8ecf pinctrl: mediatek: don't hardcode mode encoding in common code
MT8365 encode the pins mode differently than other
MTK pinctrl drivers that use the PINCTRL_MTK common code.

Add 3 new fields in mtk_pinctrl_devdata in order to store how
pin modes are encoded into the register. At the
same time update all the pinctrl driver that depends on
CONFIG_PINCTRL_MTK.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Link: https://lore.kernel.org/r/20210519162409.3755679-2-fparent@baylibre.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-05-27 16:50:15 +02:00
Rikard Falkeborn f56b273cd8 pinctrl: at91: Constify struct at91_pinctrl_mux_ops
The at91_pinctrl_mux_ops struct is never modified by the driver. Make it
const wherever it is possible to allow the compiler to put the static
variables in read-only memory. Note that sam9x60_ops was already const,
but the const was cast away when the return value of of_match_device() was
cast to a pointer to a non-const struct at91_pinctrl_mux_ops.

Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Link: https://lore.kernel.org/r/20210512180140.33293-1-rikard.falkeborn@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-05-25 17:10:05 +02:00
Jonathan Neuschäfer 9b882b73d3 pinctrl: npcm: Align a few entries in the pin function table
The entries for GPIO 33 and 34 are not properly aligned. Fix the
alignment.

Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Link: https://lore.kernel.org/r/20210513160947.1716185-1-j.neuschaefer@gmx.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-05-25 17:10:05 +02:00
Maximilian Luz 1ca46d3e43 pinctrl/amd: Add device HID for new AMD GPIO controller
Add device HID AMDI0031 to the AMD GPIO controller driver match table.
This controller can be found on Microsoft Surface Laptop 4 devices and
seems similar enough that we can just copy the existing AMDI0030 entry.

Cc: <stable@vger.kernel.org> # 5.10+
Tested-by: Sachi King <nakato@nakato.io>
Signed-off-by: Maximilian Luz <luzmaximilian@gmail.com>
Link: https://lore.kernel.org/r/20210512210316.1982416-1-luzmaximilian@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-05-25 17:09:48 +02:00
Andy Shevchenko 258435a1c8 pinctrl: tigerlake: Add Alder Lake-M ACPI ID
Intel Alder Lake-M PCH has the same GPIO hardware than Tiger Lake-LP
PCH but the ACPI ID is different. Add this new ACPI ID to the list of
supported devices.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2021-05-25 16:26:38 +03:00
satya priya 676e2d0750 pinctrl: qcom: spmi-gpio: Add support for pm7325
Add compatible string for PM7325 pmic GPIO support to the
Qualcomm PMIC GPIO driver.

Signed-off-by: satya priya <skakit@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1620817988-18809-2-git-send-email-skakit@codeaurora.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-05-20 01:42:05 +02:00
Zhen Lei ef9385fbf3 pinctrl: iproc-gpio: Remove redundant error printing in iproc_gpio_probe()
When devm_ioremap_resource() fails, a clear enough error message will be
printed by its subfunction __devm_ioremap_resource(). The error
information contains the device name, failure cause, and possibly resource
information.

Therefore, remove the error printing here to simplify code and reduce the
binary size.

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Acked-by: Ray Jui <ray.jui@broadcom.com>
Link: https://lore.kernel.org/r/20210511085126.4287-1-thunder.leizhen@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-05-20 01:37:32 +02:00
Zhen Lei 0f9facdbd9 pinctrl: ocelot: Remove redundant error printing in ocelot_pinctrl_probe()
When devm_ioremap_resource() fails, a clear enough error message will be
printed by its subfunction __devm_ioremap_resource(). The error
information contains the device name, failure cause, and possibly resource
information.

Therefore, remove the error printing here to simplify code and reduce the
binary size.

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Link: https://lore.kernel.org/r/20210511090936.4452-1-thunder.leizhen@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-05-20 01:33:53 +02:00
Bixuan Cui d7f444499d pinctrl: equilibrium: Add missing MODULE_DEVICE_TABLE
This patch adds missing MODULE_DEVICE_TABLE definition which generates
correct modalias for automatic loading of this driver when it is built
as an external module.

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Bixuan Cui <cuibixuan@huawei.com>
Link: https://lore.kernel.org/r/20210508031502.53637-1-cuibixuan@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-05-20 01:00:24 +02:00
Bjorn Andersson 969ef42b1a pinctrl: qcom: spmi-mpp: Add compatible for pmi8994
The PMI8994 has 4 multi-purpose-pins, add a compatible for this hardware
block to the MPP driver.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210429003751.224232-1-bjorn.andersson@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-05-19 02:23:52 +02:00
Raul E Rangel d62bd5ce12 pinctrl: amd: Implement irq_set_wake
This allows the OS to control which devices produce wake events.

$ grep enabled /sys/kernel/irq/*/wakeup
/sys/kernel/irq/24/wakeup:enabled

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Link: https://lore.kernel.org/r/20210429163341.1.I7631534622233689dd81410525e0dd617b9b2012@changeid
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-05-19 02:20:05 +02:00
Souptick Joarder 333944c7c3 pinctrl: aspeed: Fix minor documentation error
Kernel test robot throws below warning ->

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c:2705: warning: This comment
starts with '/**', but isn't a kernel-doc comment. Refer
Documentation/doc-guide/kernel-doc.rst
drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c:2614: warning: This comment
starts with '/**', but isn't a kernel-doc comment. Refer
Documentation/doc-guide/kernel-doc.rst
drivers/pinctrl/aspeed/pinctrl-aspeed.c:111: warning: This comment
starts with '/**', but isn't a kernel-doc comment. Refer
Documentation/doc-guide/kernel-doc.rst
drivers/pinctrl/aspeed/pinmux-aspeed.c:24: warning: This comment starts
with '/**', but isn't a kernel-doc comment. Refer
Documentation/doc-guide/kernel-doc.rst

Fix minor documentation error.

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Souptick Joarder <jrdr.linux@gmail.com>
Cc: Randy Dunlap <rdunlap@infradead.org>
Reviewed-by: Randy Dunlap <rdunlap@infradead.org>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/1619353584-8196-1-git-send-email-jrdr.linux@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-05-19 02:11:18 +02:00
Geert Uytterhoeven 904ec4bebc pinctrl: renesas: r8a779{51,6,65}: Reduce non-functional differences
Change whitespace in the pin control drivers for R-Car H3 ES2.0+, R-Car
M3-W/M3-W+, and R-Car M3-N, to reduce the differences among these very
similar drivers.

These changes have no functional impact.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/527b45ebfc664a80e41cb0136677db7260e11437.1619785375.git.geert+renesas@glider.be
2021-05-11 10:04:42 +02:00
Geert Uytterhoeven cf04bbe5ed pinctrl: renesas: r8a7778: Remove unused PORT_GP_PUP_1() macro
The last user was removed in commit dd1f760bff ("pinctrl: sh-pfc:
r8a7778: Use common PORT_GP_CFG_27() macro").

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/129147ac57f5e931cc7108db0a6483b803a1b8f4.1619785375.git.geert+renesas@glider.be
2021-05-11 10:04:42 +02:00
Geert Uytterhoeven d82b924103 pinctrl: renesas: r8a77990: Drop bogus PUEN_ prefixes in comments
The "PUEN_" prefixes are part of the bit names of the PUEN registers,
while the comments should refer to the actual pin names.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/9ea85ae8973f6d9b3d10f02f0d9b4ab6a086ec63.1619785375.git.geert+renesas@glider.be
2021-05-11 10:04:42 +02:00
Geert Uytterhoeven 702a5fa2fe pinctrl: renesas: r8a77990: JTAG pins do not have pull-down capabilities
Hence remove the SH_PFC_PIN_CFG_PULL_DOWN flags from their pin
descriptions.

Fixes: 83f6941a42 ("pinctrl: sh-pfc: r8a77990: Add bias pinconf support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/da4b2d69955840a506412f1e8099607a0da97ecc.1619785375.git.geert+renesas@glider.be
2021-05-11 10:04:42 +02:00
Geert Uytterhoeven 2cee31cd49 pinctrl: renesas: r8a7796: Add missing bias for PRESET# pin
R-Car Gen3 Hardware Manual Errata for Rev. 0.52 of Nov 30, 2016, added
the configuration bit for bias pull-down control for the PRESET# pin on
R-Car M3-W.  Add driver support for controlling pull-down on this pin.

Fixes: 2d40bd2427 ("pinctrl: sh-pfc: r8a7796: Add bias pinconf support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/c479de5b3f235c2f7d5faea9e7e08e6fccb135df.1619785375.git.geert+renesas@glider.be
2021-05-11 10:04:42 +02:00
Masahiro Yamada 0ab1438bad linux/kconfig.h: replace IF_ENABLED() with PTR_IF() in <linux/kernel.h>
<linux/kconfig.h> is included from all the kernel-space source files,
including C, assembly, linker scripts. It is intended to contain a
minimal set of macros to evaluate CONFIG options.

IF_ENABLED() is an intruder here because (x ? y : z) is C code, which
should not be included from assembly files or linker scripts.

Also, <linux/kconfig.h> is no longer self-contained because NULL is
defined in <linux/stddef.h>.

Move IF_ENABLED() out to <linux/kernel.h> as PTR_IF(). PTF_IF()
takes the general boolean expression instead of a CONFIG option
so that it fits better in <linux/kernel.h>.

Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Reviewed-by: Kees Cook <keescook@chromium.org>
2021-05-09 00:29:45 +09:00
Linus Torvalds 65ec0a7d24 This is the bulk of the pin control changes for the v5.13 kernel cycle
Core changes:
 
 - A semantic change to handle pinmux and pinconf in explicit order
   while up until now we depended on the semantic order in the
   device tree. The device tree is a functional programming
   language and does not imply any order, so the right thing is
   for the pin control core to provide these semantics.
 
 - Add a new pinmux-select debugfs file which makes it possible to
   go in and select functions for a pin manually (iteratively, at
   the prompt) for debugging purposes.
 
 - Fixes to gpio regmap handling for a new pin control driver
   making use of regmap-gpio.
 
 - Use octal permissions on debugfs files.
 
 New drivers:
 
 - A massive rewrite of the former custom pin control driver for
   MIPS Broadcom devices to instead use the pin control subsystem.
   New pin control drivers for BCM6345, BCM6328, BCM6358, BCM6362,
   BCM6368, BCM63268 and BCM6318 SoC variants are implemented.
 
 - Support for PM8350, PM8350B, PM8350C, PMK8350, PMR735A and
   PMR735B in the Qualcomm PMIC GPIO driver. Also the two GPIOs
   on PM8008 are supported.
 
 - Support for the Rockchip RK3568/RK3566 pin controller.
 
 - Support for Ingenic JZ4730, JZ4750, JZ4755, JZ4775 and
   X2000.
 
 - Support for Mediatek MTK8195.
 
 - Add a new Xilinx ZynqMP pin control driver.
 
 Driver improvements and non-urgent fixes:
 
 - Modularization and improvements of the Rockchip drivers.
 
 - Some new pins added to the description of new Renesas SoCs.
 
 - Clarifications of the GPIO base calculation in the Intel driver.
 
 - Fix the function names for the MPP54 and MPP55 pins in the Armada
   CP110 pin controller.
 
 - GPIO wakeup interrupt map for Qualcomm SC7280 and SM8350.
 
 - Support for ACPI probing of the Qualcomm SC8180x.
 
 - Fix interrupt clear status on rockchip
 
 - Fix some missing pins on the Ingenic JZ4770, some semantic
   fixes for the behaviour of the Ingenic pin controller.
   Add DMIC pins for JZ4780, X1000, X1500 and X1830.
 
 - A slew of janitorial like of_node_put() calls.
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Merge tag 'pinctrl-v5.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "There is a lot going on!

  Core changes:

   - A semantic change to handle pinmux and pinconf in explicit order
     while up until now we depended on the semantic order in the device
     tree. The device tree is a functional programming language and does
     not imply any order, so the right thing is for the pin control core
     to provide these semantics.

   - Add a new pinmux-select debugfs file which makes it possible to go
     in and select functions for a pin manually (iteratively, at the
     prompt) for debugging purposes.

   - Fixes to gpio regmap handling for a new pin control driver making
     use of regmap-gpio.

   - Use octal permissions on debugfs files.

  New drivers:

   - A massive rewrite of the former custom pin control driver for MIPS
     Broadcom devices to instead use the pin control subsystem. New pin
     control drivers for BCM6345, BCM6328, BCM6358, BCM6362, BCM6368,
     BCM63268 and BCM6318 SoC variants are implemented.

   - Support for PM8350, PM8350B, PM8350C, PMK8350, PMR735A and PMR735B
     in the Qualcomm PMIC GPIO driver. Also the two GPIOs on PM8008 are
     supported.

   - Support for the Rockchip RK3568/RK3566 pin controller.

   - Support for Ingenic JZ4730, JZ4750, JZ4755, JZ4775 and X2000.

   - Support for Mediatek MTK8195.

   - Add a new Xilinx ZynqMP pin control driver.

  Driver improvements and non-urgent fixes:

   - Modularization and improvements of the Rockchip drivers.

   - Some new pins added to the description of new Renesas SoCs.

   - Clarifications of the GPIO base calculation in the Intel driver.

   - Fix the function names for the MPP54 and MPP55 pins in the Armada
     CP110 pin controller.

   - GPIO wakeup interrupt map for Qualcomm SC7280 and SM8350.

   - Support for ACPI probing of the Qualcomm SC8180x.

   - Fix interrupt clear status on rockchip

   - Fix some missing pins on the Ingenic JZ4770, some semantic fixes
     for the behaviour of the Ingenic pin controller. Add DMIC pins for
     JZ4780, X1000, X1500 and X1830.

   - A slew of janitorial like of_node_put() calls"

* tag 'pinctrl-v5.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (99 commits)
  pinctrl: Add Xilinx ZynqMP pinctrl driver support
  firmware: xilinx: Add pinctrl support
  pinctrl: rockchip: do coding style for mux route struct
  pinctrl: Add PIN_CONFIG_MODE_PWM to enum pin_config_param
  pinctrl: Introduce MODE group in enum pin_config_param
  pinctrl: Keep enum pin_config_param ordered by name
  dt-bindings: pinctrl: Add binding for ZynqMP pinctrl driver
  pinctrl: core: Fix kernel doc string for pin_get_name()
  pinctrl: mediatek: use spin lock in mtk_rmw
  pinctrl: add drive for I2C related pins on MT8195
  pinctrl: add pinctrl driver on mt8195
  dt-bindings: pinctrl: mt8195: add pinctrl file and binding document
  pinctrl: Ingenic: Add pinctrl driver for X2000.
  pinctrl: Ingenic: Add pinctrl driver for JZ4775.
  pinctrl: Ingenic: Add pinctrl driver for JZ4755.
  pinctrl: Ingenic: Add pinctrl driver for JZ4750.
  pinctrl: Ingenic: Add pinctrl driver for JZ4730.
  dt-bindings: pinctrl: Add bindings for new Ingenic SoCs.
  pinctrl: Ingenic: Reformat the code.
  pinctrl: Ingenic: Add DMIC pins support for Ingenic SoCs.
  ...
2021-04-30 13:04:30 -07:00