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Автор SHA1 Сообщение Дата
Tekkaman Ninja 715a7119ea Documentation: Fixes a word in Documentation/arm64/memory.txt
Fixes a term in Documentation/arm64/memory.txt
The modification is based on Catalin Marinas <catalin.marinas@arm.com>'s
suggestion:
    "memory" in "ffffffc000000000 ffffffffffffffff 256GB memory"
    should  be treated as "kernel logical memory map".

Signed-off-by: Fu Wei <tekkamanninja@gmail.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2012-11-29 16:33:18 +00:00
Catalin Marinas e3978cded4 arm64: Move PCI_IOBASE closer to MODULES_VADDR
This is to reuse the same pmd table that is sparsely populated with
the modules space.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2012-10-23 15:30:51 +01:00
Catalin Marinas 4f04d8f005 arm64: MMU definitions
The virtual memory layout is described in
Documentation/arm64/memory.txt. This patch adds the MMU definitions for
the 4KB and 64KB translation table configurations. The SECTION_SIZE is
2MB with 4KB page and 512MB with 64KB page configuration.

PHYS_OFFSET is calculated at run-time and stored in a variable (no
run-time code patching at this stage).

On the current implementation, both user and kernel address spaces are
512G (39-bit) each with a maximum of 256G for the RAM linear mapping.
Linux uses 3 levels of translation tables with the 4K page configuration
and 2 levels with the 64K configuration. Extending the memory space
beyond 39-bit with the 4K pages or 42-bit with 64K pages requires an
additional level of translation tables.

The SPARSEMEM configuration is global to all AArch64 platforms and
allows for 1GB sections with SPARSEMEM_VMEMMAP enabled by default.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Olof Johansson <olof@lixom.net>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2012-09-17 13:41:56 +01:00