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4 Коммитов

Автор SHA1 Сообщение Дата
Russ Weight f09f6dfef8
spi: altera: Change to dynamic allocation of spi id
The spi-altera driver has two flavors: platform and dfl. I'm seeing
a case where I have both device types in the same machine, and they
are conflicting on the SPI ID:

... kernel: couldn't get idr
... kernel: WARNING: CPU: 28 PID: 912 at drivers/spi/spi.c:2920 spi_register_controller.cold+0x84/0xc0a

Both the platform and dfl drivers use the parent's driver ID as the SPI
ID. In the error case, the parent devices are dfl_dev.4 and
subdev_spi_altera.4.auto. When the second spi-master is created, the
failure occurs because the SPI ID of 4 has already been allocated.

Change the ID allocation to dynamic (by initializing bus_num to -1) to
avoid duplicate SPI IDs.

Signed-off-by: Russ Weight <russell.h.weight@intel.com>
Link: https://lore.kernel.org/r/20211019002401.24041-1-russell.h.weight@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2021-10-20 01:53:15 +01:00
Martin Hundebøll 4f45f34049 spi: spi-altera-dfl: support n5010 feature revision
The Max10 BMC on the Silicom n5010 PAC is slightly different than the
existing BMCs, so use a dedicated feature revision detect it.

Acked-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Tom Rix <trix@redhat.com>
Signed-off-by: Martin Hundebøll <mhu@silicom.dk>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
2021-07-29 13:02:28 -07:00
Zou Wei 532259bfd1
spi: altera: Remove redundant dev_err call in dfl_spi_altera_probe()
There is a error message within devm_ioremap_resource
already, so remove the dev_err call to avoid redundant
error message.

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Zou Wei <zou_wei@huawei.com>
Link: https://lore.kernel.org/r/1620716922-108572-1-git-send-email-zou_wei@huawei.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2021-05-11 10:06:53 +01:00
Matthew Gerlach ba2fc167e9
spi: altera: Add DFL bus driver for Altera API Controller
This patch adds a Device Feature List (DFL) bus driver for the
Altera SPI Master controller.  The SPI master is connected to an
Intel SPI Slave to Avalon Bridge inside an Intel MAX10
BMC Chip.

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Link: https://lore.kernel.org/r/20210416165720.554144-3-matthew.gerlach@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2021-04-20 17:26:41 +01:00