- Do a DT/firmware lookup in clk_core_get() even when the DT index is a
nonsensical value
- Fix some clk data typos in the Amlogic DT headers/code
- Avoid returning junk in the TI clk driver when an invalid clk is
looked for
- Fix dividers for the emac clks on Stratix10 SoCs
- Fix default HDA rates on Tegra210 to correct distorted audio
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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"A handful of clk driver fixes and one core framework fix
- Do a DT/firmware lookup in clk_core_get() even when the DT index is
a nonsensical value
- Fix some clk data typos in the Amlogic DT headers/code
- Avoid returning junk in the TI clk driver when an invalid clk is
looked for
- Fix dividers for the emac clks on Stratix10 SoCs
- Fix default HDA rates on Tegra210 to correct distorted audio"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: socfpga: stratix10: fix divider entry for the emac clocks
clk: Do a DT parent lookup even when index < 0
clk: tegra210: Fix default rates for HDA clocks
clk: ti: clkctrl: Fix returning uninitialized data
clk: meson: meson8b: fix a typo in the VPU parent names array variable
clk: meson: fix MPLL 50M binding id typo
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Based on 1 normalized pattern(s):
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Based on 3 normalized pattern(s):
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this program is free software you can redistribute it and or modify
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the free software foundation either version 2 of the license or at
your option any later version [author] [kishon] [vijay] [abraham]
[i] [kishon]@[ti] [com] this program is distributed in the hope that
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[gg]@[slimlogic] [co] [uk] [author] [kishon] [vijay] [abraham] [i]
[kishon]@[ti] [com] [based] [on] [twl6030]_[usb] [c] [author] [hema]
[hk] [hemahk]@[ti] [com] this program is distributed in the hope
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Based on 1 normalized pattern(s):
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675 mass ave cambridge ma 02139 usa
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Based on 2 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license as published by
the free software foundation either version 2 of the license or at
your option any later version this program is distributed in the
hope that it will be useful but without any warranty without even
the implied warranty of merchantability or fitness for a particular
purpose see the gnu general public license for more details you
should have received a copy of the gnu general public license along
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this program is free software you can redistribute it and or modify
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your option any later version this program is distributed in the
hope that it will be useful but without any warranty without even
the implied warranty of merchantability or fitness for a particular
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[from] [clk] [highbank] [c] you should have received a copy of the
gnu general public license along with this program if not see http
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extracted by the scancode license scanner the SPDX license identifier
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Based on 2 normalized pattern(s):
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purpose see the gnu general public license for more details you
should have received a copy of the gnu general public license along
with this program if not write to the free software foundation inc
51 franklin street fifth floor boston ma 02110 1301 usa
this program is free software you can redistribute it and or modify
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your option [no]_[pad]_[ctrl] any later version this program is
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software foundation inc 51 franklin street fifth floor boston ma
02110 1301 usa
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MPLL_5OM (the capital letter o) should indeed be MPLL_50M (the number)
Fix this before it gets used.
Fixes: 25db146aa7 ("dt-bindings: clk: meson: add g12a periph clock controller bindings")
Reported-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Pull thermal soc updates from Eduardo Valentin:
- thermal core has a new devm_* API for registering cooling devices. I
took the entire series, that is why you see changes on drivers/hwmon
in this pull (Guenter Roeck)
- rockchip thermal driver gains support to PX30 SoC (Elaine Zhang)
- the generic-adc thermal driver now considers the lookup table DT
property as optional (Jean-Francois Dagenais)
- Refactoring of tsens thermal driver (Amit Kucheria)
- Cleanups on cpu cooling driver (Daniel Lezcano)
- broadcom thermal driver dropped support to ACPI (Srinath Mannam)
- tegra thermal driver gains support to OC hw throttle and GPU throtle
(Wei Ni)
- Fixes in several thermal drivers.
* 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal: (59 commits)
hwmon: (pwm-fan) Use devm_thermal_of_cooling_device_register
hwmon: (npcm750-pwm-fan) Use devm_thermal_of_cooling_device_register
hwmon: (mlxreg-fan) Use devm_thermal_of_cooling_device_register
hwmon: (gpio-fan) Use devm_thermal_of_cooling_device_register
hwmon: (aspeed-pwm-tacho) Use devm_thermal_of_cooling_device_register
thermal: rcar_gen3_thermal: Fix to show correct trip points number
thermal: rcar_thermal: update calculation formula for R-Car Gen3 SoCs
thermal: cpu_cooling: Actually trace CPU load in thermal_power_cpu_get_power
thermal: rockchip: Support the PX30 SoC in thermal driver
dt-bindings: rockchip-thermal: Support the PX30 SoC compatible
thermal: rockchip: fix up the tsadc pinctrl setting error
thermal: broadcom: Remove ACPI support
thermal: Fix build error of missing devm_ioremap_resource on UM
thermal/drivers/cpu_cooling: Remove pointless field
thermal/drivers/cpu_cooling: Add Software Package Data Exchange (SPDX)
thermal/drivers/cpu_cooling: Fixup the header and copyright
thermal/drivers/cpu_cooling: Remove pointless test in power2state()
thermal: rcar_gen3_thermal: disable interrupt in .remove
thermal: rcar_gen3_thermal: fix interrupt type
thermal: Introduce devm_thermal_of_cooling_device_register
...
around because we've finally gotten around to fixing some long standing issues.
There's still work to do though, so this PR is largely laying down the
foundation for all the driver changes to come in the next merge window.
The first problem we're alleviating is how parents of clks are specified. With
the new method, we should see lots of drivers migrate away from the current
design of string comparisons on the entire clk tree to a more direct method
where they can use clk_hw pointers or more localized names specified in DT or
via clkdev. This should reduce our reliance on string comparisons for all the
topology description logic that we've been using for years and hopefully speed
some things up while avoiding problems we have with generating clk names.
Beyond that we also got rid of the CLK_IS_BASIC flag because it wasn't really
helping anyone and we introduced big-endian versions of the basic clk types so
that we can get rid of clk_{readl,writel}(). Both of these are things that
driver developers have tried to use over the years that I typically bat away
during code reviews because they're not useful. It's great to see these two
things go away so maintainers can save time not worrying about these things.
On the driver side we got the usual collection of new SoC support and
non-critical fixes and updates to existing code. The big topics that stand out
are the new driver support for Mediatek MT8183 and MT8516 SoCs, Amlogic Meson8b
and G12a SoCs, and the SiFive FU540 SoC. The other patches in the driver pile
are mostly fixes for things that are being used for the first time or additions
for clks that couldn't be tested before because there wasn't a consumer driver
that exercised them. Details are below and also in the sub-maintainer tags.
Core:
- Remove clk_readl() and introduce BE versions of basic clk types
- Rewrite how clk parents can be specified to allow DT/clkdev lookups
- Removal of the CLK_IS_BASIC clk flag
- Framework documentation updates and fixes
New Drivers:
- Support for STM32F769
- AT91 sam9x60 PMC support
- SiFive FU540 PRCI and PLL support
- Qualcomm QCS404 CDSP clk support
- Qualcomm QCS404 Turing clk support
- Mediatek MT8183 clock support
- Mediatek MT8516 clock support
- Milbeaut M10V clk controller support
- Support for Cirrus Logic Lochnagar clks
Updates:
- Rework AT91 sckc DT bindings
- Fix slow RC oscillator issue on sama5d3
- Mark UFS clk as critical on Hi-Silicon hi3660 SoCs
- Various static analysis fixes/finds and const markings
- Video Engine (ECLK) support on Aspeed SoCs
- Xilinx ZynqMP Versal platform support
- Convert Xilinx ZynqMP driver to be struct oriented
- Fixes for Rockchip rk3328 and rk3288 SoCs
- Sub-type for Rockchip SoCs where mux and divider aren't a single register
- Remove SNVS clock from i.MX7UPL clock driver and bindings
- Improve i.MX5 clock driver for i.MX50 support
- Addition of ADC clock definition for Exynos 5410 SoC (Odroid XU)
- Export a new clock for the MBUS controller on the A13
- Allwinner H6 fixes to support a finer clocking of the video and VPU engines
- Add g12a support in the Amlogic axg audio clock controller
- Add missing PCI USB clock on Rensas RZ/N1
- Add Z2 (Cortex-A53) clocks on Rensas R-Car E3 and RZ/G2E
- A new helper DIV64_U64_ROUND_CLOSEST() in <linux/math64.h>
- VPU and Video Decoder clocks on Amlogic Meson8b
- Finally remove the wrong ABP Meson8b clock id
- Add Video Decoder, PCIe PLL, and CPU Clocks on Amlogic G12A
- Re-expose SAR_ADC_SEL and CTS_OSCIN on Amlogic G12A AO clock controller
- Un-expose some Amlogic AXG-Audio input clocks IDs
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk framework updates from Stephen Boyd:
"We have a couple new features and changes in the core clk framework
this time around because we've finally gotten around to fixing some
long standing issues. There's still work to do though, so this pull
request is largely laying down the foundation for all the driver
changes to come in the next merge window.
The first problem we're alleviating is how parents of clks are
specified. With the new method, we should see lots of drivers migrate
away from the current design of string comparisons on the entire clk
tree to a more direct method where they can use clk_hw pointers or
more localized names specified in DT or via clkdev. This should reduce
our reliance on string comparisons for all the topology description
logic that we've been using for years and hopefully speed some things
up while avoiding problems we have with generating clk names.
Beyond that we also got rid of the CLK_IS_BASIC flag because it wasn't
really helping anyone and we introduced big-endian versions of the
basic clk types so that we can get rid of clk_{readl,writel}(). Both
of these are things that driver developers have tried to use over the
years that I typically bat away during code reviews because they're
not useful. It's great to see these two things go away so maintainers
can save time not worrying about these things.
On the driver side we got the usual collection of new SoC support and
non-critical fixes and updates to existing code. The big topics that
stand out are the new driver support for Mediatek MT8183 and MT8516
SoCs, Amlogic Meson8b and G12a SoCs, and the SiFive FU540 SoC. The
other patches in the driver pile are mostly fixes for things that are
being used for the first time or additions for clks that couldn't be
tested before because there wasn't a consumer driver that exercised
them. Details are below and also in the sub-maintainer tags.
Core:
- Remove clk_readl() and introduce BE versions of basic clk types
- Rewrite how clk parents can be specified to allow DT/clkdev lookups
- Removal of the CLK_IS_BASIC clk flag
- Framework documentation updates and fixes
New Drivers:
- Support for STM32F769
- AT91 sam9x60 PMC support
- SiFive FU540 PRCI and PLL support
- Qualcomm QCS404 CDSP clk support
- Qualcomm QCS404 Turing clk support
- Mediatek MT8183 clock support
- Mediatek MT8516 clock support
- Milbeaut M10V clk controller support
- Support for Cirrus Logic Lochnagar clks
Updates:
- Rework AT91 sckc DT bindings
- Fix slow RC oscillator issue on sama5d3
- Mark UFS clk as critical on Hi-Silicon hi3660 SoCs
- Various static analysis fixes/finds and const markings
- Video Engine (ECLK) support on Aspeed SoCs
- Xilinx ZynqMP Versal platform support
- Convert Xilinx ZynqMP driver to be struct oriented
- Fixes for Rockchip rk3328 and rk3288 SoCs
- Sub-type for Rockchip SoCs where mux and divider aren't a single register
- Remove SNVS clock from i.MX7UPL clock driver and bindings
- Improve i.MX5 clock driver for i.MX50 support
- Addition of ADC clock definition for Exynos 5410 SoC (Odroid XU)
- Export a new clock for the MBUS controller on the A13
- Allwinner H6 fixes to support a finer clocking of the video and VPU engines
- Add g12a support in the Amlogic axg audio clock controller
- Add missing PCI USB clock on Rensas RZ/N1
- Add Z2 (Cortex-A53) clocks on Rensas R-Car E3 and RZ/G2E
- A new helper DIV64_U64_ROUND_CLOSEST() in <linux/math64.h>
- VPU and Video Decoder clocks on Amlogic Meson8b
- Finally remove the wrong ABP Meson8b clock id
- Add Video Decoder, PCIe PLL, and CPU Clocks on Amlogic G12A
- Re-expose SAR_ADC_SEL and CTS_OSCIN on Amlogic G12A AO clock controller
- Un-expose some Amlogic AXG-Audio input clocks IDs"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (172 commits)
clk: Cache core in clk_fetch_parent_index() without names
clk: imx: correct pfdv2 gate_bit/vld_bit operations
clk: sifive: add a driver for the SiFive FU540 PRCI IP block
clk: analogbits: add Wide-Range PLL library
clk: imx: clk-pllv3: mark expected switch fall-throughs
clk: imx8mq: Add dsi_ipg_div
clk: imx: pllv4: add fractional-N pll support
clk: sunxi-ng: Use the correct style for SPDX License Identifier
clk: sprd: Use the correct style for SPDX License Identifier
clk: renesas: Use the correct style for SPDX License Identifier
clk: qcom: Use the correct style for SPDX License Identifier
clk: davinci: Use the correct style for SPDX License Identifier
clk: actions: Use the correct style for SPDX License Identifier
clk: imx: keep uart clock on during system boot
clk: imx: correct i.MX7D AV PLL num/denom offset
dt-bindings: clk: add documentation for the SiFive PRCI driver
clk: stm32mp1: Add ddrperfm clock
clk: Remove CLK_IS_BASIC clk flag
clock: milbeaut: Add Milbeaut M10V clock controller
dt-bindings: clock: milbeaut: add Milbeaut clock description
...
Nex drivers:
- New driver for Bitmain BM1880 pin controller
- New driver for Mediatek MT8516
- New driver for Cirrus Logich Lochnagar PMIC pins
Updates:
- Incremental development on Renesas SH-PFC
- Incremental development on Intel pin controller and some
particular updates for Cedarfork.
- Pin configuration support in Allwinner SunXi drivers
- Suspend/resume support in the NXP/Freescale i.MX8MQ driver
- Support for more packaging of the ST Micro STM32
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Merge tag 'pinctrl-v5.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"It is pretty calm and chill in pin control for the moment. Just
incremental development.
There is an odd patch to the Super-H architecture, it's coming from
the maintainers so should be fine.
Summary:
New drivers:
- Bitmain BM1880 pin controller
- Mediatek MT8516
- Cirrus Logich Lochnagar PMIC pins
Updates:
- Incremental development on Renesas SH-PFC
- Incremental development on Intel pin controller and some particular
updates for Cedarfork.
- Pin configuration support in Allwinner SunXi drivers
- Suspend/resume support in the NXP/Freescale i.MX8MQ driver
- Support for more packaging of the ST Micro STM32"
* tag 'pinctrl-v5.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits)
pinctrl: mcp23s08: Do not complain about unsupported params
pinctrl: Rework Kconfig dependency for BM1880 pinctrl driver
MAINTAINERS: Add entry for BM1880 pinctrl
pinctrl: Add pinctrl support for BM1880 SoC
dt-bindings: pinctrl: Add BM1880 pinctrl binding
pinctrl: stm32: check irq controller availability at probe
pinctrl: mediatek: Add MT8516 Pinctrl driver
pinctrl: zte: fix leaked of_node references
pinctrl: intel: Increase readability of intel_gpio_update_pad_mode()
pinctrl: intel: Retain HOSTSW_OWN for requested gpio pin
pinctrl: pistachio: fix leaked of_node references
pinctrl: sunxi: Support I/O bias voltage setting on H6
pinctrl: sunxi: Prepare for alternative bias voltage setting methods
pinctrl: st: fix leaked of_node references
pinctrl: samsung: fix leaked of_node references
pinctrl: stm32: align stm32mp157 pin names
pinctrl: stm32: add package information for stm32mp157c
pinctrl: stm32: introduce package support
dt-bindings: pinctrl: stm32: add new entry for package information
pinctrl: imx8mq: Add suspend/resume ops
...
Here is the big set of USB and PHY driver patches for 5.2-rc1
There is the usual set of:
- USB gadget updates
- PHY driver updates and additions
- USB serial driver updates and fixes
- typec updates and new chips supported
- mtu3 driver updates
- xhci driver updates
- other tiny driver updates
Nothing really interesting, just constant forward progress.
All of these have been in linux-next for a while with no reported
issues. The usb-gadget and usb-serial trees were merged a bit "late",
but both of them had been in linux-next before they got merged here last
Friday.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Merge tag 'usb-5.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
Pull USB/PHY updates from Greg KH:
"Here is the big set of USB and PHY driver patches for 5.2-rc1
There is the usual set of:
- USB gadget updates
- PHY driver updates and additions
- USB serial driver updates and fixes
- typec updates and new chips supported
- mtu3 driver updates
- xhci driver updates
- other tiny driver updates
Nothing really interesting, just constant forward progress.
All of these have been in linux-next for a while with no reported
issues. The usb-gadget and usb-serial trees were merged a bit "late",
but both of them had been in linux-next before they got merged here
last Friday"
* tag 'usb-5.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (206 commits)
USB: serial: f81232: implement break control
USB: serial: f81232: add high baud rate support
USB: serial: f81232: clear overrun flag
USB: serial: f81232: fix interrupt worker not stop
usb: dwc3: Rename DWC3_DCTL_LPM_ERRATA
usb: dwc3: Fix default lpm_nyet_threshold value
usb: dwc3: debug: Print GET_STATUS(device) tracepoint
usb: dwc3: Do core validation early on probe
usb: dwc3: gadget: Set lpm_capable
usb: gadget: atmel: tie wake lock to running clock
usb: gadget: atmel: support USB suspend
usb: gadget: atmel_usba_udc: simplify setting of interrupt-enabled mask
dwc2: gadget: Fix completed transfer size calculation in DDMA
usb: dwc2: Set lpm mode parameters depend on HW configuration
usb: dwc2: Fix channel disable flow
usb: dwc2: Set actual frame number for completed ISOC transfer
usb: gadget: do not use __constant_cpu_to_le16
usb: dwc2: gadget: Increase descriptors count for ISOC's
usb: introduce usb_ep_type_string() function
usb: dwc3: move synchronize_irq() out of the spinlock protected block
...
- Mark UFS clk as critical on Hi-Silicon hi3660 SoCs
- Support for Cirrus Logic Lochnagar clks
* clk-hisi:
clk: hi3660: Mark clk_gate_ufs_subsys as critical
* clk-lochnagar:
clk: lochnagar: Add support for the Cirrus Logic Lochnagar
clk: lochnagar: Add initial binding documentation
* clk-allwinner:
clk: sunxi-ng: sun5i: Export the MBUS clock
clk: sunxi-ng: a83t: Add pll-video0 as parent of csi-mclk
clk: sunxi-ng: h6: Allow video & vpu clocks to change parent rate
clk: sunxi-ng: h6: Preset hdmi-cec clock parent
clk: sunxi: Add Kconfig options
clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset
clk: sunxi-ng: Allow DE clock to set parent rate
* clk-rockchip:
clk: rockchip: undo several noc and special clocks as critical on rk3288
clk: rockchip: add a COMPOSITE_DIV_OFFSET clock-type
clk: rockchip: Turn on "aclk_dmac1" for suspend on rk3288
clk: rockchip: Limit use of USB PHY clock to USB on rk3288
clk: rockchip: Fix video codec clocks on rk3288
clk: rockchip: Make rkpwm a critical clock on rk3288
clk: rockchip: fix wrong clock definitions for rk3328
* clk-qoriq:
clk: qoriq: increase array size of cmux_to_group
dt-bindings: qoriq-clock: Add ls1028a chip compatible string
clk: qoriq: Add ls1028a clock configuration
clk: qoriq: add more PLL divider clocks support
dt-bindings: qoriq-clock: add more PLL divider clocks support
- Remove clk_readl() and introduce BE versions of basic clk types
* clk-doc:
clk: Drop duplicate clk_register() documentation
clk: Document and simplify clk_core_get_rate_nolock()
clk: Remove 'flags' member of struct clk_fixed_rate
clk: nxp: Drop 'flags' on fixed_rate clk macro
clk: Document __clk_mux_determine_rate()
clk: Document CLK_MUX_READ_ONLY mux flag
clk: Document deprecated things
clk: Collapse gpio clk kerneldoc
* clk-more-critical:
clk: highbank: Convert to CLK_IS_CRITICAL
* clk-meson: (21 commits)
clk: meson: axg-audio: add g12a support
clk: meson: axg-audio: don't register inputs in the onecell data
clk: meson: axg_audio: replace prefix axg by aud
dt-bindings: clk: axg-audio: add g12a support
clk: meson: meson8b: add the video decoder clock trees
clk: meson: meson8b: add the VPU clock trees
clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2
clk: meson: meson8b: use a separate clock table for Meson8m2
dt-bindings: clock: meson8b: export the video decoder clocks
clk: meson-g12a: add video decoder clocks
dt-bindings: clock: meson8b: export the VPU clock
clk: meson-g12a: add PCIE PLL clocks
dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCIN
clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLL
dt-bindings: clock: meson8b: drop the "ABP" clock definition
clk: meson: g12a: add cpu clocks
dt-bindings: clk: g12a-clkc: add VDEC clock IDs
dt-bindings: clock: axg-audio: unexpose controller inputs
dt-bindings: clk: g12a-clkc: add PCIE PLL clock ID
clk: g12a-aoclk: re-export CLKID_AO_SAR_ADC_SEL clock id
...
* clk-basic-be:
clk: core: replace clk_{readl,writel} with {readl,writel}
clk: core: remove powerpc special handling
powerpc/512x: mark clocks as big endian
clk: mux: add explicit big endian support
clk: multiplier: add explicit big endian support
clk: gate: add explicit big endian support
clk: fractional-divider: add explicit big endian support
clk: divider: add explicit big endian support
We need this to make the usb-gadget branch merge cleaner. And for
testing to keep from hitting the same issues already fixed.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This series of changes adds a new pinmux instance defines for am335x,
and a new AM33XX_PADCONF macro. And then the rest of the series updates
the dts files to use it.
The reasons for doing this is the pinmux configuration has been hard to
use and read. And we need to do this for eventually for moving to use
values.
This change is done one machine at a time, and can be easily reverted
as needed in case of unexpected trouble. The old macro is still working,
and we're planning to keep it around until we eventually change to use
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Merge tag 'omap-for-v5.2/dt-am3-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt
Add am335x pinmux defines and start using them
This series of changes adds a new pinmux instance defines for am335x,
and a new AM33XX_PADCONF macro. And then the rest of the series updates
the dts files to use it.
The reasons for doing this is the pinmux configuration has been hard to
use and read. And we need to do this for eventually for moving to use
values.
This change is done one machine at a time, and can be easily reverted
as needed in case of unexpected trouble. The old macro is still working,
and we're planning to keep it around until we eventually change to use
* tag 'omap-for-v5.2/dt-am3-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (38 commits)
ARM: dts: am335x: wega: Replaced register offsets with defines
ARM: dts: am335x: sl50: Replaced register offsets with defines
ARM: dts: am335x: shc: Replaced register offsets with defines
ARM: dts: am335x: sbc-t335: Replaced register offsets with defines
ARM: dts: am335x: sancloud-bbe: Replaced register offsets with defines
ARM: dts: am335x: phycore-som: Replaced register offsets with defines
ARM: dts: am335x: pepper: Replaced register offsets with defines
ARM: dts: am335x: pdu001: Replaced register offsets with defines
ARM: dts: am335x: pcm-953: Replaced register offsets with defines
ARM: dts: am335x: osd335x-common: Replaced register offsets with defines
ARM: dts: am335x: osd3358-sm-red: Replaced register offsets with defines
ARM: dts: am335x: nano: Replaced register offsets with defines
ARM: dts: am335x: moxa-uc-8100-me-t: Replaced register offsets with defines
ARM: dts: am335x: moxa-uc-2101: Replaced register offsets with defines
ARM: dts: am335x: moxa-uc-2100-common: Replaced register offsets with defines
ARM: dts: am335x: lxm: Replaced register offsets with defines
ARM: dts: am335x: igep0033: Replaced register offsets with defines
ARM: dts: am335x: icev2: Replaced register offsets with defines
ARM: dts: am335x: evmsk: Replaced register offsets with defines
ARM: dts: am335x: evm: Replaced register offsets with defines
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Add binding documentation of apmixedsys for MT8516 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add binding documentation of infracfg for MT8516 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add binding documentation of topckgen for MT8516 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
STM32F769 clocks are derived from STM32746 clocks.
main differences are:
- new source clock for SAI1 and SAI2 (HSI or HSE)
- Add DFSDM & DSI clocks
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
AM654x has two SERDES instances. Each instance has three input clocks
(left input, externel reference clock and right input) and two output
clocks (left output and right output) in addition to a PLL mux clock
which the SERDES uses for Clock Multiplier Unit (CMU refclock).
The PLL mux clock can select from one of the three input clocks.
The right output can select between left input and external reference
clock while the left output can select between the right input and
external reference clock.
The left and right input reference clock of SERDES0 and SERDES1
respectively are connected to the SoC clock. In the case of two lane
SERDES personality card, the left input of SERDES1 is connected to
the right output of SERDES0 in a chained fashion.
See section "Reference Clock Distribution" of AM65x Sitara Processors
TRM (SPRUID7 – April 2018) for more details.
Add dt-binding documentation in order to represent all these different
configurations in device tree.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Add macro for the UDC PHY clock of the JZ4725B.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add devicetree binding for the turing clock controller found in QCS404.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Linus Torvalds
Thomas Gleixner
Jerome Brunet
Wei Ni
Stephen Boyd
Greg Kroah-Hartman
Olof Johansson
Fabien Parent
Gabriel Fernandez
Alexandre Torgue
Kishon Vijay Abraham I
Kevin Hilman
Paul Cercueil
Bjorn Andersson