Граф коммитов

55679 Коммитов

Автор SHA1 Сообщение Дата
Alex Deucher d7929c1e13 Merge branch 'drm-next' into drm-next-5.3
Backmerge drm-next and fix up conflicts due to drmP.h removal.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-25 08:42:25 -05:00
Brian Masney 648fdc3f64 drm/msm: add dirty framebuffer helper
Use drm_atomic_helper_dirtyfb() as the dirty callback in the
msm_framebuffer_funcs struct. Call drm_plane_enable_fb_damage_clips()
when the planes are initialized in mdp4, mdp5, and dpu1.

Signed-off-by: Brian Masney <masneyb@onstation.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-06-25 05:29:59 -07:00
Andres Rodriguez 80d42db02b drm/edid: use for_each_displayid_db where applicable
Replace the duplicated versions of the while loop with the new macro.

Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190619183033.6922-1-andresx7@gmail.com
2019-06-25 14:44:03 +10:00
Andres Rodriguez e28ad544f4 drm/edid: parse CEA blocks embedded in DisplayID
DisplayID blocks allow embedding of CEA blocks. The payloads are
identical to traditional top level CEA extension blocks, but the header
is slightly different.

This change allows the CEA parser to find a CEA block inside a DisplayID
block. Additionally, it adds support for parsing the embedded CTA
header. No further changes are necessary due to payload parity.

This change fixes audio support for the Valve Index HMD.

Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: <stable@vger.kernel.org> # v4.15
Signed-off-by: Dave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190619180901.17901-1-andresx7@gmail.com
2019-06-25 14:32:26 +10:00
Dave Airlie dfd03396d7 drm/tegra: Changes for v5.3-rc1
This contains a couple of small improvements and cleanups for the Tegra
 DRM driver.
 -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl0M8jsTHHRyZWRpbmdA
 bnZpZGlhLmNvbQAKCRDdI6zXfz6zoU0MEACZhCSKLvinuCw2pWdsc2A5rZN3r0Mr
 9TpdIKXYwcHO2G2gYC1mXv0wlp2pzIOr5y3VHLl1VboWXlPZjvgH0OiDtmwZk/vU
 jjFOGZO5ZjwyVNAZ8SlQrpdBNIAm3wseVfrhVURIL+9dANDgXsxWiqTkgnEmVclZ
 Kj2SpXfysTM9TJyXfQW8op6jKtP3NJ/IPEtTguNL1R9ho0phlcRYBUMEIYqtgBVE
 aRsjrrbM27OGf+JFPY3C7bW90hzgVqZLeK9R4AAMPS8iZ91k9njlFZ20LI9Yk/P1
 GBVyemiRtcG3owbli3NlfFzaeNjmM2PmcMZJsOyf6T+UH5juH2XZ/TV5O6i/jq0z
 /8DWsuFdEMX5tdP0t4B3vnbGQTYMOo/6bRsZHceLXcpKFNuJcC6lY233/Fc3D1bw
 gWm5ZHTs3SmPm2JoWmA54h2oiXU8/hGiPZGoUDHUTxf/h7DOGhK2hfaNdB6ZYXJu
 be4yS5TidFlFKi911JuXblCDeFf0VPsOfemQtJW4OvKg9FD6WmRuehYPytJ8ifB1
 dByXh5siOVMcyE0a2bsMPAvsxK6z4pPwyDz34AJUETJ0DSmSfWeEMSbCmpJwt6m5
 35IiMossSULJXWjqtc5bcK1gmbYMJSEwj+Xe33O+H67THSgo4GLxqKdb++5QK5Ky
 svluhQIjYYx3pw==
 =T2hU
 -----END PGP SIGNATURE-----

Merge tag 'drm/tegra/for-5.3-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next

drm/tegra: Changes for v5.3-rc1

This contains a couple of small improvements and cleanups for the Tegra
DRM driver.

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Thierry Reding <thierry.reding@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190621150753.19550-1-thierry.reding@gmail.com
2019-06-25 12:59:43 +10:00
Dave Airlie 9b75276e4f Merge commit 'refs/for-upstream/mali-dp' of git://linux-arm.org/linux-ld into drm-next
Picking up pace on the upstreaming of Komeda driver, with quite a lot
of new features added this time. On top of that we have the small
cleanups and improved usage of the debugfs functions. Please pull!

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Liviu Dudau <Liviu.Dudau@arm.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190621095349.GI17204@e110455-lin.cambridge.arm.com
2019-06-25 12:56:40 +10:00
Rob Clark f47bee2ba4 drm/msm/a3xx: remove TPL1 regs from snapshot
These regs are write-only, and the hw throws a hissy-fit (ie. reboots)
when we try to read them for GPU state snapshot, in response to a GPU
hang.  It is rather impolite when GPU recovery triggers an insta-
reboot, so lets remove the TPL1 registers from the snapshot.

Fixes: 7198e6b031 drm/msm: add a3xx gpu support
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>
2019-06-24 09:28:55 -07:00
tiancyin 8ac875db0f drm/amdgpu: disable gfxoff on navi10
The gfxoff brings unstability, disable it by default

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: tiancyin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-24 09:31:43 -05:00
Hawking Zhang 73c86d628d drm/amdgpu: fix modprobe failure for uvd_4/5/6
For uvd_4/5/6, amdgpu driver will only power on them when
there are jobs assigned to decode/enc rings.uvd_4/5/6 dpm was broken
since amdgpu_dpm_set_powergating_by_smu only covers gfx block.

The change would add more IP block support in amdgpu_dpm_set_powergating_by_smu
For GFX/UVD/VCN/VCE, if the new SMU driver is supported, invoke new
power gate helper function smu_dpm_set_power_gate, otherwise, fallback to
legacy powerplay helper function pp_set_powergating_by_smu. For other IP blocks
always invoke legacy powerplay helper function.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tianci Yin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-24 09:29:59 -05:00
Suzuki K Poulose 92ce7e83b4 driver_find_device: Unify the match function with class_find_device()
The driver_find_device() accepts a match function pointer to
filter the devices for lookup, similar to bus/class_find_device().
However, there is a minor difference in the prototype for the
match parameter for driver_find_device() with the now unified
version accepted by {bus/class}_find_device(), where it doesn't
accept a "const" qualifier for the data argument. This prevents
us from reusing the generic match functions for driver_find_device().

For this reason, change the prototype of the driver_find_device() to
make the "match" parameter in line with {bus/class}_find_device()
and adjust its callers to use the const qualifier. Also, we could
now promote the "data" parameter to const as we pass it down
as a const parameter to the match functions.

Cc: Corey Minyard <minyard@acm.org>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: "Rafael J. Wysocki" <rafael@kernel.org>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Peter Oberparleiter <oberpar@linux.ibm.com>
Cc: Sebastian Ott <sebott@linux.ibm.com>
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: Nehal Shah <nehal-bakulchandra.shah@amd.com>
Cc: Shyam Sundar S K <shyam-sundar.s-k@amd.com>
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-24 05:22:31 +02:00
Suzuki K Poulose 418e3ea157 bus_find_device: Unify the match callback with class_find_device
There is an arbitrary difference between the prototypes of
bus_find_device() and class_find_device() preventing their callers
from passing the same pair of data and match() arguments to both of
them, which is the const qualifier used in the prototype of
class_find_device().  If that qualifier is also used in the
bus_find_device() prototype, it will be possible to pass the same
match() callback function to both bus_find_device() and
class_find_device(), which will allow some optimizations to be made in
order to avoid code duplication going forward.  Also with that, constify
the "data" parameter as it is passed as a const to the match function.

For this reason, change the prototype of bus_find_device() to match
the prototype of class_find_device() and adjust its callers to use the
const qualifier in accordance with the new prototype of it.

Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Andreas Noever <andreas.noever@gmail.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Corey Minyard <minyard@acm.org>
Cc: Christian Borntraeger <borntraeger@de.ibm.com>
Cc: David Kershner <david.kershner@unisys.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: David Airlie <airlied@linux.ie>
Cc: Felipe Balbi <balbi@kernel.org>
Cc: Frank Rowand <frowand.list@gmail.com>
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Cc: Harald Freudenberger <freude@linux.ibm.com>
Cc: Hartmut Knaack <knaack.h@gmx.de>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Jason Gunthorpe <jgg@ziepe.ca>
Cc: Jonathan Cameron <jic23@kernel.org>
Cc: "James E.J. Bottomley" <jejb@linux.ibm.com>
Cc: Len Brown <lenb@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Michael Jamet <michael.jamet@intel.com>
Cc: "Martin K. Petersen" <martin.petersen@oracle.com>
Cc: Peter Oberparleiter <oberpar@linux.ibm.com>
Cc: Sebastian Ott <sebott@linux.ibm.com>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: Yehezkel Bernat <YehezkelShB@gmail.com>
Cc: rafael@kernel.org
Acked-by: Corey Minyard <minyard@acm.org>
Acked-by: David Kershner <david.kershner@unisys.com>
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Acked-by: Wolfram Sang <wsa@the-dreams.de> # for the I2C parts
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-24 05:22:31 +02:00
Alex Deucher f3f48d7331 drm/amdgpu: drop unused df init callback
It was replaced with the sw_init callback so is no longer
needed.

Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:14 -05:00
Jonathan Kim 8f78f1b03e drm/amdgpu: add sw_init to df_v1_7
change df_init to df_sw_init df 1.7 to prevent regression issues on pre-vega20
products when callback is called in sw_common_sw_init.

Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:14 -05:00
Oak Zeng d9848e149d drm/amdkfd: Set gws_mask to 64 bit 1s
Previous kfd doesn't use gws so this mask was set to 0.
Set it to 64 bit 1s because now kfd can use all 64 gws
resources.

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:14 -05:00
hersen wu 9cbee6eff8 drm/amd/display/dc: set num-dwb = 1 as navi10 asic cap
during navi10 bring up, dwb causes system hang.
to continue debug major issue, disable dwb by
set num-dwb = 0. the hang issue is not reproduced now
by enable num-dwb =1. dc source is shared by all os.
win needs num-dwb = 1.

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:14 -05:00
Su Sung Chung 170a2398d2 drm/amd/display: make clk_mgr call enable_pme_wa
[why]
Before for raven and navi we are calling pp_smu functions for pme

[how]
refactor a code so we will call clk_mgr's enable_pme_wa function so we
can use pme_wa for future asics. This way we don't need to worry about
different ASIC since clk_mgr already have that information

Signed-off-by: Su Sung Chung <Su.Chung@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:14 -05:00
Charlene Liu 7a5ab155d3 drm/amd/display: expose dentist_get_did_from_divider
for future use

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:14 -05:00
Dmytro Laktyushkin c00d56fede drm/amd/display: add missing mod_vmid destructor
mod_vmid is missing a destructor.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:14 -05:00
Thomas Lim 1a7d296d16 drm/amd/display: Add Underflow Asserts to dc
[Why]
For debugging underflow issues it can be useful to have asserts when the
underflow initially occurs.

[How]
Read the underflow status registers after actions that have a high risk
of causing underflow and assert that no underflow occurred. If underflow
occurred, clear the bit.

Signed-off-by: Thomas Lim <Thomas.Lim@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:14 -05:00
Dmytro Laktyushkin bda9afdacf drm/amd/display: move vmid determination logic to a module
Currently vmid is decided internally inside dc. With the introduction
of new asics we are required to coordinate vmid use with external
components.

This change converts vmid logic to a DAL module allowing vmid to be
passed in as a parameter to DC.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:14 -05:00
Charlene Liu a6465d1f3b drm/amd/display: dcn2 use fixed clocks.
[Description]
dcn2 use fixed clocks and not program DPP CLK or Disp_CLK.

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:14 -05:00
Charlene Liu 971ff2b433 drm/amd/display: add p010 and ayuv plane caps
for future use

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:14 -05:00
Jun Lei 6e17b5b8a8 drm/amd/display: update DCN2 uclk switch time
[why]
value commited to by HW team is going to be higher
than pre-silicon, and will cause underflow if driver not
updated

[how]
update hardcoded value, update pstate switching logic
to fix case where with long uclk time we won't allow switch
even when we should

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:14 -05:00
Nicholas Kazlauskas cf020d49b3 drm/amd/display: Rework CRTC color management
[Why]
To prepare for the upcoming DRM plane color management properties
we need to correct a lot of wrong behavior and assumptions made for
CRTC color management.

The documentation added by this commit in amdgpu_dm_color explains
how the HW color pipeline works and its limitations with the DRM
interface.

The current implementation does the following wrong:
- Implicit sRGB DGM when no CRTC DGM is set
- Implicit sRGB RGM when no CRTC RGM is set
- No way to specify a non-linear DGM matrix that produces correct output
- No way to specify a correct RGM when a linear DGM is used

We had workarounds for passing kms_color tests but not all of the
behavior we had wrong was covered by these tests (especially when
it comes to non-linear DGM). Testing both DGM and RGM at the same time
isn't something kms_color tests well either.

[How]
The specifics for how color management works in AMDGPU and the new
behavior can be found by reading the documentation added to
amdgpu_dm_color.c from this patch.

All of the incorrect cases from the old implementation have been
addressed for the atomic interface, but there still a few TODOs for
the legacy one.

Note: this does cause regressions for kms_color@pipe-a-ctm-* over HDMI.

The result looks correct from visual inspection but the CRC no longer
matches. For reference, the test was previously doing the following:

linear degamma -> CTM -> sRGB regamma -> RGB to YUV (709) -> ...

Now the test is doing:

linear degamma -> CTM -> linear regamma -> RGB to YUV (709) -> ...

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:13 -05:00
Wesley Chalmers 043f5bb630 drm/amd/display: Use macro for invalid OPP ID
[WHY]
This is meant to make it clearer that 0xf is not a valid OPP ID, and
that code making use of OPP IDs should not accept this value.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:13 -05:00
Eric Bernstein c5509aadcf drm/amd/display: expose enable dp output functions
expose this function for future use

Implementation of DCN3 DIO Link Encoder including
dpcs register headers.

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:13 -05:00
Charlene Liu a6132cb102 drm/amd/display: add dwb stere caps and version
add dwb stereo caps and ver for future use

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:13 -05:00
Eric Bernstein 779451a736 drm/amd/display: Alpha plane type
Add Alpha surface type for future use

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:13 -05:00
Jun Lei 5d36f78311 drm/amd/display: making DCN20 WM table non-overlapping
[why]
Existing behavior has overlapping ranges resulting in path
dependent SMU selection

[how]
Make ranges non-overlapping, resulting in non-path dependent
selection

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:13 -05:00
Wenjing Liu e710fdb134 drm/amd/display: update dsc max_target_bpp to 16 bpp
[why]
According to the latest specs, the max_target bpp sink
can support is 16 bpp.

[how]
update dsc max_target_bpp to 16

Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:13 -05:00
Charlene Liu f82c916c41 drm/amd/display: add some parameters to validate bandwidth functions
required for new checks.

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:13 -05:00
Wenjing Liu 39a4eb853f drm/amd/display: update DSC MST DP virtual DPCD peer device enumeration policy
[why]
Current policy assumes virtual DPCD peer device as
an individual MST branch device with 1 input and 1 output.
However this is only true for virtual DP-to-DP peer device.
In general there are three types of virtual DP peer devices.
1. Sink peer device with virtual DPCD.
2. Virtual DP-to-DP Peer device with virtual DPCD.
3. Virtual DP-to-HDMI Protocol Converter Peer Device with
Virtual DPCD.
So we should break the assumption and handle all three types.

[how]
DP-to-DP peer device will have virtual DPCD cap upstream.
Sink peer device will have virtual DPCD on the logical port.
Dp to HDMI protocol converter peer device will have virtual DPCD
on its converter port.
For DSC capable Synaptics non VGA port we workaround by enumerating
a virutal DPCD peer device on its upstream
even if it doesn't have one.

Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:13 -05:00
Jun Lei 2131f65581 drm/amd/display: add support for forcing DCFCLK without affecting watermarks
[why]
useful for debugging

[how]
plumb a debug option in dc

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:13 -05:00
Nicholas Kazlauskas 6f4992b0e2 drm/amd/display: Copy stream updates onto streams
[Why]
Almost every function in DC that works with stream state expects that
the current state on the stream is the one that it should be writing
out. These functions are typically triggered by specifying a particular
stream update - but the actual contents of the stream update itself
are ignored, leaving it to the DM to actually update the stream state
itself.

The problem with doing this in DM is a matter of timing. On Linux
most of this is incorrectly done in atomic check, when we actually want
it to be done during atomic commit tail while access to DC is locked.

To give an example, a commit requesting to modify color management
state for DM could come in, be rejected, but still have modified
the actual system state for the stream since it's shared memory. The
next time color management gets programmed it'll use the rejected
color management info - which might not even still be around if it's
a custom transfer function.

So a reasonable place to perform this is within DC itself and this is
the model that's currently in use for surface updates. DC can even
compare the current system state to the incoming surface update to
determine update level, something that can't currnetly be done with the
framework for stream updates.

[How]
Duplicate the framework used for surface updates for stream updates
as well. Copy all the updates after checking the update type.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:13 -05:00
Ilya Bakoulin 4f008d931b drm/amd/display: Fix incorrect vba type
SwathWidthCThisState is expected to be an unsigned int array.

Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:13 -05:00
Martin Leung d8cd587d2b drm/amd/display: removing MODULO change for dcn2
[why]
when resetting pipes from 480p to dual-pipe 8k, modulo reg write for
video optimized rate updated one pipe without changing the other, causing
sync error

[how]
removed code from dcn2

Signed-off-by: Martin Leung <martin.leung@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:13 -05:00
Ilya Bakoulin 03fd87db6d drm/amd/display: Fix incorrect DML output_bpp value
[Why]
The output_bpp pipe parameter was assigned an incorrect value
(color depth enum), and subsequently used to overwrite
the OutputBpp parameter calculated by DML. Seems like this had no
effect except with DSC enabled, which would make DML produce
bad outputs.

[How]
Removed assignment to OutputBpp, fixed output_bpp assignment,
and properly set ForcedOutputLinkBPP instead of OutputBpp.
Also removed condition in DML that prevented forcing of
Output BPP with DSC enabled.

Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:13 -05:00
Jun Lei 3979efcec6 drm/amd/display: Add missing VM conversion from hw values
[why]
VM implemenation is missing conversion from HW values in hubbub
DM not passing actual PTB during flip

[how]
add proper HW conversion from logical values
fix cases where we programmed VA even though we are in PA
plumb in PTB from DM

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:13 -05:00
Ilya Bakoulin a746a25855 drm/amd/display: Drive-by fixes for display_mode_vba
Fixes for the following:
- Incorrect pointer type (unsigned int instead of double)
- Incorrect DSC number of slices setting

Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:13 -05:00
Nikola Cornij 98ce8cc1b4 drm/amd/display: Enable DSC power-gating for DSC streams
[why]
Currently DSC power gating is disabled by default because the power
transition doesn't happen, causing a crash on some systems

[how]
Fix the lack of power state transition and enable DSC power gating
by default.

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:12 -05:00
Charlene Liu c3ec8ba537 drm/amd/display: Return UPDATE_TYPE_FULL on writeback update
Should do full update when display writeback is updated.

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Duke Du <Duke.Du@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:12 -05:00
Wenjing Liu ba32c50f04 drm/amd/display: decouple dsc adjustment out of enablement
[why]
dsc adjustment is allowed via stream update sequence.
dsc enablement is only allowed via commit stream sequence.
with the current unified dsc set function, it is hard
to determine which sequence it is called by.
The solution is to decouple dsc adjustment out of enablement
sequence so we can handle them separately.

[how]
decouple dsc adjustment out of enablement.

Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:12 -05:00
Jun Lei 1621f4c417 drm/amd/display: always use 4 dp lanes for dml
[why]
current DML logic uses currently trained setting for number
of dp lanes in DML calculations.  this is obviously flawed since
just because 1 lane is in use doesn't mean only 1 lane can be used

this causes mode validation to fail depending on current state,
which is incorrect

[how]
DML should always assume 4 lanes are available.  validation of
bandwidth is not supposed to be handled by DML, since we do
link validation without DML already

also, DML is expecting there to be a copy of the max state, this
state is removed when update_bounding_box is called to update
actual SKU clocks.  fix this as well by duping last state.

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Eric Yang <eric.yang2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:12 -05:00
Wesley Chalmers 278141f58e drm/amd/display: Use DCN2 functions instead of DCE
[WHY]
DCN code should make as few references to DCE as possible

[HOW]
Copy DCE110 implementation of find_first_free_match_stream_enc_for_link
into DCN10

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:12 -05:00
Wesley Chalmers 6936c8b1d4 drm/amd/display: DCN2 Engine-specifc encoder allocation
[WHY]
From DCE110 onward, we have the ability to assign DIG BE and FE
separately for any display connector type; before, we could only do this
for DP.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:12 -05:00
Nikola Cornij b5d71c9396 drm/amd/display: Disable DSC power gating in Diags
[why]
With DSC power gating enabled, one of the register reads times out occasionally,
causing a DSC test to fail.

[how]
Disable DSC power gating in Diags.
NOTE: This has to be reverted once the problems with DSC power gating are
resolved.

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:12 -05:00
Joshua Aberback 324707fdf8 drm/amd/display: Set test pattern on blank when using Visual Confirm
[Why]
We want a test pattern to show up on screen when we're blanked and have
visual confirm enabled, for debugging. Raven does this, it's a mistake that
Navi does not.

[How]
 - in "blank_pixel_data", set appropriate DPG pattern for visual confirm
 - refactor DPG calls out of "enable_stream_timing"

Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:12 -05:00
Dmytro Laktyushkin ad141db915 drm/amd/display: add null checks and set update flags for DCN2
* add plane state null checks
* add and set update surface flags

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:12 -05:00
Tyler DiBattista 9796b71318 drm/amd/display: move DWB structs and enums to dc_hw_types
[Why]
these enums/structs will be used more generically in the future
so moving it to dc_hw_types and dc_types

Signed-off-by: Tyler DiBattista <tyler.dibattista@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:12 -05:00
Vitaly Prosyak f99b6f4f21 drm/amd/display: Integrate color transform3x4 with 3dlut tm
[Why & How]
Reuse existent code path (dcn1+) and in order to do that apply de gamma
in 1D blender LUT and re use MPC OGAM.
Follow up is required.

Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Vitaly Prosyak <Vitaly.Prosyak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:12 -05:00
Charlene Liu 8bb3d7e7b5 drm/amd/display: used optimum VSTARTUP instead of MaxVStartup
[Description]
Features that are desirable for minimizing the Global Sync Period:
DRR and lateflip

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:12 -05:00
Wenjing Liu 09104d151a drm/amd/display: add dsc_passthrough_support bit in dpcd struct
Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:12 -05:00
Wenjing Liu cba4d59c93 drm/amd/display: fix a potential issue in DSC logic
[why]
In compute dsc bandwidth range there is an uninitialized variable

[how]
Initialize the variable to the correct value.

Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:12 -05:00
Leo (Hanghong) Ma e34fe1bba6 drm/amd/display: Expose send immediate sdp message interface
[Why]
To send sdp message immediately from a single slot.

[How]
Modify the generic SDP message interface, and use GSP4 to send immediate
sdp message.

Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:12 -05:00
Ilya Bakoulin ed07237c0c drm/amd/display: Fix LB BPP and Cursor width
DCN2.0 LB BPP should be 48 or 16BPC and max cursor width should be 256.

Also use populate_dml_pipes as functions pointer instead of using it directly

Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:12 -05:00
Dmytro Laktyushkin b964e79064 drm/amd/display: fix macro_tile_size for tiling
A regression was introduced when we set correct tile size
for the gfx9 swizzle mode. This resulted in incorrect
macro tile size.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:12 -05:00
Joshua Aberback 97ae9b9675 drm/amd/display: Remove OPP clock programming on plane disable
[Why]
Plane disable gets calls when we enable blank. On DCN2, we blank by using
DPG to display a black colour instead of using OTG blank. DPG runs off the
OPP clock, therefore we shouldn't disable the OPP clock when disabling the
plane. We do need to disable the OPP clock when disabling the entire pipe,
that will be addressed in a separate commit.

Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:11 -05:00
Dmytro Laktyushkin 02ce5a799a drm/amd/display: fix odm mpo disable
It looks like mpo isn't properly disabled during odm, this change is
meant to fix that.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:11 -05:00
Charlene Liu 72c6473a6a drm/amd/display: [backport] dwb dm + efc support
dwb fixes.

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Duke Du <Duke.Du@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:11 -05:00
Charlene Liu bb21290ff6 drm/amd/display: Create DWB resource for DCN2
[Description]
dcn20 has num_dwb =1 in the res cap, but not created.

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Duke Du <Duke.Du@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:11 -05:00
Aric Cyr 6bd8d7d3f7 drm/amd/display: Intermittent DCN2 pipe hang on mode change
[Why]
GSL is being used to synchronize pipes when vsync is off but
on transition to vsync on during a mode change GSL is not
being reset correctly.

[How]
Disable GSL on any plane that is disabled.

Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:11 -05:00
Nikola Cornij f446489adc drm/amd/display: Add support for extended DSC DPCD caps
[why]
A few of the new DSC DPCD caps were introduced by a DP 1.4a SCR in order
to give DSC branch decoders a chance to expose their maximum throughput
and maximum line width limitations.

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:11 -05:00
Nikola Cornij ce76898527 drm/amd/display: Do a reg update instead of set when writing ODM color format
[why]
If a set is done, DSC settings are zeroed out, leading to no DSC for the modes
that require ODM, such as 8k60.

This was a regression introduced by 5a4f26295176bbfc776c75aaf0f6dd8ccf806958.

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:11 -05:00
Vitaly Prosyak 97516065a0 drm/amd/display: add flags for gamut map library
[Why & How]
Gamut map lib provides a wider gamut mapping options
vs BT2390

Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Vitaly Prosyak <Vitaly.Prosyak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:11 -05:00
Samson Tam 796c9ece2e drm/amd/display: block passive dongle EDID Emulation for USB-C ports
[Why]
Emulating passive dongle on USB-C port causes issue on some asics.

[How]
Check for DP_IS_USB_C flag in bios parser and propagate it to
encoder features flags. If DP_IS_USB_C flag is set and it is trying to
emulate passive dongle, then return fail.

Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:11 -05:00
Yongqiang Sun 040a4d63bd drm/amd/display: DCHUB requestors numbers for Navi.
[Why]
The DCHub arbiter has a mechanism to dynamically rate limit the DCHub
request stream to the fabric. If the memory controller is fully utilized
and the DCHub requestors are well ahead of their amortized schedule,
then it is safe to prevent the next winner from being committed and sent
to the fabric. The utilization of the memory controller is approximated
by ensuring that the number of outstanding requests is greater than a
threshold specified by the ARB_MIN_REQ_OUTSTANDING. To determine that
the DCHub requestors are well ahead of the amortized schedule, the slack
of the next winner is compared with the ARB_SAT_LEVEL in DLG RefClk
cycles.

[How]
The recommended settings to enable thise dynamic limiting for Navi is
180 requests.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:11 -05:00
Nikola Cornij d7cd0e053b drm/amd/display: Add 170Mpix/sec DSC throughput support
[why]
It was missing, although defined in DP spec

[how]
- Add handling of this value to DSC code
- Also remove unused file dsc_helpers.c

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:11 -05:00
Charlene Liu c703e753c8 drm/amd/display: add SW_USE_I2C_REG request.
[Description]
This is for DC_I2c arbitration use between HW use/SW use and DMCU use.

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:11 -05:00
Nikola Cornij b01473e919 drm/amd/display: Make sure line size is not zero in DCN2 line buffer size calculations
[why]
'Divide by zero' error happens when line size happens to be zero.

[how]
The code that makes sure line size minimum value can be 1 was already
present in DCN1 part of the driver, this is mearly a port to DCN2.

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:11 -05:00
Eryk Brol 7fad39ca4a drm/amd/display: Change DCN2 vupdate start programming
[Why]
In order to ensure that incoming flips are latched and
complete immediately, we need to program the vupdate
interrupt to come during the back porch of each frame.

[How]
Program the vupdate start_line to be in the back porch
like it's done for DCN1.

Signed-off-by: Eryk Brol <eryk.brol@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:11 -05:00
Yongqiang Sun 78b674573a drm/amd/display: Refactor program watermark.
Refactor programming watermark function:
Divided into urgent watermark, stutter watermark and pstate watermark.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:10 -05:00
Dmytro Laktyushkin be67de3561 drm/amd/display: fix dcn2 mpc split decision
The split condition is broken and will always activate
at the moment.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:10 -05:00
Charlene Liu 4850ce697f drm/amd/display: Add hubp_init entry to hubp vtable
Different HW will need to init HUBP differently. For now, add a vtable
entry, and hook a NO-OP for DCN1 and DCN2.

In addition, future HW will need to access the HUBPREQ_DEBUG and
CUR_TTU_CNTL0 register for hubp_init. Add that here.

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:10 -05:00
Ilya Bakoulin fbc9ca671f drm/amd/display: Fix ODM combine data format
[Why]
OPTC data format was left at its default value (444) when enabling
ODM combine. This caused issues with FPGA capture.

[How]
Write the OPTC_DATA_FORMAT field when enabling ODM combine.

Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:10 -05:00
Yongqiang Sun 2a874fa025 drm/amd/display: Remove duplicate define of TO_DCN20_HUBBUB
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:10 -05:00
Thomas Lim 78ad75f8d7 drm/amd/display: Add power down display on boot flag
[Why]
Due to the generic introduction of seamless boot, the display is no
longer blanked upon boot. However, this causes corruption on some
systems that does not lock the memory in the non-secure boot case,
resulting in brief corruption on boot due to garbage being written into
the frame buffer.

[How]
Add a flag, read during DC init, to determine whether display should be
blanked on boot. Default to true.

Signed-off-by: Thomas Lim <Thomas.Lim@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:10 -05:00
Nikola Cornij 9c0ab2dd07 drm/amd/display: Consider DSC target bpp precision when calculating DSC target bpp
[why]
DSC target bpp precision is a decoder DPCD and an AMD encoder capability.
It must be taken into account when calculating target bitrate.

[how]
Add a DC DSC function that does this calculation.

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:10 -05:00
Josip Pavic d7c29549e3 drm/amd/display: enable abm on dcn2
[Why]
ABM is currently not enabled on DCN2.

[How]
Update the register name list for DCN2 and un-comment the code that
creates the abm object.

Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:10 -05:00
Wenjing Liu c2209d1544 drm/amd/display: Implement DSC MST fair share algorithm
[why]
The current policy will always enable DSC to 12 bpp
regardless of if the current bandwidth is enough for MST displays.
This logic is not optimal because user will get lower quality output
if DSC compression is enabled.
This change to is to implement a DSC MST bandwidth fair share
algorithm so we will dynamically decide if DSC is needed and what
quality (target bpp) is needed to fairly destribute the MST bandwidth
in one MST topology. This will allow user to see the most optimal
image quality with the given bandwidth.

[how]
We will start with lowest bandwidth possible and run a
Max-Min fairness algorithm to fairly distribute the available
bandwidth. If there is still remaining bandwidth, we will try to fit
the timing without DSC compression.

Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:10 -05:00
Nikola Cornij c9ae6e1691 drm/amd/display: Acquire DSC HW resource only if required by stream
[why]
There are ASICs that have fewer DSC engines than pipes, which makes
DSC a resource that should be used only if required.

[how]
Acquire DSC HW resource if required by stream and release when not
required anymore.

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:10 -05:00
hersen wu 0d7bd17c6e drm/amd/display: Disable display writeback on Linux for NV10
[WHY] system crash when initialize dwb
current linux driver does not support dwb.
 disable this feature for now.

[HOW] set num_dwb = 0 to disable dwb for now

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:10 -05:00
hersen wu b37727fb14 drm/amd/display: Add vupdate interrupt sources to NV10
[WHY] linux upstream already has interrupt vupdate for freesync
in dcn10. dcn20 interrupt shares the same source code as dcn10.
but dcn20 interrupt translator does not add vupdate interrupt.
this cause index of vupdate aarray be negative which causes
crash.

[HOW] add vupdate into dc interrupt transltor

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:10 -05:00
Nikola Cornij c92b4c46c1 drm/amd/display: Mark DSC resource as unused after copying to the secondary ODM pipe
[why]
DSC resource has to be acquired before it can be used and simply copying
a reference to it is very likely to cause problems when accessing DSC.

[how]
Set DSC resource pointer to NULL to mark it as unused after primary pipe
resources were copied to the secondary ODM pipe.

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:10 -05:00
Tyler DiBattista 5940ff3941 drm/amd/display: Change Min fclk to 1.2Ghz
[Why]
Some nightly tests are failing since the new value for fclk is a
bit too low. Also, a new test for the maximum downscale case was
needed.

[How]
Updated the default value for fclk to be 1.2GHz.

Signed-off-by: Tyler DiBattista <tyler.dibattista@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:10 -05:00
Wenjing Liu 6c5be4ac63 drm/amd/display: add global master update lock for DCN2
[why]
when an update programming sequence requires both
front end and back end pipe to be updated synchronously,
a global update lock needs to be set to ensure that
we don't get a frame with only front end update but
not the back end update.

[how]
setup global lock parameters on enable_stream_timing.
enable global lock when pipe_control_lock_global is called.
disable global lock when pipe_control_lock is called.

Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:10 -05:00
Yongqiang Sun 64f223b0dd drm/amd/display: Remove REFCYC regs
[Why]
Some register fields are not needed.

[How]
remove them

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:10 -05:00
Joshua Aberback 42351c66ae drm/amd/display: Add profiling tools for bandwidth validation
[Why]
We used this change to investigate the performance of bandwidth validation,
it will be useful to have if we need to investigate further.

[How]
We use performance counter tick numbers to profile performance, they live
at dc->debug.bw_val_profile (set .enable in debugger to turn on measuring).

Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:10 -05:00
Joshua Aberback 254eb07cb0 drm/amd/display: Optimize bandwidth validation by adding early return
We can split validation into three parts: getting voltage level, getting
watermarks, and rq/dlg calculations. The voltage level is enough to answer
the question "do we support this state", and the rest of it is to determine
what hardware programming is needed to support the state. Most of the calls
to validate_bandwidth only care about the first part, so we added an early
return in that case

Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:09 -05:00
Leo Li 776c1f569f drm/amd/display: Properly guard display_mode_vba with DCN2
[Why]

display_mode_vba is for DCN2 and up. When building for upstream (DCN1
enabled only), there will be a build error, since display_mode_vba.c/h
is stripped out.

Note that building DCN1 only with internal dal-dev is still fine, since
display_mode_vba.h is not stripped out internally - only in upstream.
The make directives therefore stll work, and so will any #include's.

[How]

Since subsequent generations require DCN2 enabled anyways, guard the
makefile directive for display_mode_vba.o with DCN2. Guard any includes
with DCN2. In addition, guard the entire contents of display_mode_vba.h
with DCN2, to simulate the file being stripped out in upstream.

A forward declaration for 'struct display_mode_lib' also needs to be
added in display_mode_lib.h. Previously, display_mode_vba.h contained
the forward declaration, and display_mode_lib.h in turn included it.
This won't work if mode_vba.h is stripped out, requring mode_lib.h to do
so itself.

Signed-off-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:09 -05:00
Leo Li 10b3aa5eb1 drm/amd/display: Guard DML_FAIL_DSC_VALIDATION_FAILURE
[Why]
Usage of this enum is DSC-only.

[How]
Guard it with CONFIG_DRM_AMD_DC_DSC_SUPPORT.

Signed-off-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:09 -05:00
Vitaly Prosyak 83a76b5373 drm/amd/display: Add 3dlut control flags
[Why & How]
The follow up change
Improve some naming for fields and structs

Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Vitaly Prosyak <Vitaly.Prosyak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:09 -05:00
Charlene Liu ede37e4ce4 drm/amd/display: fix can not turn on two displays due to DSC_RESOURCE failed.
[Why]
Can not turn on two displays at the same time with the asic having only one DSC.
DC_DSC_RESOURCE allocation failed.

[Solution]
Only add_dsc if the timing is dsc capable based on diag_dc and num_dsc

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:09 -05:00
Ilya Bakoulin 8e27a2d4cd drm/amd/display: Fix DCFCLK and SOCCLK not set
[Why]
If voltage level > 0, DCFCLK and SOCCLK could be 0 during DML
calculations, which ended up causing an assert.

[How]
Initialize dcfclk_mhz and socclk_mhz values according to the
voltage level.

Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:09 -05:00
Yongqiang Sun 0213541d4b drm/amd/display: DCN2 reg refactors
Added some regs and exposed some functions for future use

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:09 -05:00
Vitaly Prosyak adb732d66c drm/amd/display: Add some tm3dlut flags
Move flags from color_gamma.h to mod_shared.h
and add more options and setting structures

Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Vitaly Prosyak <Vitaly.Prosyak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:09 -05:00
Nikola Cornij 23882a693f drm/amd/display: Make sure DSC slice height is divisible by 2 for 4:2:0 color format
[why] DSC spec requires this

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:09 -05:00
Nikola Cornij d438d11338 drm/amd/display: Use 1/8th DSC target bitrate precision for N4:2:2 and 4:2:0 formats
[why]
On at least some of the devices (e.g. Realtek scaler) we get a black screen if 1/16th
precision is used.

[how]
Work around it by reducing precision to 1/8th for N4:2:2 and 4:2:0 color formats. This
is a safe workaround and would have a very mild impact on the quality.
The issue is still to be root-caused and fixed correctly.

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:09 -05:00
Wenjing Liu db5378c1dc drm/amd/display: isolate global double buffer lock programming
[why]
Global optic double buffer lock is currently disabled due to
incorrect programming sequence that affects non global lock.

[how]
Isolate global lock programming sequence out of non global lock
programming sequence, so it can be enabled without affecting
non global lock.

Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:09 -05:00
Nikola Cornij 87029eb4fa drm/amd/display: Remove additional FEC link bandwidth reduction
[why]
This is now done in the original link bandwidth calculation and DSC
must not do this anymore.

[how]
Remove the line of code that should have been removed when transition
to correctly applying FEC overhead was made.

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:09 -05:00
Tony Cheng b7d39c5878 drm/amd/display: move dsc clock from plane_resource to stream_resource
code restructure.

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:09 -05:00
Dmytro Laktyushkin 0ff8dfe8f8 drm/amd/display: fix fpga fclk programming
We shouldnt need overhead on top of dppclk when setting fclk.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:09 -05:00
Wenjing Liu 96454cfb4f drm/amd/display: remove target_dpp hack for dsc
Remove dc_dsc hack for MST policy

Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:09 -05:00
Wenjing Liu 390fdfbd2d drm/amd/display: remove legacy DSC functions
[why]
Clean up some dsc legacy functions that are
no longer needed.

[how]
remove two dsc functions in dc_dsc, use dc_bandwidth_in_kbps_from_timing
instead of calc_required_bandwidth_for_timing.

Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:09 -05:00
Joshua Aberback 2e2e73fc63 drm/amd/display: Remove dependency on pipe->plane for immedaite flip status
[Why]
dcn20_apply_ctx_for_surface can be called with 0 planes, which means we
should blank the display. In this case when we get down to
dcn20_setup_gsl_group_as_lock, pipe_ctx->plane_state is NULL, but we don't
check for it. However, this function is only called by
dcn20_pipe_control_lock, and in that function we alraedy have a local for
the immediate flip status, which is what we care about in the plane state.

[How]
 - pass in immediate flip status as parameter

Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:09 -05:00
Dmytro Laktyushkin 0ba37b20ef drm/amd/display: fix dsc validation
Currently dsc is validated not taking the image width limitation into
mind.

This change addresses that, but due to previous design being limited
to non odm dsc validation additional sequence changes are made.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:08 -05:00
Aidan Wood 173932dec7 drm/amd/display: Properly set u clock
[Why]
u clk set request was being sent in units of mts, when it needed to be
in units of Mhz

[How]
add a division by 16 to convert from mts to Mhz

Signed-off-by: Aidan Wood <Aidan.Wood@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:08 -05:00
Aidan Wood c2ad17c3b2 drm/amd/display: Properly set DCF clock
[Why]
If num_states == 0 we did update_bound_box which doesn't updated any max
clocks if num_states == 0, therefore we need to do cap_soc_clocks
instead, also SMU cannot set DCF clock to a higher than or equal to freq
than SOC clock

[How]
Add a num_states != 0 check for update_bounding_box to be run, and after
we run get_maximum_sustainable_clocks we now check if the reported max
value of DCF is higher than SOC and if necessary set it to 1000
(becomes 1 after division by 1000) lower than SOC

Signed-off-by: Aidan Wood <Aidan.Wood@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:08 -05:00
Nikola Cornij c2bcd914a2 drm/amd/display: Calculate link bandwidth in a common function
[why]
Currently link bandwidth is calculated in various places using the same
multi-step formula. Doing this in one common place makes sure the same
formula will indeed be applied to all link bandwidth calculations.
It also makes it possible to apply link-setting-specific adjustments
that affect effective link bandwidth.

[how]
Replace all implementations of link bandwidth calculation with a call
to a function.

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:08 -05:00
Vitaly Prosyak c5d3a38b1a drm/amd/display: Add a flags union for 3dlut transformation matrix
[Why & How]
When TM is enabled with 3dlut, we apply conversion to
dcip3 in gamut remap matrix, if source area less than
dcip3. If it is bigger, we remap to bt2020. The added
flags will be used to facilitate this logic.

Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:08 -05:00
Dmytro Laktyushkin 00999d991f drm/amd/display: clean up validation failure log spam
Currently dcn2+ validation will unconditionally print a failure
reason before validation completes. This change categorizes the
failure reason as a warning log and only prints at the end of
validation resolving false positives.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:08 -05:00
Bob Yang 0cd3262566 drm/amd/display: fixed DCC corruption
[Description]
swath_bytes_horz_wc should be 256/64/64 for 2160p 32bpp surface

Signed-off-by: Bob Yang <Bob.Yang@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:08 -05:00
Leo Li 4e0cbbbfbc drm/amd/display: Clean up locking in dcn*_apply_ctx_for_surface()
[Why]

dcn*_disable_plane() doesn't unlock the pipe anymore, making the extra
lock unnecessary.

In addition - during full plane updates - all necessary pipes should be
locked/unlocked together when modifying hubp to avoid tearing in
pipesplit setups.

[How]

Remove redundant locks, and add function to lock all pipes. If an
interdependent pipe update is required, lock down all pipes. Otherwise,
lock only the top pipe for the updated pipe tree.

Signed-off-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:08 -05:00
Leo Li 1b394e92a1 drm/amd/display: Disconnect DCN2 mpcc when changing tg
A previous fix was done for DCN1 that needed to be ported to DCN2:
commit 60c677534e73 ("drm/amd/display: Disconnect mpcc when changing tg")

Signed-off-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:08 -05:00
Hawking Zhang 38354495d7 drm/amd/display: enable DSC support by default
Enable DSC (display stream compression) by default.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:08 -05:00
hersen wu ec8763486d drm/amd/display: navi10 bring up skip dsc encoder config
not needed for bring up.

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:08 -05:00
hersen wu 9e14d4f17e drm/amd/display: skip dsc config for navi10 bring up
[why] we meet a bug when program dsc register even dsc mode is not
enabled. disable dsc config for now. we will re-visit this issue.

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:08 -05:00
hersen wu 0fcf90d177 drm/amd/display: do not need otg lock if otg is not active
[todo] need find caller bug. tempooariy fix

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:08 -05:00
hersen wu 96cb7cf13d drm/amd/display: disable dcn20 abm feature for bring up
[WHY] dcn20 enable usb-c dp ALT mode in dmcu. There is bug
when enable abm feature which cause system crash. dal team
will debug this bug later.

[HOW] disable dcn abm feature for dcn20.

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:08 -05:00
Eric Bernstein bcba830ce7 drm/amd/display: Refactor DIO stream encoder
* Pull duplicate audio_clock_info struct to stream_encoder.h
* Generalize sec_gsp7* to sec_gsp_pps*
* Expose enc1 and enc2 stream encoder audio funcs

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:08 -05:00
Jun Lei 6ba117404e drm/amd/display: fix pstate allow handling in dcn2
[why]
pstate allow/block is not being handled properly on DCN2

[how]
DML needs to be updated to calculate pstate support at both min and max
mpc combine rather than just min
clock manager needs to update current to new pstate support before
sending to pplib/smu

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:08 -05:00
Ilya Bakoulin 5cb646d767 drm/amd/display: Add writeback_config to VBA vars
Adding writeback_config enum to vba_vars_st, replacing old flag.
Initialize to dm_normal.

Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:07 -05:00
Eric Yang c69dd2d06c drm/amd/display: Refactor clk_mgr functions
[Why]
Some HW specific implementations can be pulled out into clk_mgr.c.

[How]
- Pull get_active_display_cnt out to clk_mgr.
- Pull out shared logic in set_dispclk and set_dprefclk

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:07 -05:00
Charlene Liu 8712bda45c drm/amd/display: dcn2 dmcu wait_for_loop update with dispclk.
[Description]
DMUB is using DPREF CLK, but DMCU still use displayclk.
This is for updating DMCU wait_for_loop after display clock change.

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:07 -05:00
Anthony Koo 45021f8ea5 drm/amd/display: do not power on eDP power rail early
[Why]
Modern Standby may toggle display adapter state between D0
and D3 state unpredictably.
But events that cause transition to D0 are not always resulting
in a display light up scenario.

Modern eDP panels should be able to power on panel logic
quickly upon VDD going high. Based on spec, the T3 time
between VDD on and HPD high can be between 0 and 80 ms.

Doing any tricky sorts of optimization by powering on panel
VDD early during D0 transition on can negatively impact other
features due to unnecessary power drain and toggling when
final system state does not intend for the panel to be lit up.

We need OEMs to source higher end panels that have T3 time
close to 0 if they want quick S3/Modern Standby resume times.

[How]
Remove panel VDD power on in init_hw

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:07 -05:00
Chris Park bedbbe6af4 drm/amd/display: Move link functions from dc to dc_link
[Why]
link-specific functions should reside in dc_link.c

[How]
Move them there.

Signed-off-by: Chris Park <Chris.Park@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:07 -05:00
Jun Lei f18bc4e53a drm/amd/display: update calculated bounding box logic for NV
[why]
Current calculation of bounding box will cause DML to increase voltage
state due to DPP or DISPCLK, this is unnecessary since from DML perspective
we can max DPP/DISP can be supported at DPM0.  This is because
increasing voltage for DPP/DISP is done separately via actual minimum values
of DISP and DPP CLK

[how]
For each calculated state, DPP, DISP, PHY, and DSC clk should always be set to
maximum.  FCLK, SOCCLK, and DCFCLK should be based of UCLK.

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:07 -05:00
Paul Hsieh 98b5b65eb8 drm/amd/display: disable PSR/ABM before destroy DMCU struct
[Why]
1. DMCU is not running on some platform but driver still send ABM
   command. It may cause assert due to DMCU is not alive.
2. To make sure PSR disable when driver disable

[How]
1. Add dmcu_is_running in ABM struct, driver can check this flag to
   determine driver should send ABM command or not.
2. Send PSR disable command when destroy PSR

Signed-off-by: Paul Hsieh <paul.hsieh@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:07 -05:00
Eryk Brol ae8f425840 drm/amd/display: Ensure DRR triggers in BP
[Why]
In the previous implementation DRR event sometimes came
in during FP2 region which is a keep-out zone. This
would cause the frame not to latch until the next frame
which resulted in heavy flicker. To fix this we need
to make sure that it triggers in the BP.

[How]
1. Remove DRR programming during flip
2. Setup manual trigger for DRR event and trigger it
after surface programming is complete

Signed-off-by: Eryk Brol <eryk.brol@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:07 -05:00
hersen wu 284358f2ac drm/amd/display/dc: fix azalia workaround sw implementation bug
caller of pp_nv_set_pme_wa_enable pass incorrect pp_smu:
dc->res_pool->pp_smu. it should be dc->res_pool->pp_smu->nv_funcs.pp_smu.
with incorrect input, pp->dm = NULL. This causes system crash.

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:07 -05:00
Joshua Aberback 3972c35085 drm/amd/display: Program VTG params after programming Global Sync for DCN2
[Why]
VTG has a parameter FP2, which is defined as:
    if VSTARTUP is before VSYNC:
        FP2 = number of lines in between VSTARTUP and VSYNC
    else
        FP2 = 0
Currently, FP2 is only programmed during "program_timing". However, the
position of VSTARTUP is affected by the prefetching requirements on all pipes,
so the position might change when we do memory request control on another pipe, so we need
to make sure that FP2 stays up-to-date whenever we adjust VSTARTUP.

[How]
 - refactor VTG_CONTROL programming into a new function "set_vtg_params"
 - call it after calling "program_global_sync"
   - make sure it's called after because it relies on the cached dlg params

Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Jun Lei <Jun.Lei@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:07 -05:00
Harry Wentland 97bda0322b drm/amd/display: Add DSC support for Navi (v2)
Add support for DCN2 DSC (Display Stream Compression)

HW Blocks:

 +--------++------+       +----------+
 | HUBBUB || HUBP |  <--  | MMHUBBUB |
 +--------++------+       +----------+
        |                     ^
        v                     |
    +--------+            +--------+
    |  DPP   |            |  DWB   |
    +--------+            +--------+
        |
        v                      ^
    +--------+                 |
    |  MPC   |                 |
    +--------+                 |
        |                      |
        v                      |
    +-------+      +-------+   |
    |  OPP  | <--> |  DSC  |   |
    +-------+      +-------+   |
        |                      |
        v                      |
    +--------+                /
    |  OPTC  |  --------------
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

v2: rebase (Alex)

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:07 -05:00
Harry Wentland b4f199c7b0 drm/amdgpu: Enable DC support for Navi10
Enable the IP for navi10.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:07 -05:00
Harry Wentland 476e955dd6 drm/amd/display: Hook DCN2 into amdgpu_dm and expose as config (v2)
Enable DCN2 support in DM (Display Manager).

v2: fix spurious raven change (Alex)

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:07 -05:00
Alex Deucher 5b1b2f209f drm/amd/display: update dcn2 dc_plane_cap
To deal with rebasing the code.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:07 -05:00
Alex Deucher e249428256 drm/amd/display: updates for dcn20_update_bandwidth
Pass extra parameter to validate_bandwidth() callback.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:07 -05:00
Alex Deucher cb0b554abe drm/amd/display: add fast_validate parameter to dcn20_validate_bandwidth
To deal with changes from rebasing.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:07 -05:00
hersen wu 79a7b060d8 drm/amd/display: hook navi10 pplib functions
during bring up time, before window dc-ppplib interface
design, linux dc use raven dc-pplib interface.
now nvai10 dc-pplib-smu interface is changed and verified
under window, navi10 need its specific dc-pplib-smu
interface. todo: hook set_hard_min_uclk_by_freq,
get_maximum_sustainable_clocks

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:07 -05:00
hersen wu be9a7355e9 drm/amd/powerplay: add interface to get uclk dpm table
dc needs get uclk dpm table for bandwidth calculation

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:34:06 -05:00
hersen wu a18bf0ca41 drm/amd/powrplay: add interface for dc to get max clock values
dc (display component) needs maximum clock values of uclock,
socclk, dcefclk, to calculate display bandwidth.

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22 09:33:44 -05:00
Russell King d880fa6627 drm/armada: use mode_valid to validate the adjusted mode
Validate the adjusted mode in the CRTC mode_fixup() call to ensure that
any encoder or bridge doesn't supply us with a mode we can't support.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-06-22 11:58:20 +01:00
Russell King 1ba246f2fd drm/armada: improve Dove clock selection
Improve the Dove (Armada 510) LCD clock selection and divider
calculation, limiting to the valid divisor values, and reporting an
error if the clock is not achievable within the bounds of HDMI
clocking requirements.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-06-22 11:51:20 +01:00
Jason A. Donenfeld 9285ec4c8b timekeeping: Use proper clock specifier names in functions
This makes boot uniformly boottime and tai uniformly clocktai, to
address the remaining oversights.

Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lkml.kernel.org/r/20190621203249.3909-2-Jason@zx2c4.com
2019-06-22 12:11:27 +02:00
Harry Wentland 6fbefb84a9 drm/amd/display: Add DC core changes for DCN2
Core DC changes for DCN2.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:35 -05:00
Harry Wentland 7ed4e6352c drm/amd/display: Add DCN2 HW Sequencer and Resource
Add DCN2 resource definition and HW Sequencer changes.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:35 -05:00
Harry Wentland 18eaea4bf8 drm/amd/display: Add DCN2 VMID
Add support to program DCN2 VMID (Virtual Memory Support)

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:35 -05:00
Harry Wentland 83421f32b7 drm/amd/display: Add DCN2 IPP
Add support to program DCN2 cursor (IPP)

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:35 -05:00
Harry Wentland 345429a67c drm/amd/display: Add DCN2 DWB
Add support to program the DCN2 DWB (Display Writeback)

HW Blocks:

 +--------++------+       +----------+
 | HUBBUB || HUBP |  <--  | MMHUBBUB |
 +--------++------+       +----------+
        |                     ^
        v                     |
    +--------+            +--------+
    |  DPP   |            |  DWB   |
    +--------+            +--------+
        |
        v                      ^
    +--------+                 |
    |  MPC   |                 |
    +--------+                 |
        |                      |
        v                      |
    +-------+                  |
    |  OPP  |                  |
    +-------+                  |
        |                      |
        v                      |
    +--------+                /
    |  OPTC  |  --------------
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:35 -05:00
Harry Wentland fa0d2c989c drm/amd/display: Add DCN2 MMHUBBUB
Add support to program the DCN2 MMHUBBUB (Multimedia HUB interface)

HW Blocks:

 +--------++------+       +----------+
 | HUBBUB || HUBP |  <--  | MMHUBBUB |
 +--------++------+       +----------+
        |
        v
    +--------+
    |  DPP   |
    +--------+
        |
        v
    +--------+
    |  MPC   |
    +--------+
        |
        v
    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:34 -05:00
Harry Wentland bbeb64d0eb drm/amd/display: Add DCN2 HUBP and HUBBUB
Add support to program the DCN2 HUBP (Display to data fabric interface
pipe) and HUBBUB (DCN memory HUB interface)

HW Blocks:

 +--------++------+
 | HUBBUB || HUBP |
 +--------++------+
        |
        v
    +--------+
    |  DPP   |
    +--------+
        |
        v
    +--------+
    |  MPC   |
    +--------+
        |
        v
    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:34 -05:00
Harry Wentland f7de96ee8b drm/amd/display: Add DCN2 DPP
Add support to program the DCN2 DPP (Multiple pipe and plane combine)

HW Blocks:

    +--------+
    |  DPP   |
    +--------+
        |
        v
    +--------+
    |  MPC   |
    +--------+
        |
        v
    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:34 -05:00
Harry Wentland f789b0b82b drm/amd/display: Add DCN2 MPC
Add support to program the DCN2 MPC (Multiple pipe and plane combine)

HW Blocks:

    +--------+
    |  MPC   |
    +--------+
        |
        v
    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:34 -05:00
Harry Wentland eb7a74a36c drm/amd/display: Add DCN2 OPP
Add support to program the DCN2 OPP (Output Plane Processing)

HW Blocks:

    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:34 -05:00
Harry Wentland 2d78b3a177 drm/amd/display: Add DCN2 OPTC
Add support for programming the DCN2 OPTC (Output Timing Controller)

HW Blocks:

    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:34 -05:00
Harry Wentland fcee01b9f8 drm/amd/display: Add DCN2 clk mgr
Adds support for handling of clocking relevant to the DCN2 block,
including programming of the DCCG (Display Controller Clock Generator)
block:

HW Blocks:

    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:34 -05:00
Harry Wentland ca4d9b3a5a drm/amd/display: Add DCN2 DIO
Add support for the DIO (Display IO)  block of DCN2, which entails our
stream and link encoders.

HW Blocks:

    +--------+
    |  DIO   |
    +--------+

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:34 -05:00
Harry Wentland 728c06986a drm/amd/display: Add DCN2 changes to DML
Update DML (Display Mode Lib) to support DCN2

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:34 -05:00
Harry Wentland bff65b7781 drm/amd/display: Add DCN2 IRQ handling
Add support to program DCN2 IRQ handling

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:34 -05:00
Harry Wentland 9647509497 drm/amd/display: Add DCN2 BIOS parsing
Handle BIOS parsing for DCN2

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:34 -05:00
Harry Wentland 2e35facf82 drm/amd/display: Add GPIO support for DCN2
Adding support to program GPIO HW block of DCN2

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:34 -05:00
Harry Wentland 38e7128960 drm/amd/display: add AUX and I2C for DCN2
Adding support to program DCN2 AUX and I2C HW.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:34 -05:00
Harry Wentland 9793014570 drm/amd/display: Add DCN2 and NV ASIC ID
DCN2.0 (Display Core Next) is the display block in Navi10.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:34 -05:00
Xiaojie Yuan 76b743f45d drm/amd/display: use fixed-width data type for soc bounding box struct
since it's firmware.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:34 -05:00
Leo Li 57b3ec35d5 drm/amdgpu: Split gpu_info_soc_bounding_box out from amdgpu_ucode.h
DC needs to include the soc bounding box when initializing HW resources.

Including amdgpu_ucode.h directly will cause warnings, since amdgpu.h is
required to define amdgpu_device. The solution here is to split the
bounding box structs into a different header, then include it in both
amdgpu_ucode.h, and relevant DC HW resource files.

Signed-off-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:34 -05:00
Harry Wentland 48321c3dde drm/amd/display: Read soc_bounding_box from gpu_info (v2)
[WHY]
We don't want to expose sensitive ASIC information before ASIC release.

[HOW]
Encode the soc_bounding_box in the gpu_info FW (for Linux) and read it
at driver load.

v2: fix warning when CONFIG_DRM_AMD_DC_DCN2_0 is not set (Alex)

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:34 -05:00
hersen wu edee92c379 drm/amd/powerplay: notify smu with active display count
when dc update clocks via smu, smu needs to know how many
displays active. this interface is for dc notify number
of active displays to smu.

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:33 -05:00
hersen wu 5c170a59e7 drm/amd/powerplay: allow dc request uclk change
when dc set mode or color format in frame buffer
change, it may request clock changes, like dispclk,
dcfclk, uclk. after smu get clock requests, smu
will make decision.

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:33 -05:00
Hawking Zhang ccbf007b47 drm/amdgpu: initialize THM & CLK IP registers base address
was missed before.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:33 -05:00
Marek Olšák 61af800fe7 drm/amdgpu: fix PA_SC_FIFO_SIZE for Navi10 (v2)
Proper size is 0.

v2: squash in whitespace fixes (Ernst Sjöstrand)

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:33 -05:00
Kevin Wang 93dfbcefb3 drm/amd/powerplay: remove unsupport function set_thermal_fan_table for navi10
the PPSMC_MSG_SetFanTemperatureTarget is not support on navi10

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:33 -05:00
Jack Xiao 7c6fe84cf5 drm/amd/powerplay: enable BACO feature as WAR
It would hit SMU fw bug without BACO enablement when audio
driver put audio device to D3 state. Before the bug in SMU fw
get fixed, enable BACO feature as WAR.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:33 -05:00
Kevin Wang a39bf39816 drm/amd/powerplay: use pp_feature_mask to control uclk(mclk) dpm enabled
the uclk dpm feature is not work well on all navi10 asic,
use pp feature mask module parameter to control it.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:33 -05:00
tiancyin 4f56d9d412 drm/amdgpu: add new navi10 DIDs
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: tiancyin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:33 -05:00
tiancyin 408e27cbba drm/amd/powerplay: add ppt interface version log
Include the interface version as well.

Signed-off-by: tiancyin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:33 -05:00
Alex Deucher 6ad68a7e1f drm/amdgpu/gfx10: update to latest golden setting
Fix UTCL1_CGTT_CLK_CTRL

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:33 -05:00
Alex Deucher 5917458548 drm/amdgpu/powerplay/vega20: use correct table index
Use the SMU_* variant so we look up the correct index.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:33 -05:00
Leo Liu 450af30ce2 drm/amdgpu/VCN: enable indirect DPG SRAM mode
This is default mode for VCN2.x now

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:33 -05:00
Leo Liu dc8ae677c2 drm/amdgpu/VCN: implement indirect DPG SRAM mode
SRAM will be programmed by PSP

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:33 -05:00
Leo Liu a77b9fdf9a drm/amdgpu/VCN: add buffer for indirect SRAM usage
This will be used later for indirect SRAM mode

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:33 -05:00
Jack Xiao 1768908ec5 drm/amd/powerplay: disable fw dstate when gfxoff is enabled
SMU FW has bug that it would cause hung when both fw dstate and
gfxoff are enabled at the same time.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:33 -05:00
Jack Xiao 4bc920a680 drm/amd/powerplay: update smu11_driver_if_navi10.h
update the smu11_driver_if_navi10.h since navi10 smu fw
update to 42.23

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:33 -05:00
Jack Xiao 86ddf3529e drm/amdgpu/psp: add new psp interface for vcn updating sram
PSP leverages the existing fw loading function for vcn updating sram.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:33 -05:00
Jack Xiao c76ff09bef drm/amdgpu/psp: convert ucode id to psp ucode id
Convert ucode id to the corresponding psp ucode id.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:32 -05:00
Jack Xiao 6e72d8e9fb drm/amdgpu: add corresponding vcn ram ucode id
Add VCN RAM ucode id in corresponding to psp ucode id.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:32 -05:00
Jack Xiao 68c0798cd9 drm/amdgpu/psp: add new VCN RAM ucode id to psp
PSP supports to program vcn sram by ucode loading interface.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:32 -05:00
Leo Liu 157710ea4d drm/amdgpu: enable VCN2.0 DPG mode
It will be the default for VCN2.x family

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:32 -05:00
Leo Liu 7282da0b3a drm/amdgpu/VCN2.0: add DPG pause mode
Pause the DPG when not doing decode

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:32 -05:00
Leo Liu bf4865b587 drm/amdgpu/VCN2.0: add DPG mode start and stop (v2)
This is for using SRAM directly

v2: rebase (Alex)

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:32 -05:00
Leo Liu 19c663fc77 drm/amdgpu/VCN2.0: add direct SRAM read and write
This will be the basic and used for DPG mode

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:32 -05:00
Leo Liu b3ef5ce037 drm/amdgpu/VCN2.0 remove unused Macro and declaration
Just for cleanup

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:32 -05:00
Kevin Wang 0c83d32c56 drm/amd/powerplay: simplified od_settings for each asic
the od_settings is asic related data, so move it to asic file.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:32 -05:00
Kevin Wang 8f30a16d3a drm/amd/powerplay: move od_default_setting callback to asic file
the set default od_setting is asic related function,
so move thic code to vega20_ppt file.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:32 -05:00
Kevin Wang a259714bb2 drm/amd/powerplay: move od8_setting helper function to vega20_ppt
these callback functions is only used for vega20 asic, to be compatible
other asics,need to move this code to vega20_ppt file

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:32 -05:00
Kevin Wang c7a063a2f2 drm/amd/powerplay: fix clk type name error OD_SCLK OD_MCLK
use sw-smu clk type name to replace legacy clk type name

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:32 -05:00
Kevin Wang 6f6a7bba69 drm/amd/powerplay: fix deadlock issue for smu_force_performance_level
the smu->mutex is internal lock resource in sw-smu, some functions will use
it at the same time, so it maybe will cause deadlock issue.
this patch fix this issue in smu_force_performance_level function.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:32 -05:00
Jack Xiao 3ebab625e6 drm/amd: the data retured from PRT is expected to be 0
The dummy page for returning from PRT resides inside system memory,
need set system flag bit in VM_L2_CNTL.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:32 -05:00
tiancyin b1fa87a48e drm/amdgpu/gfx10: update gfx golden settings
add new registers: mmPA_SC_ENHANCE_1, mmTCP_CNTL,
update registers: mmDB_DEBUG4, mmUTCL1_CTRL

Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: tiancyin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:32 -05:00
Alex Deucher f5c1b7afff drm/amdgpu/powerplay: add license to smu11 header
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:32 -05:00
hersen wu f4b3295fa2 drm/amd/powerplay: add interface to get uclk dpm table
dc needs get uclk dpm table for bandwidth calculation

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:32 -05:00
hersen wu 26e2b58148 drm/amd/powerplay: wake up azalia from d3 by sending smu message
this is hw workaround to wake up azalia from d3. display asic
and azalia are two different pci devices. while display asic
wake from d3, current hw does not send signal to azalia.
workaround: display driver ask smu send message to azalia device
to let azalia wake up.

Defintion of SMU message, like PPSMC_MSG_BacroAudioD3PME, is per
asic. It is shared by different OS.

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:32 -05:00
hersen wu 2e13c7551c drm/amd/powerplay: notify smu with active display count
when dc update clocks via smu, smu needs to know how many
displays active. this interface is for dc notify number
of active displays to smu.

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:31 -05:00
hersen wu 382fb77891 drm/amd/powerplay: allow dc request uclk change
when dc set mode or color format in frame buffer
change, it may request clock changes, like dispclk,
dcfclk, uclk. after smu get clock requests, smu
will make decision.

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:31 -05:00
Kevin Wang 576851345b drm/amd/powerplay: remove smu callback funciton get_mclk(get_sclk)
remove smu callback: get_mclk, get_sclk.
because the function smu_get_dpm_freq_range has the same function.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:31 -05:00
Kevin Wang e9c12a8e27 drm/amd/powerplay: remove smu mutex lock in smu_hw_init
the smu mutex lock is unnecessary in smu hw init.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:31 -05:00
Kevin Wang 5e6d266573 drm/amd/powerplay: add thermal ctf support for navi10
add sw-CTF support for navi10

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:31 -05:00
Hawking Zhang 9634de271a drm/amd/powerplay: fix no statements in function returning non-void
Add missing return (rebase fix).

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:31 -05:00
Hawking Zhang e211580da9 drm/amd/powerplay: move get_thermal_temperature_range to ppt funcs
The thermal policy could be ASIC specific ones and depends on structures
in pptable. As a result, get_thermal_temperature_range should be implemented
as ppt funcs instead of smu funcs

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:31 -05:00
Kevin Wang 4dc9c8bf34 drm/amd/powerplay: move function thermal_get_temperature to veag20_ppt
the fcuntion thermal_get_temperature will be access SmuMetrics_t data,
the data structure is asic related, so move vega20_ppt to implement.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:31 -05:00
Kevin Wang 62b9a88c0e drm/amd/powerplay: move function get_metrics_table to vega20_ppt
the SmuMetrics_t table is asic related data structure.
so move vega20_ppt file to implement.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:31 -05:00
Kevin Wang a38470f0f8 drm/amd/powerplay: move power_dpm_force_performance_level to amdgpu_smu file
because this callback is not asic related function, so move it to top
code level to support more asic (eg: navi10)

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:31 -05:00
Kevin Wang eefa5e2b30 drm/amd/powerplay: enable uclk dpm default on navi10
enable uclk (mclk) dpm by default on navi10

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:31 -05:00
Kenneth Feng d8ceb192cb drm/amd/powerplay: enable ac/dc feature on navi10
enable ac/dc feature on navi10. currently we don't have
the case to verify it.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:31 -05:00
Kenneth Feng 3a3c51dd90 drm/amd/powerplay: enable gfxclk ds,dcefclk ds and fw dstate on navi10
on navi10, by default the below four features are enabled.
gfxclk deep sleep: enabled and verified
fw dstate: enabled and then soc ulv is verified
dcefclk deep sleep: enabled and verified. notice that on different boards,
due to the minimum dcefclk deep sleep setting in VBIOS, we may not see dcefclk
deep sleep kicking in.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:31 -05:00
Kevin Wang c0b9d6d2f1 drm/amd/powerplay: add sclk sysfs interface support for navi10
miss sclk support in force_clk_levels function

Signed-off-by: Kevin Wang <kevin1.Wang@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:31 -05:00
Tao Zhou 462a70d87e drm/amdgpu: correct reference clock value on navi10
remove the divisor 4

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Acked-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:31 -05:00
Tao Zhou c877dff7d9 drm/amd/powerplay/smu11: disable some pp features on navi10 A0 secure board
disable DPM UCLK and SOC DS on A0 secure board

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:31 -05:00
Tao Zhou fc41915810 drm/amd/powerplay/smu11: add secure board check function (v2)
To determine whether the board is secure or not.

v2: rebase (Alex)

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:31 -05:00
Tao Zhou d7a8efa59b drm/amd/powerplay/smu11: enable ds socclk by default
Enable soc clk deep sleep.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:30 -05:00
Kevin Wang d5c316930f drm/amd/powerplay: fix amdgpu_pm_info show gpu load error
due to the smu dma/RTOS restriction, the interval of catching smu
metric table should be more than 1ms. otherwise it will cause the gpu
activity data corruption.

Signed-off-by:Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:30 -05:00
Kevin Wang 564c4c7f00 drm/amd/powerplay: simplify the interface of get_gpu_power
this callback function is only call in read_sensor in smu_v11_0.c,
so move this code to {asic}_ppt.c to implement as asic related function.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:30 -05:00
Kevin Wang d573bb214d drm/amd/powerplay: simplify the interface of get_current_activity_percent
this callback function is only call in read_sensor in smu_v11_0.c,
so move this code to {asic}_ppt.c to implement as asic related function.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:30 -05:00
Kevin Wang e36182490d drm/amd/powerplay: fix dpm freq unit error (10KHz -> Mhz)
the interface smu_v11_0_get_current_clk_freq should be return 10Khz not
Mhz unit to adapt vega20 and navi10 asic at the same time.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:30 -05:00
Kenneth Feng 162aa5c31a amd/powerplay: update the vcn pg
update the vcn pg function in navi10.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:30 -05:00
Kevin Wang 9c62f993ee drm/amd/powerplay: add function read_sensor for navi10
add callback function read_sensor for navi10 asic

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:30 -05:00
Kevin Wang 5bbb09943e drm/amd/powerplay: add function set_watermarks_table function for navi10
add callback function set_watermarks_table for navi10 asic

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:30 -05:00
Kevin Wang 4f963b01f6 drm/amd/powerplay: add function notify_smc_display_config_change for navi10
add callback function notify_smc_display_config_change for navi10 asic

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:30 -05:00
Kevin Wang 2d9fb9b066 drm/amd/powerplay: add function get_profiling_clk_mask for navi10
add callback function get_profiling_clk_mask for navi10 asic

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:30 -05:00
Kevin Wang b45dc20b08 drm/amd/powerplay: add funciton get[set]_power_profile_mode for navi10 (v2)
add callback function get[set]_power_profile_mode for navi10 asic

v2: fix smu_update_table for rebase (Alex)

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:30 -05:00
Kevin Wang 6c6187ece0 drm/amd/powerplay: add function get_workload_type_map for swsmu
1.add new callback function get_workload_byte for smu
2.remove old workload map function

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:30 -05:00
Kevin Wang 1316b71361 drm/amd/powerplay: remove upload_dpm_level function for vega20
the function upload_dpm_level is an internal function,
so remove public interface.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:30 -05:00
Kevin Wang 2d589a5bfb drm/amd/powerplay: add function get_fan_speed_percent for navi10
add callback function get_fan_speed_percent for navi10 asic

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:30 -05:00
Kevin Wang da85f08123 drm/amd/powerplay: add function set_thermal_fan_table for navi10
add callback function set_thermal_fan_table for navi10 asic

Signed-off-by:Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:30 -05:00
Kevin Wang 4228b6015d drm/amd/powerplay: add function is_dpm_running for navi10
add callback function is_dpm_running for navi10 asic

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:30 -05:00
Kevin Wang 6b1b7b5bf0 drm/amd/powerplay: move read sensor of UVD[VCE]_POWER to amdgpu_smu file
This part of code is asic unrelated and moves to top code level.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:30 -05:00
Kevin Wang 7447a23b08 drm/amd/powerplay: add function get_current_activity_percent for navi10
add callback function get_current_activity_percent for navi10 asic

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:30 -05:00
Kevin Wang 077ca74e3c drm/amd/powerplay: add function get_gpu_power for navi10
add callback function get_gpu_power for navi10 asic

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:29 -05:00
Kevin Wang 2f72726b2a drm/amd/powerplay: add function unforce_dpm_levels for navi10
add callback function unforce_dpm_levels for navi10 asic

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:29 -05:00
Kevin Wang 50add63bbf drm/amd/powerplay: add funciton force_dpm_limit for navi10
add callback function force_dpm_limit for navi10 asic

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:29 -05:00
Kevin Wang 0a6430da0c drm/amd/powerplay: add function display_configuration_changed for navi10
1.add callback function to support navi10 asic.
2.Remove unnecessary logical code.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:29 -05:00
Kevin Wang 284305445f drm/amd/powerplay: add function pre_display_config_changed for navi10
add callback function pre_display_config_changed for navi10 asic

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:29 -05:00
Kevin Wang a43913ea50 drm/amd/powerplay: add function get_clock_by_type_with_latency for navi10
add callback function get_clock_by_type_with_latency for navi10 asic

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:29 -05:00
Kevin Wang fa51bfc279 drm/amd/powerplay: add function populate_umd_state_clk for navi10
add callback function populate_umd_state_clk for navi10 asic

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:29 -05:00
Kevin Wang db439ca21b drm/amd/powerplay: add function force_clk_levels for navi10
add sysfs interface of force_clk_levels sysfs for navi10.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:29 -05:00
Kevin Wang 3366561767 drm/amd/powerplay: add helper function of smu_set_hard_freq_range
add this function to get dpm clock information.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:29 -05:00
Kevin Wang 0d7cbd2807 drm/amd/powerplay: add helper function of smu_set_soft_freq_range
add this helper function to get dpm clk information.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:29 -05:00
Kevin Wang 8b3d243e47 drm/amd/powerplay: add helper function of smu_get_dpm_freq_range
add this helper function to get dpm clk information (min, max);

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:29 -05:00
Kevin Wang b1e7e22419 drm/amd/powerplay: add function print_clk_levels for navi10
add sysfs interface of print_clk_levels sysfs for navi10.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:29 -05:00
Kevin Wang 3ac54a5043 drm/amd/powerplay: add helper function to get dpm freq informations
this function can help driver to get ppclk informations

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:29 -05:00
Kevin Wang 98e1a543c7 drm/amd/powerplay: add function get current clock freq interface for navi10
add function of get_current_clk_freq_by_table for navi10.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:29 -05:00
Jack Xiao bbd7a65350 drm/amdgpu/gfx10: require to pin/unpin CSIB BO when suspend/resume
CSIB BO is required to be pinned down to guarantee
bo is always valid when resume, and to be unpinned it
so that its content can be saved during suspend.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:29 -05:00
Jack Xiao 2c195b6cac drm/amdgpu/gfx10: remove unnecessary waiting on gfx inactive
The following KIQ ring test could guarantee the previous unmap
has been done.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21 18:59:29 -05:00