Граф коммитов

479 Коммитов

Автор SHA1 Сообщение Дата
Miquel Raynal 8389a7b909 SPI NOR core changes:
- introduce 'struct spi_nor_controller_ops',
 - clean the Register Operations methods,
 - use dev_dbg insted of dev_err for low level info,
 - fix retlen handling in sst_write(),
 - fix silent truncations in spi_nor_read and spi_nor_read_raw(),
 - fix the clearing of QE bit on lock()/unlock(),
 - rework the disabling of the block write protection,
 - rework the Quad Enable methods,
 - make sure nor->spimem and nor->controller_ops are mutually exclusive,
 - set default Quad Enable method for ISSI flashes,
 - add support for few flashes.
 
 SPI NOR controller drivers changes:
 - intel-spi:
 	- support chips without software sequencer,
 	- add support for Intel Cannon Lake and Intel Comet Lake-H flashes.
 -----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCAAdFiEEHUIqys8OyG1eHf7fS1VPR6WNFOkFAl3Kep8ACgkQS1VPR6WN
 FOn9kgf/aKPgU6LR84YpwUKRZ4S+6K1H8SdDUt8v0FYSQ6oaTjF13fApg43WDja5
 Zk0l5tlX7WIvlcRC6XKPhryZTXOKWojW1X8sguPYIZGzo7q82Eyda23jkw1QptWr
 VO9L/tdK4yVUbdtp6VS/FUF31PC0DtDoCzsfBSUgrZP2srFF1BtOJNUgyuDceoxo
 y3hEmINDnkaOvDDl/kbJjdEHG4PV8Vi4k0KE8deLpqlp8GDG1nkTeA1Sim7WjBPA
 ZZOdg9fmGI8H8+umQEnn06H4O95T2+fX+kDMCYo4RbgWyWlGv5TidgRREmC/cSbl
 YEPu6LCQoUZPVEvgolr/8Akf968ZiQ==
 =i15M
 -----END PGP SIGNATURE-----

Merge tag 'spi-nor/for-5.5' into mtd/next

SPI NOR core changes:
- introduce 'struct spi_nor_controller_ops',
- clean the Register Operations methods,
- use dev_dbg insted of dev_err for low level info,
- fix retlen handling in sst_write(),
- fix silent truncations in spi_nor_read and spi_nor_read_raw(),
- fix the clearing of QE bit on lock()/unlock(),
- rework the disabling of the block write protection,
- rework the Quad Enable methods,
- make sure nor->spimem and nor->controller_ops are mutually exclusive,
- set default Quad Enable method for ISSI flashes,
- add support for few flashes.

SPI NOR controller drivers changes:
- intel-spi:
	- support chips without software sequencer,
	- add support for Intel Cannon Lake and Intel Comet Lake-H flashes.
2019-11-17 18:34:01 +01:00
Sagar Shrikant Kadam 83cba933a6
mtd: spi-nor: Set default Quad Enable method for ISSI flashes
Set the default Quad Enable method for ISSI flashes. Used for
ISSI flashes (IS25WP256D-JMLE) that do not support SFDP tables
and can not determine the Quad Enable method by parsing BFPT.

Based on code originally written by Wesley Terpstra <wesley@sifive.com>
and/or Palmer Dabbelt <palmer@sifive.com>
c94e267766

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
[tudor.ambarus@microchip.com:
- rebase, split and adapt for latest spi-nor/next,
- use PMC CFI ID for ISSI. According to JEP106BA, "Programmable Micro Corp"
  changed its name to Integrated Silicon Solution (ISSI)]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-11 20:42:55 +02:00
Sagar Shrikant Kadam d6ee516372
mtd: spi-nor: Add support for is25wp256
Update the spi_nor_id table for is25wp256 (32MB) device from ISSI,
present on HiFive Unleashed dev board (Rev: A00).

Use the post bfpt fixup hook for the is25wp256 device, as done for
the is25lp256 device to overwrite the wrong address width advertised
by BFPT.

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
[tudor.ambarus@microchip.com: rebase, split and adapt for latest spi-nor/next]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-11 20:42:54 +02:00
Manivannan Sadhasivam 4c42f63553
mtd: spi-nor: Add support for w25q256jw
Add MTD support for w25q256jw SPI NOR chip from Winbond. This chip
supports dual/quad I/O mode with 512 blocks of memory organized in
64KB sectors. In addition to this, there is also small 4KB sectors
available for flexibility. The device has been validated using Thor96
board.

Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tudor Ambarus <tudor.ambarus@microchip.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Richard Weinberger <richard@nod.at>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Cc: linux-mtd@lists.infradead.org
Signed-off-by: Darshak Patel <darshak.patel@einfochips.com>
[Mani: cleaned up for upstream]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-11-11 20:42:53 +02:00
Tudor Ambarus 9326b4e078
mtd: spi-nor: Move condition to avoid a NULL check
When the controller is not under the SPI-MEM interface it may implement
the optional controller_ops->erase() method.

nor->spimem and nor->controller_ops are mutually exclusive. Move the
nor->controller_ops->erase != NULL check as an 'else if' case to
nor->spimem, in order to avoid the nor->controller_ops != NULL
check.

Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-11 20:42:52 +02:00
Tudor Ambarus ac82229d4e
mtd: spi-nor: Make sure nor->spimem and nor->controller_ops are mutually exclusive
Expand the spi_nor_check() to make sure that nor->spimem and
nor->controller_ops are mutually exclusive.

Fixes: b35b9a1036 ("mtd: spi-nor: Move m25p80 code in spi-nor.c")
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-11 20:42:13 +02:00
Tudor Ambarus 658488ed21
mtd: spi-nor: Rename Quad Enable methods
Rename macronix_quad_enable() to a generic name:
spi_nor_sr1_bit6_quad_enable().

Prepend "spi_nor_" to "sr2_bit7_quad_enable". All SPI NOR generic
methods should be prepended by "spi_nor_".

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-11 08:56:40 +02:00
Tudor Ambarus 7b678c69c0
mtd: spi-nor: Merge spansion Quad Enable methods
Merge
    spansion_no_read_cr_quad_enable()
    spansion_read_cr_quad_enable()
into
    spi_nor_sr2_bit1_quad_enable().

Reduce code duplication by introducing spi_nor_write_16bit_cr_and_check().
The Configuration Register contains bits that can be updated in future:
FREEZE, CMP. Provide a generic method that allows updating all bits
of the Configuration Register.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-11 08:56:39 +02:00
Tudor Ambarus bb2dc7f46a
mtd: spi-nor: Rename CR_QUAD_EN_SPAN to SR2_QUAD_EN_BIT1
JEDEC Basic Flash Parameter Table, 15th DWORD, bits 22:20,
refers to this bit as "bit 1 of the status register 2".
Rename the macro accordingly.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-11 08:56:37 +02:00
Tudor Ambarus 4da11da15a
mtd: spi-nor: Extend the SR Read Back test
Test that all the bits from Status Register 1 and Status Register 2
were written correctly.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-11 08:56:36 +02:00
Tudor Ambarus 3e0930f109
mtd: spi-nor: Rework the disabling of block write protection
spi_nor_unlock() unlocks blocks of memory or the entire flash memory
array, if requested. clear_sr_bp() unlocks the entire flash memory
array at boot time. This calls for some unification, clear_sr_bp() is
just an optimization for the case when the unlock request covers the
entire flash size.

Get rid of clear_sr_bp() and introduce spi_nor_unlock_all(), which is
just a call to spi_nor_unlock() for the entire flash memory array.
This fixes a bug that was present in spi_nor_spansion_clear_sr_bp().
When the QE bit was zero, we used the Write Status (01h) command with
one data byte, which might cleared the Status Register 2. We now always
use the Write Status (01h) command with two data bytes when
SNOR_F_HAS_16BIT_SR is set, to avoid clearing the Status Register 2.

The SNOR_F_NO_READ_CR case is treated as well. When the flash doesn't
support the CR Read command, we make an assumption about the value of
the QE bit. In spi_nor_init(), call spi_nor_quad_enable() first, then
spi_nor_unlock_all(), so that at the spi_nor_unlock_all() time we can
be sure the QE bit has value one, because of the previous call to
spi_nor_quad_enable().

Get rid of the MFR handling and implement specific manufacturer
default_init() fixup hooks.

Note that this changes a bit the logic for the SNOR_MFR_ATMEL,
SNOR_MFR_INTEL and SNOR_MFR_SST cases. Before this patch, the Atmel,
Intel and SST chips did not set the locking ops, but unlocked the entire
flash at boot time, while now they are setting the locking ops to
stm_locking_ops. This should work, since the disable of the block
protection at the boot time used the same Status Register bits to unlock
the flash, as in the stm_locking_ops case.

Suggested-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-11 08:56:19 +02:00
Tudor Ambarus 39d1e3340c
mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()
Make sure that when doing a lock() or an unlock() operation we don't clear
the QE bit from Status Register 2.

JESD216 revB or later offers information about the *default* Status
Register commands to use (see BFPT DWORDS[15], bits 22:20). In this
standard, Status Register 1 refers to the first data byte transferred on a
Read Status (05h) or Write Status (01h) command. Status register 2 refers
to the byte read using instruction 35h. Status register 2 is the second
byte transferred in a Write Status (01h) command.

Industry naming and definitions of these Status Registers may differ.
The definitions are described in JESD216B, BFPT DWORDS[15], bits 22:20.
There are cases in which writing only one byte to the Status Register 1
has the side-effect of clearing Status Register 2 and implicitly the Quad
Enable bit. This side-effect is hit just by the
BFPT_DWORD15_QER_SR2_BIT1_BUGGY and BFPT_DWORD15_QER_SR2_BIT1 cases.

Suggested-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-11 08:55:25 +02:00
Tudor Ambarus b24eaf5f23
mtd: spi-nor: Print debug message when the read back test fails
Demystify where the EIO error occurs.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07 08:18:28 +02:00
Tudor Ambarus 40b7d5cccc
mtd: spi-nor: Check all the bits written, not just the BP ones
Check that all the bits written in the write_sr_and_check() method
match the status_new received value. Failing to write the other bits
is dangerous too, extend the check.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07 08:18:28 +02:00
Tudor Ambarus b0db77f5aa
mtd: spi-nor: Fix errno on Quad Enable methods
When the Read-Modify-Write-Read-Back Quad Enable methods failed on
the Read-Back, they returned -EINVAL. Since this is an I/O error,
return -EIO.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07 08:18:27 +02:00
Tudor Ambarus 6011b484f1
mtd: spi-nor: Drop spansion_quad_enable()
Drop the default spansion_quad_enable() method and replace it with
spansion_read_cr_quad_enable().

The function was buggy, it didn't care about the previous values
of the Status and Configuration Registers. spansion_read_cr_quad_enable()
is a Read-Modify-Write-Check function that keeps track of what were
the previous values of the Status and Configuration Registers.

In terms of instruction types sent to the flash, the only difference
between the spansion_quad_enable() and spansion_read_cr_quad_enable()
is that the later calls spi_nor_read_sr(). We can safely assume that all
flashes support spi_nor_read_sr(), because all flashes call it in
spi_nor_sr_ready(). The transition from spansion_quad_enable() to
spansion_read_cr_quad_enable() will not affect anybody, drop the buggy
code.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07 08:18:26 +02:00
Tudor Ambarus 78f1ddf7bb
mtd: spi-nor: Describe all the Reg Ops
Document all the Register Operations.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07 08:18:25 +02:00
Tudor Ambarus 6e3087a863
mtd: spi-nor: Merge spi_nor_write_sr() and spi_nor_write_sr_cr()
Merge
static int spi_nor_write_sr(struct spi_nor *nor, u8 val)
static int spi_nor_write_sr_cr(struct spi_nor *nor, const u8 *sr_cr)
into
static int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len)

The Status Register can be written with one or two bytes. Merge
the two functions to avoid code duplication.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-07 08:18:25 +02:00
Tudor Ambarus 718dd9e69f
mtd: spi-nor: Move the WE and wait calls inside Write SR methods
Avoid duplicating code by moving the calls to spi_nor_write_enable() and
spi_nor_wait_till_ready() inside the Write Status Register methods.

Move spi_nor_write_sr() to avoid forward declaration of
spi_nor_wait_till_ready().

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-07 08:18:24 +02:00
Tudor Ambarus abd494bb07
mtd: spi-nor: Void return type for spi_nor_clear_sr/fsr()
spi_nor_clear_sr() and spi_nor_clear_fsr() are called just in case
of errors. The callers didn't check their return value, make them
of type void.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-07 08:18:23 +02:00
Tudor Ambarus cd1ebe1ca0
mtd: spi-nor: Rename label as it is no longer generic
Rename 'sst_write_err' label to 'out' as it is no longer generic for
all the errors in the sst_write() method, and may introduce confusion.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-07 08:18:22 +02:00
Tudor Ambarus bce679e5ae
mtd: spi-nor: Check for errors after each Register Operation
Check for the return vales of each Register Operation.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07 08:18:21 +02:00
Tudor Ambarus d1ed88eae3
mtd: spi-nor: Print debug info inside Reg Ops methods
Spare the callers of printing debug messages by themselves.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07 08:18:21 +02:00
Tudor Ambarus f633ebe487
mtd: spi-nor: Use dev_dbg insted of dev_err for low level info
What most users care about is "my dev is not working properly".
All low level information should be discovered when activating
the debug traces.

Keep error messages just for the following cases:
- when the SR/FSR report program or erase fails, or attempts of
  modifying a protected sector,
- when the JEDEC ID is not recognized,
- when the resume() call fails,
- when the spi_nor_check() fails.

Suggested-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07 08:16:07 +02:00
Sergei Shtylyov 3d63ee5deb
mtd: spi-nor: fix silent truncation in spi_nor_read_raw()
spi_nor_read_raw() assigns the result of 'ssize_t spi_nor_read_data()'
to the 'int ret' variable, while 'ssize_t' is a 64-bit type and *int*
is a 32-bit type on the 64-bit machines. This silent truncation isn't
really valid, so fix up the variable's type.

Fixes: f384b352cb ("mtd: spi-nor: parse Serial Flash Discoverable Parameters (SFDP) tables")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-11-02 12:16:38 +02:00
Sergei Shtylyov a719a75a77
mtd: spi-nor: fix silent truncation in spi_nor_read()
spi_nor_read() assigns the result of 'ssize_t spi_nor_read_data()'
to the 'int ret' variable, while 'ssize_t' is a 64-bit type and *int*
is a 32-bit type on the 64-bit machines. This silent truncation isn't
really valid, so fix up the variable's type.

Fixes: 59451e1233 ("mtd: spi-nor: change return value of read/write")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-11-02 12:16:37 +02:00
Mika Westerberg 5a0feb6287
mtd: spi-nor: intel-spi: Add support for Intel Comet Lake-H SPI serial flash
Intel Comet Lake-H PCH has the same SPI serial flash controller as Comet
Lake-LP. Add Comet Lake-H PCI ID to the driver list of supported devices.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-11-02 12:16:36 +02:00
Tudor Ambarus 0aa369540d
mtd: spi-nor: Print device info in case of error
Print identifying information about struct device.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-02 12:16:33 +02:00
Tudor Ambarus cc86f3e705
mtd: spi-nor: Constify data to write to the Status Register
Constify the data to write to the Status Register.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01 10:20:45 +02:00
Tudor Ambarus 4b3745361c
mtd: spi-nor: Fix retlen handling in sst_write()
In case the write of the first byte failed, retlen was incorrectly
incremented to *retlen += actual; on the exit path. retlen should be
incremented when actual data was written to the flash.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01 10:20:44 +02:00
Tudor Ambarus 70d2c6dcf8
mtd: spi-nor: Drop redundant error reports in Reg Ops callers
Drop the error messages from the callers, since the callees
already print an error message in case of failure.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01 10:20:43 +02:00
Tudor Ambarus b662d398cc
mtd: spi-nor: Pointer parameter for CR in spi_nor_read_cr()
Let the callers pass the pointer to the DMA-able buffer where
the value of the Configuration Register will be written. This way we
avoid the casts between int and u8, which can be confusing.

Callers stop compare the return value of spi_nor_read_cr() with negative,
spi_nor_read_cr() returns 0 on success and -errno otherwise.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01 10:20:36 +02:00
Tudor Ambarus 5ce1b49ccb
mtd: spi-nor: Pointer parameter for FSR in spi_nor_read_fsr()
Let the callers pass the pointer to the DMA-able buffer where
the value of the Flag Status Register will be written. This way we
avoid the casts between int and u8, which can be confusing.

Caller stops compare the return value of spi_nor_read_fsr() with negative,
spi_nor_read_fsr() returns 0 on success and -errno otherwise.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01 09:33:51 +02:00
Tudor Ambarus cd1718f5c4
mtd: spi-nor: Pointer parameter for SR in spi_nor_read_sr()
Let the callers pass the pointer to the DMA-able buffer where
the value of the Status Register will be written. This way we
avoid the casts between int and u8, which can be confusing.

Callers stop compare the return value of spi_nor_read_sr() with negative,
spi_nor_read_sr() returns 0 on success and -errno otherwise.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01 09:33:26 +02:00
Tudor Ambarus 7380f79c11
mtd: spi-nor: Don't overwrite errno from Reg Ops
Do not overwrite the error numbers received the Register Operations
methods.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01 08:29:35 +02:00
Tudor Ambarus 17ccd0e487
mtd: spi-nor: Drop explicit cast to int to already int value
ret is already of type int.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01 08:28:52 +02:00
Tudor Ambarus ebe04bfe26
mtd: spi-nor: Stop compare with negative in Reg Ops methods
spi_mem_exec_op()
nor->controller_ops->write_reg()
nor->controller_ops->read_reg()
spi_nor_wait_till_ready()
Return 0 on success, -errno otherwise.

Stop compare with negative and compare with zero in all the register
operations methods.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01 08:28:43 +02:00
Tudor Ambarus 502c4b0a14
mtd: spi-nor: Group all Reg Ops to avoid forward declarations
Group all register methods up in the file, to avoid forward
declarations.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01 08:28:38 +02:00
Tudor Ambarus 40b04958fa
mtd: spi-nor: Drop duplicated new line
Two new lines, one after another, drop one.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01 08:28:33 +02:00
Tudor Ambarus 567c2983ef
mtd: spi-nor: Prepend spi_nor_ to all Reg Ops methods
All the core functions should begin with "spi_nor_".

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01 08:27:22 +02:00
Tudor Ambarus a5c6603038
mtd: spi-nor: cadence-quadspi: Fix cqspi_command_read() definition
n_tx was never used, drop it. Replace 'const u8 *txbuf' with 'u8 opcode',
to comply with the SPI NOR int (*read_reg)() method. The 'const'
qualifier has no meaning for parameters passed by value, drop it.
Going furher, the opcode was passed to cqspi_calc_rdreg() and never used,
drop it.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-10-23 09:27:21 +03:00
Tudor Ambarus 4539778753
mtd: spi-nor: Introduce 'struct spi_nor_controller_ops'
Move all SPI NOR controller driver specific ops in a dedicated
structure. 'struct spi_nor' becomes lighter.

Use size_t for lengths in 'int (*write_reg)()' and 'int (*read_reg)()'.
Rename wite/read_buf to buf, the name of the functions are
suggestive enough. Constify buf in int (*write_reg). Comply with these
changes in the SPI NOR controller drivers.

Suggested-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-10-23 09:27:21 +03:00
Tudor Ambarus 1a21bdfeac
mtd: spi-nor: hisi-sfc: Drop nor->erase NULL assignment
The pointer to 'struct spi_nor' is kzalloc'ed above in the code.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-10-23 09:27:20 +03:00
DENG Qingfang 172b33212d
mtd: spi-nor: add support for en25qh16
Tested on HiWiFi C526A

Datasheet is available at:
http://www.xinyahong.com/upLoad/product/month_1411/201411201256018276.pdf

Signed-off-by: DENG Qingfang <dqfext@gmail.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-10-23 09:27:19 +03:00
Jethro Beekman 4b97ba73dc
mtd: spi-nor: intel-spi: add support for Intel Cannon Lake SPI flash
Now that SPI flash controllers without a software sequencer are
supported, it's trivial to add support for CNL and its PCI ID.

Values from https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/300-series-chipset-pch-datasheet-vol-2.pdf

Signed-off-by: Jethro Beekman <jethro@fortanix.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-10-23 09:27:18 +03:00
Jethro Beekman 3912970809
mtd: spi-nor: intel-spi: support chips without software sequencer
Some flash controllers don't have a software sequencer. Avoid
configuring the register addresses for it, and double check
everywhere that its not accidentally trying to be used.

Every use of `sregs` is now guarded by a check of `sregs` or
`swseq_reg`. The check might be done in the calling function.

Signed-off-by: Jethro Beekman <jethro@fortanix.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-10-23 09:27:15 +03:00
Stephen Boyd aab478ca0f mtd: Remove dev_err() usage after platform_get_irq()
We don't need dev_err() messages when platform_get_irq() fails now that
platform_get_irq() prints an error message itself when something goes
wrong. Let's remove these prints with a simple semantic patch.

// <smpl>
@@
expression ret;
struct platform_device *E;
@@

ret =
(
platform_get_irq(E, ...)
|
platform_get_irq_byname(E, ...)
);

if ( \( ret < 0 \| ret <= 0 \) )
{
(
-if (ret != -EPROBE_DEFER)
-{ ...
-dev_err(...);
-... }
|
...
-dev_err(...);
)
...
}
// </smpl>

While we're here, remove braces on if statements that only have one
statement (manually).

Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Richard Weinberger <richard@nod.at>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Cc: linux-mtd@lists.infradead.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-10-08 19:01:49 +02:00
Tudor Ambarus 41e086e155 mtd: spi-nor: Fix direction of the write_sr() transfer
write_sr() sends data to the SPI memory, fix the direction.

Fixes: b35b9a1036 ("mtd: spi-nor: Move m25p80 code in spi-nor.c")
Reported-by: John Garry <john.garry@huawei.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Tested-by: John Garry <john.garry@huawei.com>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-10-04 18:09:01 +02:00
Ashish Kumar 9607af6f85
mtd: spi-nor: Rename "n25q512a" to "mt25qu512a (n25q512a)"
n25q512a was rebranded to mt25qu512a after its spin off from STM.
mt25qu512a is different only in terms of operating frequency, the
JEDEC id is the same as in n25q512a.

Dual reads are supported (0x3b, 0x3c), set the SPI_NOR_DUAL_READ flag.
4-byte opcodes are supported, set the SPI_NOR_4B_OPCODES flag.

Tested Single I/O and QUAD I/O mode on LS1046FRWY.

Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
[tudor.ambarus@microchip.com: rename entry to "mt25qu512a (n25q512a)",
reword commit message, order entry by size, drop comment as it looked
redundant]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-08-30 10:11:50 +03:00
Ashish Kumar 173c3d4773
mtd: spi-nor: Add support for mt35xu02g
mt35xu02g is an Octal flash supporting Single and OCTAL I/O.
Tested on LS1028ARDB.

Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
[tudor.ambarus@microchip.com: reword commit message]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-08-30 10:07:34 +03:00