Граф коммитов

94998 Коммитов

Автор SHA1 Сообщение Дата
Ard Biesheuvel 8ceee72808 crypto: ghash-clmulni-intel - use C implementation for setkey()
The GHASH setkey() function uses SSE registers but fails to call
kernel_fpu_begin()/kernel_fpu_end(). Instead of adding these calls, and
then having to deal with the restriction that they cannot be called from
interrupt context, move the setkey() implementation to the C domain.

Note that setkey() does not use any particular SSE features and is not
expected to become a performance bottleneck.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: H. Peter Anvin <hpa@linux.intel.com>
Fixes: 0e1227d356 (crypto: ghash - Add PCLMULQDQ accelerated implementation)
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2014-04-01 17:22:47 +08:00
Christian Borntraeger 1b6a19b34d kvm/s390: also set guest pages back to stable on kexec/kdump
We need to reset the usage state of the pages on kexec/kdump,
which use subcode 0 and 1. We will only do the cmma reset in
the kernel, everything else is done in userspace as before.

Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2014-04-01 09:23:38 +02:00
Heiko Carstens 0ccc8b7ac8 s390/bitops,atomic: add missing memory barriers
When reworking the bitops and atomic ops I missed that those instructions
that got atomic behaviour only perform a "specific-operand-serialization"
instead of a full "serialization".
The compare-and-swap instruction used before performs a full serialization
before and after the instruction is executed, which means it has full
memory barrier semantics.
In order to give the new bitops and atomic ops functions also full memory
barrier semantics add a "bcr 14,0" before and after each of those new
instructions which performs full serialization as well.

This restores memory barrier semantics for bitops and atomic ops functions
which return values, like e.g. atomic_add_return(), but not for functions
which do not return a value, like e.g. atomic_add().
This is consistent to other architectures and what common code requires.

Cc: stable@vger.kernel.org # v3.13+
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2014-04-01 09:23:35 +02:00
Ramkumar Ramachandra 4c3b7df4ed avr32: replace simple_strtoul() with kstrtoul()
simple_strtoul() is marked for obsoletion; use the newer and more
pleasant kstrtoul() in its place.

Cc: Alexey Dobriyan <adobriyan@gmail.com>
Cc: Haavard Skinnemoen <hskinnemoen@gmail.com>
Cc: Hans-Christian Egtvedt <egtvedt@samfundet.no>
Signed-off-by: Ramkumar Ramachandra <artagnon@gmail.com>
Signed-off-by: Hans-Christian Egtvedt <egtvedt@samfundet.no>
2014-04-01 09:09:25 +02:00
Linus Torvalds 01d5f3b598 Merge branch 'for-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata
Pull libata updates from Tejun Heo:
 "A lot of activities on libata side this time.

   - A lot of changes around ahci.  Various embedded platforms are
     implementing ahci controllers.  Some were built atop ahci_platform,
     others were doing their own things.  Hans made some structural
     changes to libahci and librarized ahci_platform so that ahci
     platform drivers can share more common code.  A couple platform
     drivers are added on top of that and several are added to replace
     older drivers which were doing their own things (older ones are
     scheduled to be removed).

   - Dan finishes the patchset to make libata PM operations
     asynchronous.  Combined with one patch being routed through scsi,
     this should speed resume measurably.

   - Various fixes and cleanups from Bartlomiej and others"

* 'for-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata: (61 commits)
  ata: fix Marvell SATA driver dependencies
  ata: fix ARASAN CompactFlash PATA driver dependencies
  ata: remove superfluous casts
  ata: sata_highbank: remove superfluous cast
  ata: fix Calxeda Highbank SATA driver dependencies
  ata: fix R-Car SATA driver dependencies
  ARM: davinci: da850: update SATA AHCI support
  ata: add new-style AHCI platform driver for DaVinci DA850 AHCI controller
  ata: move library code from ahci_platform.c to libahci_platform.c
  ata: ahci_platform: fix ahci_platform_data->suspend method handling
  libata: remove unused ata_sas_port_async_resume() stub
  libata.h: add stub for ata_sas_port_resume
  libata: async resume
  libata, libsas: kill pm_result and related cleanup
  ata: Fix compiler warning with APM X-Gene host controller driver
  arm64: Add APM X-Gene SoC AHCI SATA host controller DTS entries
  ata: Add APM X-Gene SoC AHCI SATA host controller driver
  Documentation: Add documentation for the APM X-Gene SoC SATA host controller DTS binding
  arm64: Add APM X-Gene SoC 15Gbps Multi-purpose PHY DTS entries
  ata: ahci_sunxi: fix code formatting
  ...
2014-03-31 15:27:37 -07:00
Linus Torvalds 1ce235faa8 - KGDB support for arm64
- PCI I/O space extended to 16M (in preparation of PCIe support patches)
 - Dropping ZONE_DMA32 in favour of ZONE_DMA (we only need one for the
   time being), together with swiotlb late initialisation to correctly
   setup the bounce buffer
 - DMA API cache maintenance support (not all ARMv8 platforms have
   hardware cache coherency)
 - Crypto extensions advertising via ELF_HWCAP2 for compat user space
 - Perf support for dwarf unwinding in compat mode
 - asm/tlb.h converted to the generic mmu_gather code
 - asm-generic rwsem implementation
 - Code clean-up
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Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull ARM64 updates from Catalin Marinas:
 - KGDB support for arm64
 - PCI I/O space extended to 16M (in preparation of PCIe support
   patches)
 - Dropping ZONE_DMA32 in favour of ZONE_DMA (we only need one for the
   time being), together with swiotlb late initialisation to correctly
   setup the bounce buffer
 - DMA API cache maintenance support (not all ARMv8 platforms have
   hardware cache coherency)
 - Crypto extensions advertising via ELF_HWCAP2 for compat user space
 - Perf support for dwarf unwinding in compat mode
 - asm/tlb.h converted to the generic mmu_gather code
 - asm-generic rwsem implementation
 - Code clean-up

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (42 commits)
  arm64: Remove pgprot_dmacoherent()
  arm64: Support DMA_ATTR_WRITE_COMBINE
  arm64: Implement custom mmap functions for dma mapping
  arm64: Fix __range_ok macro
  arm64: Fix duplicated Kconfig entries
  arm64: mm: Route pmd thp functions through pte equivalents
  arm64: rwsem: use asm-generic rwsem implementation
  asm-generic: rwsem: de-PPCify rwsem.h
  arm64: enable generic CPU feature modalias matching for this architecture
  arm64: smp: make local symbol static
  arm64: debug: make local symbols static
  ARM64: perf: support dwarf unwinding in compat mode
  ARM64: perf: add support for frame pointer unwinding in compat mode
  ARM64: perf: add support for perf registers API
  arm64: Add boot time configuration of Intermediate Physical Address size
  arm64: Do not synchronise I and D caches for special ptes
  arm64: Make DMA coherent and strongly ordered mappings not executable
  arm64: barriers: add dmb barrier
  arm64: topology: Implement basic CPU topology support
  arm64: advertise ARMv8 extensions to 32-bit compat ELF binaries
  ...
2014-03-31 15:01:45 -07:00
Linus Torvalds e38be1b106 Miscellaneous ia64 fixes for 3.15 merge window
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Merge tag 'please-pull-misc-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux

Pull ia64 updates from Tony Luck:
 "Miscellaneous ia64 fixes for 3.15 merge window"

* tag 'please-pull-misc-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux:
  [IA64] Keep format strings from leaking into printk
  Fix warning in make defconfig
  [IA64] sba_iommu: fix section mismatch To: linux-kernel@vger.kernel.org
2014-03-31 15:01:16 -07:00
Linus Torvalds f24279172d Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/linux-m68k
Pull m68k updates from Geert Uytterhoeven.

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/linux-m68k:
  m68k: Update defconfigs for v3.14-rc1
  [SCSI] atari_scsi: Fix sleep_on race
  m68k: head.S - Remove bogus L prefix in comment
  m68k: Remove dead code
  m68k: Remove CONSOLE_PENGUIN macro, adopt CONFIG_LOGO
2014-03-31 15:00:32 -07:00
Linus Torvalds 1f8c538ed6 Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux
Pull s390 updates from Martin Schwidefsky:
 "There are two memory management related changes, the CMMA support for
  KVM to avoid swap-in of freed pages and the split page table lock for
  the PMD level.  These two come with common code changes in mm/.

  A fix for the long standing theoretical TLB flush problem, this one
  comes with a common code change in kernel/sched/.

  Another set of changes is Heikos uaccess work, included is the initial
  set of patches with more to come.

  And fixes and cleanups as usual"

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux: (36 commits)
  s390/con3270: optionally disable auto update
  s390/mm: remove unecessary parameter from pgste_ipte_notify
  s390/mm: remove unnecessary parameter from gmap_do_ipte_notify
  s390/mm: fixing comment so that parameter name match
  s390/smp: limit number of cpus in possible cpu mask
  hypfs: Add clarification for "weight_min" attribute
  s390: update defconfigs
  s390/ptrace: add support for PTRACE_SINGLEBLOCK
  s390/perf: make print_debug_cf() static
  s390/topology: Remove call to update_cpu_masks()
  s390/compat: remove compat exec domain
  s390: select CONFIG_TTY for use of tty in unconditional keyboard driver
  s390/appldata_os: fix cpu array size calculation
  s390/checksum: remove memset() within csum_partial_copy_from_user()
  s390/uaccess: remove copy_from_user_real()
  s390/sclp_early: Return correct HSA block count also for zero
  s390: add some drivers/subsystems to the MAINTAINERS file
  s390: improve debug feature usage
  s390/airq: add support for irq ranges
  s390/mm: enable split page table lock for PMD level
  ...
2014-03-31 14:35:30 -07:00
Linus Torvalds 190f918660 Merge branch 'compat' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux
Pull s390 compat wrapper rework from Heiko Carstens:
 "S390 compat system call wrapper simplification work.

  The intention of this work is to get rid of all hand written assembly
  compat system call wrappers on s390, which perform proper sign or zero
  extension, or pointer conversion of compat system call parameters.
  Instead all of this should be done with C code eg by using Al's
  COMPAT_SYSCALL_DEFINEx() macro.

  Therefore all common code and s390 specific compat system calls have
  been converted to the COMPAT_SYSCALL_DEFINEx() macro.

  In order to generate correct code all compat system calls may only
  have eg compat_ulong_t parameters, but no unsigned long parameters.
  Those patches which change parameter types from unsigned long to
  compat_ulong_t parameters are separate in this series, but shouldn't
  cause any harm.

  The only compat system calls which intentionally have 64 bit
  parameters (preadv64 and pwritev64) in support of the x86/32 ABI
  haven't been changed, but are now only available if an architecture
  defines __ARCH_WANT_COMPAT_SYS_PREADV64/PWRITEV64.

  System calls which do not have a compat variant but still need proper
  zero extension on s390, like eg "long sys_brk(unsigned long brk)" will
  get a proper wrapper function with the new s390 specific
  COMPAT_SYSCALL_WRAPx() macro:

     COMPAT_SYSCALL_WRAP1(brk, unsigned long, brk);

  which generates the following code (simplified):

     asmlinkage long sys_brk(unsigned long brk);
     asmlinkage long compat_sys_brk(long brk)
     {
         return sys_brk((u32)brk);
     }

  Given that the C file which contains all the COMPAT_SYSCALL_WRAP lines
  includes both linux/syscall.h and linux/compat.h, it will generate
  build errors, if the declaration of sys_brk() doesn't match, or if
  there exists a non-matching compat_sys_brk() declaration.

  In addition this will intentionally result in a link error if
  somewhere else a compat_sys_brk() function exists, which probably
  should have been used instead.  Two more BUILD_BUG_ONs make sure the
  size and type of each compat syscall parameter can be handled
  correctly with the s390 specific macros.

  I converted the compat system calls step by step to verify the
  generated code is correct and matches the previous code.  In fact it
  did not always match, however that was always a bug in the hand
  written asm code.

  In result we get less code, less bugs, and much more sanity checking"

* 'compat' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux: (44 commits)
  s390/compat: add copyright statement
  compat: include linux/unistd.h within linux/compat.h
  s390/compat: get rid of compat wrapper assembly code
  s390/compat: build error for large compat syscall args
  mm/compat: convert to COMPAT_SYSCALL_DEFINE with changing parameter types
  kexec/compat: convert to COMPAT_SYSCALL_DEFINE with changing parameter types
  net/compat: convert to COMPAT_SYSCALL_DEFINE with changing parameter types
  ipc/compat: convert to COMPAT_SYSCALL_DEFINE with changing parameter types
  fs/compat: convert to COMPAT_SYSCALL_DEFINE with changing parameter types
  ipc/compat: convert to COMPAT_SYSCALL_DEFINE
  fs/compat: convert to COMPAT_SYSCALL_DEFINE
  security/compat: convert to COMPAT_SYSCALL_DEFINE
  mm/compat: convert to COMPAT_SYSCALL_DEFINE
  net/compat: convert to COMPAT_SYSCALL_DEFINE
  kernel/compat: convert to COMPAT_SYSCALL_DEFINE
  fs/compat: optional preadv64/pwrite64 compat system calls
  ipc/compat_sys_msgrcv: change msgtyp type from long to compat_long_t
  s390/compat: partial parameter conversion within syscall wrappers
  s390/compat: automatic zero, sign and pointer conversion of syscalls
  s390/compat: add sync_file_range and fallocate compat syscalls
  ...
2014-03-31 14:32:17 -07:00
Linus Torvalds 176ab02d49 Merge branch 'x86-asmlinkage-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 LTO changes from Peter Anvin:
 "More infrastructure work in preparation for link-time optimization
  (LTO).  Most of these changes is to make sure symbols accessed from
  assembly code are properly marked as visible so the linker doesn't
  remove them.

  My understanding is that the changes to support LTO are still not
  upstream in binutils, but are on the way there.  This patchset should
  conclude the x86-specific changes, and remaining patches to actually
  enable LTO will be fed through the Kbuild tree (other than keeping up
  with changes to the x86 code base, of course), although not
  necessarily in this merge window"

* 'x86-asmlinkage-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (25 commits)
  Kbuild, lto: Handle basic LTO in modpost
  Kbuild, lto: Disable LTO for asm-offsets.c
  Kbuild, lto: Add a gcc-ld script to let run gcc as ld
  Kbuild, lto: add ld-version and ld-ifversion macros
  Kbuild, lto: Drop .number postfixes in modpost
  Kbuild, lto, workaround: Don't warn for initcall_reference in modpost
  lto: Disable LTO for sys_ni
  lto: Handle LTO common symbols in module loader
  lto, workaround: Add workaround for initcall reordering
  lto: Make asmlinkage __visible
  x86, lto: Disable LTO for the x86 VDSO
  initconst, x86: Fix initconst mistake in ts5500 code
  initconst: Fix initconst mistake in dcdbas
  asmlinkage: Make trace_hardirqs_on/off_caller visible
  asmlinkage, x86: Fix 32bit memcpy for LTO
  asmlinkage Make __stack_chk_failed and memcmp visible
  asmlinkage: Mark rwsem functions that can be called from assembler asmlinkage
  asmlinkage: Make main_extable_sort_needed visible
  asmlinkage, mutex: Mark __visible
  asmlinkage: Make trace_hardirq visible
  ...
2014-03-31 14:13:25 -07:00
Neil Horman 6f8a1b335f x86: Adjust irq remapping quirk for older revisions of 5500/5520 chipsets
Commit 03bbcb2e7e (iommu/vt-d: add quirk for broken interrupt
remapping on 55XX chipsets) properly disables irq remapping on the
5500/5520 chipsets that don't correctly perform that feature.

However, when I wrote it, I followed the errata sheet linked in that
commit too closely, and explicitly tied the activation of the quirk to
revision 0x13 of the chip, under the assumption that earlier revisions
were not in the field.  Recently a system was reported to be suffering
from this remap bug and the quirk hadn't triggered, because the
revision id register read at a lower value that 0x13, so the quirk
test failed improperly.  Given this, it seems only prudent to adjust
this quirk so that any revision less than 0x13 has the quirk asserted.

[ tglx: Removed the 0x12 comparison of pci id 3405 as this is covered
    	by the <= 0x13 check already ]

Signed-off-by: Neil Horman <nhorman@tuxdriver.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: x86@kernel.org
Cc: stable@vger.kernel.org
Link: http://lkml.kernel.org/r/1394649873-14913-1-git-send-email-nhorman@tuxdriver.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-31 22:07:01 +02:00
Linus Torvalds e06df6a7ea Merge branch 'x86-kaslr-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 kaslr update from Ingo Molnar:
 "This adds kernel module load address randomization"

* 'x86-kaslr-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86, kaslr: fix module lock ordering problem
  x86, kaslr: randomize module base load address
2014-03-31 12:34:49 -07:00
Linus Torvalds c0fc3cbac0 Merge branch 'x86-hyperv-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 hyperv change from Ingo Molnar:
 "Skip the timer_irq_works() check on hyperv systems"

* 'x86-hyperv-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86, hyperv: Bypass the timer_irq_works() check
2014-03-31 12:28:38 -07:00
Linus Torvalds d9fcca40eb Merge branch 'x86-hash-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 hashing changes from Ingo Molnar:
 "Small fixes and cleanups to the librarized arch_fast_hash() methods,
  used by the net/openvswitch code"

* 'x86-hash-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86, hash: Simplify switch, add __init annotation
  x86, hash: Swap arguments passed to crc32_u32()
  x86, hash: Fix build failure with older binutils
2014-03-31 12:27:32 -07:00
Linus Torvalds 7cc3afdf43 Merge branch 'x86-efi-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 EFI changes from Ingo Molnar:
 "The main changes:

  - Add debug code to the dump EFI pagetable - Borislav Petkov

  - Make 1:1 runtime mapping robust when booting on machines with lots
    of memory - Borislav Petkov

  - Move the EFI facilities bits out of 'x86_efi_facility' and into
    efi.flags which is the standard architecture independent place to
    keep EFI state, by Matt Fleming.

  - Add 'EFI mixed mode' support: this allows 64-bit kernels to be
    booted from 32-bit firmware.  This needs a bootloader that supports
    the 'EFI handover protocol'.  By Matt Fleming"

* 'x86-efi-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (31 commits)
  x86, efi: Abstract x86 efi_early calls
  x86/efi: Restore 'attr' argument to query_variable_info()
  x86/efi: Rip out phys_efi_get_time()
  x86/efi: Preserve segment registers in mixed mode
  x86/boot: Fix non-EFI build
  x86, tools: Fix up compiler warnings
  x86/efi: Re-disable interrupts after calling firmware services
  x86/boot: Don't overwrite cr4 when enabling PAE
  x86/efi: Wire up CONFIG_EFI_MIXED
  x86/efi: Add mixed runtime services support
  x86/efi: Firmware agnostic handover entry points
  x86/efi: Split the boot stub into 32/64 code paths
  x86/efi: Add early thunk code to go from 64-bit to 32-bit
  x86/efi: Build our own EFI services pointer table
  efi: Add separate 32-bit/64-bit definitions
  x86/efi: Delete dead code when checking for non-native
  x86/mm/pageattr: Always dump the right page table in an oops
  x86, tools: Consolidate #ifdef code
  x86/boot: Cleanup header.S by removing some #ifdefs
  efi: Use NULL instead of 0 for pointer
  ...
2014-03-31 12:26:05 -07:00
Linus Torvalds ad8946fbf9 Merge branch 'x86-debug-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 debug cleanup from Ingo Molnar:
 "A single trivial cleanup"

* 'x86-debug-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  i386: Remove unneeded test of 'task' in dump_trace() (again)
2014-03-31 12:25:28 -07:00
Linus Torvalds 918d80a136 Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 cpu handling changes from Ingo Molnar:
 "Bigger changes:

   - Intel CPU hardware-enablement: new vector instructions support
     (AVX-512), by Fenghua Yu.

   - Support the clflushopt instruction and use it in appropriate
     places.  clflushopt is similar to clflush but with more relaxed
     ordering, by Ross Zwisler.

   - MSR accessor cleanups, by Borislav Petkov.

   - 'forcepae' boot flag for those who have way too much time to spend
     on way too old Pentium-M systems and want to live way too
     dangerously, by Chris Bainbridge"

* 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86, cpu: Add forcepae parameter for booting PAE kernels on PAE-disabled Pentium M
  Rename TAINT_UNSAFE_SMP to TAINT_CPU_OUT_OF_SPEC
  x86, intel: Make MSR_IA32_MISC_ENABLE bit constants systematic
  x86, Intel: Convert to the new bit access MSR accessors
  x86, AMD: Convert to the new bit access MSR accessors
  x86: Add another set of MSR accessor functions
  x86: Use clflushopt in drm_clflush_virt_range
  x86: Use clflushopt in drm_clflush_page
  x86: Use clflushopt in clflush_cache_range
  x86: Add support for the clflushopt instruction
  x86, AVX-512: Enable AVX-512 States Context Switch
  x86, AVX-512: AVX-512 Feature Detection
2014-03-31 12:00:45 -07:00
Linus Torvalds 26a5c0dfbc Merge branch 'x86-cleanups-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 cleanups from Ingo Molnar:
 "Various smaller cleanups"

* 'x86-cleanups-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86, pageattr: Correct WBINVD spelling in comment
  x86, crash: Unify ifdef
  x86, boot: Correct max ramdisk size name
2014-03-31 12:00:10 -07:00
Linus Torvalds 54cad6270a Merge branch 'x86-build-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 build change from Ingo Molnar:
 "Explicitly disable x87 FPU instructions, to catch mistaken floating
  point use at build time, instead of crashing or misbehaving during run
  time"

* 'x86-build-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86: Disable generation of traditional x87 instructions
2014-03-31 11:59:31 -07:00
Linus Torvalds 6ed7705167 Merge branch 'x86-apic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 apic changes from Ingo Molnar:
 "An xAPIC CPU hotplug race fix, plus cleanups and minor fixes"

* 'x86-apic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/apic: Plug racy xAPIC access of CPU hotplug code
  x86/apic: Always define nox2apic and define it as initdata
  x86/apic: Remove unused function prototypes
  x86/apic: Switch wait_for_init_deassert() to a bool flag
  x86/apic: Only use default_wait_for_init_deassert()
2014-03-31 11:58:45 -07:00
Linus Torvalds 3a88fe3b74 Merge branch 'x86-acpi-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 acpi numa fix from Ingo Molnar:
 "A single NUMA CPU hotplug fix"

* 'x86-acpi-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86, acpi: Fix bug in associating hot-added CPUs with corresponding NUMA node
2014-03-31 11:58:08 -07:00
Linus Torvalds 971eae7c99 Merge branch 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull scheduler changes from Ingo Molnar:
 "Bigger changes:

   - sched/idle restructuring: they are WIP preparation for deeper
     integration between the scheduler and idle state selection, by
     Nicolas Pitre.

   - add NUMA scheduling pseudo-interleaving, by Rik van Riel.

   - optimize cgroup context switches, by Peter Zijlstra.

   - RT scheduling enhancements, by Thomas Gleixner.

  The rest is smaller changes, non-urgnt fixes and cleanups"

* 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (68 commits)
  sched: Clean up the task_hot() function
  sched: Remove double calculation in fix_small_imbalance()
  sched: Fix broken setscheduler()
  sparc64, sched: Remove unused sparc64_multi_core
  sched: Remove unused mc_capable() and smt_capable()
  sched/numa: Move task_numa_free() to __put_task_struct()
  sched/fair: Fix endless loop in idle_balance()
  sched/core: Fix endless loop in pick_next_task()
  sched/fair: Push down check for high priority class task into idle_balance()
  sched/rt: Fix picking RT and DL tasks from empty queue
  trace: Replace hardcoding of 19 with MAX_NICE
  sched: Guarantee task priority in pick_next_task()
  sched/idle: Remove stale old file
  sched: Put rq's sched_avg under CONFIG_FAIR_GROUP_SCHED
  cpuidle/arm64: Remove redundant cpuidle_idle_call()
  cpuidle/powernv: Remove redundant cpuidle_idle_call()
  sched, nohz: Exclude isolated cores from load balancing
  sched: Fix select_task_rq_fair() description comments
  workqueue: Replace hardcoding of -20 and 19 with MIN_NICE and MAX_NICE
  sys: Replace hardcoding of -20 and 19 with MIN_NICE and MAX_NICE
  ...
2014-03-31 11:21:19 -07:00
Linus Torvalds 8c292f1174 Merge branch 'perf-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull perf changes from Ingo Molnar:
 "Main changes:

  Kernel side changes:

   - Add SNB/IVB/HSW client uncore memory controller support (Stephane
     Eranian)

   - Fix various x86/P4 PMU driver bugs (Don Zickus)

  Tooling, user visible changes:

   - Add several futex 'perf bench' microbenchmarks (Davidlohr Bueso)

   - Speed up thread map generation (Don Zickus)

   - Introduce 'perf kvm --list-cmds' command line option for use by
     scripts (Ramkumar Ramachandra)

   - Print the evsel name in the annotate stdio output, prep to fix
     support outputting annotation for multiple events, not just for the
     first one (Arnaldo Carvalho de Melo)

   - Allow setting preferred callchain method in .perfconfig (Jiri Olsa)

   - Show in what binaries/modules 'perf probe's are set (Masami
     Hiramatsu)

   - Support distro-style debuginfo for uprobe in 'perf probe' (Masami
     Hiramatsu)

  Tooling, internal changes and fixes:

   - Use tid in mmap/mmap2 events to find maps (Don Zickus)

   - Record the reason for filtering an address_location (Namhyung Kim)

   - Apply all filters to an addr_location (Namhyung Kim)

   - Merge al->filtered with hist_entry->filtered in report/hists
     (Namhyung Kim)

   - Fix memory leak when synthesizing thread records (Namhyung Kim)

   - Use ui__has_annotation() in 'report' (Namhyung Kim)

   - hists browser refactorings to reuse code accross UIs (Namhyung Kim)

   - Add support for the new DWARF unwinder library in elfutils (Jiri
     Olsa)

   - Fix build race in the generation of bison files (Jiri Olsa)

   - Further streamline the feature detection display, trimming it a bit
     to show just the libraries detected, using VF=1 gets a more verbose
     output, showing the less interesting feature checks as well (Jiri
     Olsa).

   - Check compatible symtab type before loading dso (Namhyung Kim)

   - Check return value of filename__read_debuglink() (Stephane Eranian)

   - Move some hashing and fs related code from tools/perf/util/ to
     tools/lib/ so that it can be used by more tools/ living utilities
     (Borislav Petkov)

   - Prepare DWARF unwinding code for using an elfutils alternative
     unwinding library (Jiri Olsa)

   - Fix DWARF unwind max_stack processing (Jiri Olsa)

   - Add dwarf unwind 'perf test' entry (Jiri Olsa)

   - 'perf probe' improvements including memory leak fixes, sharing the
     intlist class with other tools, uprobes/kprobes code sharing and
     use of ref_reloc_sym (Masami Hiramatsu)

   - Shorten sample symbol resolving by adding cpumode to struct
     addr_location (Arnaldo Carvalho de Melo)

   - Fix synthesizing mmaps for threads (Don Zickus)

   - Fix invalid output on event group stdio report (Namhyung Kim)

   - Fixup header alignment in 'perf sched latency' output (Ramkumar
     Ramachandra)

   - Fix off-by-one error in 'perf timechart record' argv handling
     (Ramkumar Ramachandra)

  Tooling, cleanups:

   - Remove unused thread__find_map function (Jiri Olsa)

   - Remove unused simple_strtoul() function (Ramkumar Ramachandra)

  Tooling, documentation updates:

   - Update function names in debug messages (Ramkumar Ramachandra)

   - Update some code references in design.txt (Ramkumar Ramachandra)

   - Clarify load-latency information in the 'perf mem' docs (Andi
     Kleen)

   - Clarify x86 register naming in 'perf probe' docs (Andi Kleen)"

* 'perf-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (96 commits)
  perf tools: Remove unused simple_strtoul() function
  perf tools: Update some code references in design.txt
  perf evsel: Update function names in debug messages
  perf tools: Remove thread__find_map function
  perf annotate: Print the evsel name in the stdio output
  perf report: Use ui__has_annotation()
  perf tools: Fix memory leak when synthesizing thread records
  perf tools: Use tid in mmap/mmap2 events to find maps
  perf report: Merge al->filtered with hist_entry->filtered
  perf symbols: Apply all filters to an addr_location
  perf symbols: Record the reason for filtering an address_location
  perf sched: Fixup header alignment in 'latency' output
  perf timechart: Fix off-by-one error in 'record' argv handling
  perf machine: Factor machine__find_thread to take tid argument
  perf tools: Speed up thread map generation
  perf kvm: introduce --list-cmds for use by scripts
  perf ui hists: Pass evsel to hpp->header/width functions explicitly
  perf symbols: Introduce thread__find_cpumode_addr_location
  perf session: Change header.misc dump from decimal to hex
  perf ui/tui: Reuse generic __hpp__fmt() code
  ...
2014-03-31 11:13:25 -07:00
Linus Torvalds 462bf234a8 Merge branch 'core-locking-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull core locking updates from Ingo Molnar:
 "The biggest change is the MCS spinlock generalization changes from Tim
  Chen, Peter Zijlstra, Jason Low et al.  There's also lockdep
  fixes/enhancements from Oleg Nesterov, in particular a false negative
  fix related to lockdep_set_novalidate_class() usage"

* 'core-locking-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (22 commits)
  locking/mutex: Fix debug checks
  locking/mutexes: Add extra reschedule point
  locking/mutexes: Introduce cancelable MCS lock for adaptive spinning
  locking/mutexes: Unlock the mutex without the wait_lock
  locking/mutexes: Modify the way optimistic spinners are queued
  locking/mutexes: Return false if task need_resched() in mutex_can_spin_on_owner()
  locking: Move mcs_spinlock.h into kernel/locking/
  m68k: Skip futex_atomic_cmpxchg_inatomic() test
  futex: Allow architectures to skip futex_atomic_cmpxchg_inatomic() test
  Revert "sched/wait: Suppress Sparse 'variable shadowing' warning"
  lockdep: Change lockdep_set_novalidate_class() to use _and_name
  lockdep: Change mark_held_locks() to check hlock->check instead of lockdep_no_validate
  lockdep: Don't create the wrong dependency on hlock->check == 0
  lockdep: Make held_lock->check and "int check" argument bool
  locking/mcs: Allow architecture specific asm files to be used for contended case
  locking/mcs: Order the header files in Kbuild of each architecture in alphabetical order
  sched/wait: Suppress Sparse 'variable shadowing' warning
  hung_task/Documentation: Fix hung_task_warnings description
  locking/mcs: Allow architectures to hook in to contended paths
  locking/mcs: Micro-optimize the MCS code, add extra comments
  ...
2014-03-31 10:59:39 -07:00
Ralf Baechle ade63aada7 Merge branch '3.14-fixes' into mips-for-linux-next 2014-03-31 18:17:33 +02:00
Paul Burton 9a1724c750 MIPS: CPC: Use __raw_ memory access functions
The CPC registers use native endianness, so using plain readl & writel
will produce incorrect results on big endian systems.

Reported-by: Jeffrey Deans <jeffrey.deans@imgtec.com>
Reported-by: Keng Koh <keng.koh@imgtec.com>
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6657/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:13 +02:00
Paul Burton cd21754660 MIPS: CM: use __raw_ memory access functions
The CM registers use native endianness, so using plain readl & writel
will produce incorrect results on big endian systems.

Reported-by: Jeffrey Deans <jeffrey.deans@imgtec.com>
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6656/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:13 +02:00
Paul Burton b966087b51 MIPS: Fix warning when including smp-ops.h with CONFIG_SMP=n
The gic_send_ipi_mask function declared in smp-ops.h takes a struct
cpumask argument, but linux/cpumask.h is only included within an #ifdef
CONFIG_SMP. Move the gic_ function declarations within that #ifdef too
to fix warnings during build such as:

In file included from arch/mips/fw/arc/init.c:15:0:
/mnt/buildbot/kernel/mips/slave/mips-linux__allno_/build/arch/mips/include/asm/smp-ops.h:62:44:
warning: 'struct cpumask' declared inside parameter list [enabled by
default]
 extern void gic_send_ipi_mask(const struct cpumask *mask, unsigned int
action);

Reported-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6655/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:13 +02:00
Paul Burton 45b2957804 MIPS: Malta: GIC IPIs may be used without MT
It's perfectly valid to use SMP on a non-MT CPU and use the GIC for
IPIs. Set them up conditional upon CONFIG_MIPS_GIC_IPI rather than
CONFIG_MIPS_MT_SMP.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Paul Burton <paul.burton@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/6654/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Paul Burton 0c2cb004b2 MIPS: smp-mt: Use common GIC IPI implementation
Rather than duplicating the GIC IPI send function, share the one already
used by CONFIG_MIPS_CPS & CONFIG_MIPS_CMP.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Paul Burton <paul.burton@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/6653/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Paul Burton f0cff5c86f MIPS: smp-cmp: Remove incorrect core number probe
This probing is already done by decode_configs as part of cpu_probe, and
furthermore the implementation here was incorrect for any MT core with
a number of VPEs other than 2.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6650/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Ralf Baechle a809d46066 MIPS: Fix gigaton of warning building with microMIPS.
With binutils 2.24 the attempt to switch with microMIPS mode to MIPS III
mode through .set mips3 results in *lots* of warnings like

{standard input}: Assembler messages:
{standard input}:397: Warning: the 64-bit MIPS architecture does not support the `smartmips' extension

during a kernel build.  Fixed by using .set arch=r4000 instead.

This breaks support for building the kernel with binutils 2.13 which
was supported for 32 bit kernels only anyway and 2.14 which was a bad
vintage for MIPS anyway.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Paul Burton 30ee615bb8 MIPS: Fix core number detection for MT cores
In cores which implement the MT ASE, the CPUNum in the EBase register is
a concatenation of the core number & the VPE ID within that core. In
order to retrieve the correct core number CPUNum must be shifted
appropriately to remove the VPE ID bits.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6666/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Paul Burton 968a0734db MIPS: MT: core_nvpes function to retrieve VPE count
This function simply returns the number of VPEs present in the current
core, or 1 if the core does not implement the MT ASE. In SMP kernels
this will typically equal smp_num_siblings, however it will also be
usable in UP kernels and helps prepare for the possibility of a
heterogenous system where the VPE count is not the same across all
cores.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6665/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Paul Burton d94c90f805 MIPS: Provide empty mips_mt_set_cpuoptions when CONFIG_MIPS_MT=n
Both the CONFIG_MIPS_CPS & CONFIG_MIPS_CMP SMP implementations call
mips_mt_set_cpuoptions when preparing to start secondary CPUs. However
both may be used without MT. Provide an empty inline function to prevent
a link error in this case.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6647/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Julia Lawall 49992cb1db MIPS: Lasat: Replace del_timer by del_timer_sync
Use del_timer_sync to ensure that the timer is stopped on all CPUs before
the driver exists.

This change was suggested by Thomas Gleixner

The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)

// <smpl>
@r@
declarer name module_exit;
identifier ex;
@@

module_exit(ex);

@@
identifier r.ex;
@@

ex(...) {
  <...
- del_timer
+ del_timer_sync
    (...)
  ...>
}
// </smpl>

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Cc: kernel-janitors@vger.kernel.org
Cc: tglx@linutronix.de
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/6663/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Paul Burton fa12b773b7 MIPS: Malta: Setup PM I/O region on boot
This patch ensures that the kernel sets a sane base address for the
PIIX4 PM I/O register region during boot. Without this the kernel may
not successfully claim the region as a resource if the bootloader didn't
configure the region. With this patch the kernel will always succeed
with:

  pci 0000:00:0a.3: quirk: [io  0x1000-0x103f] claimed by PIIX4 ACPI

The lack of the resource claiming is easily reproducible without this
patch using current versions of QEMU.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Tested-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6641/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Huacai Chen 024e6a8b5b MIPS: Loongson: Add a Loongson-3 default config file
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Hongliang Tao <taohl@lemote.com>
Signed-off-by: Hua Yan <yanh@lemote.com>
Tested-by: Alex Smith <alex.smith@imgtec.com>
Reviewed-by: Alex Smith <alex.smith@imgtec.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/6640
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Huacai Chen c4a987db1b MIPS: Loongson 3: Add CPU hotplug support
Tips of Loongson's CPU hotplug:
1, To fully shutdown a core in Loongson 3, the target core should go to
   CKSEG1 and flush all L1 cache entries at first. Then, another core
   (usually Core 0) can safely disable the clock of the target core. So
   play_dead() call loongson3_play_dead() via CKSEG1 (both uncached and
   unmmaped).
2, The default clocksource of Loongson is MIPS. Since clock source is a
   global device, timekeeping need the CP0' Count registers of each core
   be synchronous. Thus, when a core is up, we use a SMP_ASK_C0COUNT IPI
   to ask Core-0's Count.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Hongliang Tao <taohl@lemote.com>
Signed-off-by: Hua Yan <yanh@lemote.com>
Tested-by: Alex Smith <alex.smith@imgtec.com>
Reviewed-by: Alex Smith <alex.smith@imgtec.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/6639
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Huacai Chen 300459d558 MIPS: Loongson 3: Add Loongson-3 SMP support
IPI registers of Loongson-3 include IPI_SET, IPI_CLEAR, IPI_STATUS,
IPI_EN and IPI_MAILBOX_BUF. Each bit of IPI_STATUS indicate a type of
IPI and IPI_EN indicate whether the IPI is enabled. The sender write 1
to IPI_SET bits generate IPIs in IPI_STATUS, and receiver write 1 to
bits of IPI_CLEAR to clear IPIs. IPI_MAILBOX_BUF are used to deliver
more information about IPIs.

Why we change code in arch/mips/loongson/common/setup.c?

If without this change, when SMP configured, system cannot boot since
it hang at printk() in cgroup_init_early(). The root cause is:

console_trylock()
  \-->down_trylock(&console_sem)
    \-->raw_spin_unlock_irqrestore(&sem->lock, flags)
      \-->_raw_spin_unlock_irqrestore()(SMP/UP have different versions)
        \-->__raw_spin_unlock_irqrestore()  (following is the SMP case)
          \-->do_raw_spin_unlock()
            \-->arch_spin_unlock()
              \-->nudge_writes()
                \-->mb()
                  \-->wbflush()
                    \-->__wbflush()

In previous code __wbflush() is initialized in plat_mem_setup(), but
cgroup_init_early() is called before plat_mem_setup(). Therefore, In
this patch we make changes to avoid boot failure.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Hongliang Tao <taohl@lemote.com>
Signed-off-by: Hua Yan <yanh@lemote.com>
Tested-by: Alex Smith <alex.smith@imgtec.com>
Reviewed-by: Alex Smith <alex.smith@imgtec.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/6638
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Huacai Chen 0e476d9124 MIPS: Loongson: Add Loongson-3 Kconfig options
Added Kconfig options include: Loongson-3 CPU and machine definition,
CPU cache features, UEFI-like firmware interface (LEFI), HT-linked PCI,
and swiotlb support.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Hongliang Tao <taohl@lemote.com>
Signed-off-by: Hua Yan <yanh@lemote.com>
Tested-by: Alex Smith <alex.smith@imgtec.com>
Reviewed-by: Alex Smith <alex.smith@imgtec.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/6637
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Huacai Chen 1299b0e05e MIPS: Loongson: Add swiotlb to support All-Memory DMA
Loongson doesn't support DMA address above 4GB traditionally. If memory
is more than 4GB, CONFIG_SWIOTLB and ZONE_DMA32 should be selected. In
this way, DMA pages are allocated below 4GB preferably. However, if low
memory is not enough, high pages are allocated and swiotlb is used for
bouncing.

Moreover, we provide a platform-specific dma_map_ops::set_dma_mask() to
set a device's dma_mask and coherent_dma_mask. We use these masks to
distinguishes an allocated page can be used for DMA directly, or need
swiotlb to bounce.

Recently, we found that 32-bit DMA isn't a hardware bug, but a hardware
configuration issue. So, latest firmware has enable the DMA support as
high as 40-bit. To support all-memory DMA for all devices (besides the
Loongson platform limit, there are still some devices have their own
DMA32 limit), and also to be compatible with old firmware, we keep use
swiotlb.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Hongliang Tao <taohl@lemote.com>
Signed-off-by: Hua Yan <yanh@lemote.com>
Tested-by: Alex Smith <alex.smith@imgtec.com>
Reviewed-by: Alex Smith <alex.smith@imgtec.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/6636
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Huacai Chen 7546d2f48d MIPS: Loongson 3: Add serial port support
Loongson family machines has three types of serial port: PCI UART, LPC
UART and CPU internal UART. Loongson-2E and parts of Loongson-2F based
machines use PCI UART; most Loongson-2F based machines use LPC UART;
Loongson-2G/3A has both LPC and CPU UART but usually use CPU UART.

Port address of UARTs:
CPU UART: REG_BASE + OFFSET;
LPC UART: LIO1_BASE + OFFSET;
PCI UART: PCIIO_BASE + OFFSET.

Since LPC UART are linked in "Local Bus", both CPU UART and LPC UART
are called "CPU provided serial port".

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Hongliang Tao <taohl@lemote.com>
Signed-off-by: Hua Yan <yanh@lemote.com>
Tested-by: Alex Smith <alex.smith@imgtec.com>
Reviewed-by: Alex Smith <alex.smith@imgtec.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/6635
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Huacai Chen d788bfa900 MIPS: Loongson 3: Add IRQ init and dispatch support
IRQ routing path of Loongson-3:
Devices(most) --> I8259 --> HT Controller --> IRQ Routing Table --> CPU
                                                  ^
                                                  |
Device(legacy devices such as UART) --> Bonito ---|

IRQ Routing Table route 32 INTs to CPU's INT0~INT3(IP2~IP5 of CP0), 32
INTs include 16 HT INTs(mostly), 4 PCI INTs, 1 LPC INT, etc. IP6 is used
for IPI and IP7 is used for internal MIPS timer. LOONGSON_INT_ROUTER_*
are IRQ Routing Table registers.

I8259 IRQs are 1:1 mapped to HT1 INTs. LOONGSON_HT1_* are configuration
registers of HT1 controller.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Hongliang Tao <taohl@lemote.com>
Signed-off-by: Hua Yan <yanh@lemote.com>
Tested-by: Alex Smith <alex.smith@imgtec.com>
Reviewed-by: Alex Smith <alex.smith@imgtec.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/6634
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Huacai Chen c7d3555ac0 MIPS: Loongson 3: Add HT-linked PCI support
Loongson family machines use Hyper-Transport bus for inter-core
connection and device connection. The PCI bus is a subordinate
linked at HT1.

With LEFI firmware interface, We don't need fixup for PCI irq routing
(except providing a VBIOS of the integrated GPU).

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Hongliang Tao <taohl@lemote.com>
Signed-off-by: Hua Yan <yanh@lemote.com>
Tested-by: Alex Smith <alex.smith@imgtec.com>
Reviewed-by: Alex Smith <alex.smith@imgtec.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/6633
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Huacai Chen 1a08f1524d MIPS: Loongson: Add UEFI-like firmware interface (LEFI) support
The new UEFI-like firmware interface (LEFI, i.e. Loongson Unified
Firmware Interface) has 3 advantages:

1, Firmware export a physical memory map which is similar to X86's
   E820 map, so prom_init_memory() will be more elegant that #ifdef
   clauses can be removed.
2, Firmware export a pci irq routing table, we no longer need pci
   irq routing fixup in kernel's code.
3, Firmware has a built-in vga bios, and its address is exported,
   the linux kernel no longer need an embedded blob.

With the LEFI interface, Loongson-3A/2G and all their successors can use
a unified kernel. All Loongson-based machines support this new interface
except 2E/2F series.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Hongliang Tao <taohl@lemote.com>
Signed-off-by: Hua Yan <yanh@lemote.com>
Tested-by: Alex Smith <alex.smith@imgtec.com>
Reviewed-by: Alex Smith <alex.smith@imgtec.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/6632
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Huacai Chen 5f6d693ebb MIPS: Loongson 3: Add Lemote-3A machtypes definition
Add four Loongson-3 based machine types:
MACH_LEMOTE_A1004/MACH_LEMOTE_A1201 are laptops;
MACH_LEMOTE_A1101 is mini-itx;
MACH_LEMOTE_A1205 is all-in-one machine.

The most significant differrent between A1004/A1201 and A1101/A1205 is
the laptops have EC but others don't.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Hongliang Tao <taohl@lemote.com>
Signed-off-by: Hua Yan <yanh@lemote.com>
Tested-by: Alex Smith <alex.smith@imgtec.com>
Reviewed-by: Alex Smith <alex.smith@imgtec.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/6631
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Huacai Chen c579d310b9 MIPS: Loongson: Add basic Loongson-3 CPU support
Basic Loongson-3 CPU support include CPU probing and TLB/cache
initializing.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Hongliang Tao <taohl@lemote.com>
Signed-off-by: Hua Yan <yanh@lemote.com>
Tested-by: Alex Smith <alex.smith@imgtec.com>
Reviewed-by: Alex Smith <alex.smith@imgtec.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/6630
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Huacai Chen 152ebb44ef MIPS: Loongson: Add basic Loongson-3 definition
Loongson-3 is a multi-core MIPS family CPU, it support MIPS64R2 fully.
Loongson-3 has the same IMP field (0x6300) as Loongson-2.

Loongson-3 has a hardware-maintained cache, system software doesn't
need to maintain coherency.

Loongson-3A is the first revision of Loongson-3, and it is the quad-
core version of Loongson-2G. Loongson-3A has a simplified version named
Loongson-2Gq, the main difference between Loongson-3A/2Gq is 3A has two
HyperTransport controller but 2Gq has only one. HT0 is used for cross-
chip interconnection and HT1 is used to link PCI bus. Therefore, 2Gq
cannot support NUMA but 3A can. For software, Loongson-2Gq is simply
identified as Loongson-3A.

Exsisting Loongson family CPUs:
Loongson-1: Loongson-1A, Loongson-1B, they are 32-bit MIPS CPUs.
Loongson-2: Loongson-2E, Loongson-2F, Loongson-2G, they are 64-bit
            single-core MIPS CPUs.
Loongson-3: Loongson-3A(including so-called Loongson-2Gq), they are
            64-bit multi-core MIPS CPUs.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Hongliang Tao <taohl@lemote.com>
Signed-off-by: Hua Yan <yanh@lemote.com>
Tested-by: Alex Smith <alex.smith@imgtec.com>
Reviewed-by: Alex Smith <alex.smith@imgtec.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/6629/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Ralf Baechle d6d3c9afaa MIPS: MT: proc: Add support for printing VPE and TC ids
And there are more CPUs or configurations that want to provide special
per-CPU information in /proc/cpuinfo.  So I think there needs to be a
hook mechanism, such as a notifier.

This is a first cut only; I need to think about what sort of looking
the notifier needs to have.  But I'd appreciate testing on MT hardware!

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6066/
2014-03-31 18:17:12 +02:00
Rafał Miłecki a2bec07844 MIPS: BCM47XX: Add new file for device specific workarounds
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Patchwork: https://patchwork.linux-mips.org/patch/6627/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Paul Burton dab75dd956 MIPS: Simplify ptrace_getfpregs FPU IR retrieval
All architecturally defined bits in the FPU implementation register
are read only & unchanging. It contains some implementation-defined
bits but the architecture manual states "This bits are explicitly not
intended to be used for mode control functions" which seems to provide
justification for viewing the register as a whole as unchanging. This
being the case we can simply re-use the value we read at boot rather
than having to re-read it later, and avoid the complexity which that
read entails.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6147/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Paul Burton 3351047f01 MIPS: Simplify PTRACE_PEEKUSR for FPC_EIR
All architecturally defined bits in the FPU implementation register
are read only & unchanging. It contains some implementation-defined
bits but the architecture manual states "This bits are explicitly not
intended to be used for mode control functions" which seems to provide
justification for viewing the register as a whole as unchanging. This
being the case we can simply re-use the value we read at boot rather
than having to re-read it later, and avoid the complexity which that
read entails.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Qais Yousef <qais.yousef@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6144/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Wu Zhangjin d7b12056bc MIPS: Use current_cpu_type() instead of c->cputype
If current_cpu_type() is pre-defined in cpu-feature-overrides.h, This
may save about 10k for the compressed kernel image(vmlinuz).

Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1901/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Richard Weinberger e009189ed9 MIPS: Octeon: Remove SYS_HAS_DMA_OPS
The symbol is an orphan, get rid of it.

Signed-off-by: Richard Weinberger <richard@nod.at>
Cc: linux-mips@linux-mips.org (open list:MIPS)
Cc: linux-kernel@vger.kernel.org (open list)
Patchwork: https://patchwork.linux-mips.org/patch/6523/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Paul Gortmaker f698a3b58c MIPS: SEAD3: Don't use module_init in non-modular sead3-mtd.c code
The sead3-mtd.o is built for obj-y -- and hence this code is always
present.  It will never be modular, so using module_init as an alias
for __initcall can be somewhat misleading.

Fix this up now, so that we can relocate module_init from
init.h into module.h in the future.  If we don't do this, we'd
have to add module.h to obviously non-modular code, and that
would be a worse thing.

Note that direct use of __initcall is discouraged, vs. one
of the priority categorized subgroups.  As __initcall gets
mapped onto device_initcall, our use of device_initcall
directly in this change means that the runtime impact is
zero -- it will remain at level 6 in initcall ordering.

We also fix a missing semicolon, which this change uncovers.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Reported-by: kbuild test robot <fengguang.wu@intel.com>
Cc: linux-mips@linux-mips.org
Cc: fengguang.wu@intel.com
Patchwork: https://patchwork.linux-mips.org/patch/6412/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Ralf Baechle a9dde2886b MIPS: Malta: Fix CONFIG_BLK_DEV_IDE vestiges.
Don't depend on CONFIG_IDE to make this more robust.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Huacai Chen 2685919819 MIPS: Loongson: Rename PRID_IMP_LOONGSON1 and PRID_IMP_LOONGSON2
Loongson-1 is a 32-bit MIPS CPU and Loongson-2/3 are 64-bit MIPS CPUs,
and both Loongson-2/3 has the same PRID IMP filed (0x6300). As a
result, renaming PRID_IMP_LOONGSON1 and PRID_IMP_LOONGSON2 to
PRID_IMP_LOONGSON_32 and PRID_IMP_LOONGSON_64 will make more sense.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Tested-by: Alex Smith <alex.smith@imgtec.com>
Reviewed-by: Alex Smith <alex.smith@imgtec.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/6552/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Paul Bolle 9b3384bedf MIPS: No need to select ARCH_SUPPORTS_MSI
Commit c24a8a7a99 ("MIPS: Netlogic: Add MSI support for XLP") added
"select ARCH_SUPPORTS_MSI". But the Kconfig symbol ARCH_SUPPORTS_MSI was
already removed in v3.12, so that select is a nop. Drop it.

Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Cc: Jayachandran C <jchandra@broadcom.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/6521/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Deng-Cheng Zhu 9597e43245 MIPS: perf: Add interAptiv support
Choose event/cache maps and handle raw event mapping for interAptiv. Update
code comments.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Reviewed-by: Markos Chandras <Markos.Chandras@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Steven.Hill@imgtec.com
Patchwork: https://patchwork.linux-mips.org/patch/6528/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Deng-Cheng Zhu c52068bd2f MIPS: perf: Add proAptiv support
Choose event/cache maps and handle raw event mapping for proAptiv. Update
code comments.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Reviewed-by: Markos Chandras <Markos.Chandras@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Steven.Hill@imgtec.com
Patchwork: https://patchwork.linux-mips.org/patch/6527/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Deng-Cheng Zhu 6b0b84295c MIPS: perf: Rename 74K event/cache maps in preparation for Aptiv support
74K/proAptiv share the same event/cache maps. So it's better to change the
names of the existing mipsxx74Kcore_[event|cache]_map.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Reviewed-by: Markos Chandras <Markos.Chandras@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Steven.Hill@imgtec.com
Patchwork: https://patchwork.linux-mips.org/patch/6526/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 18:17:12 +02:00
Vineet Gupta 6041003a8f ARC: Remove unused DT template file
Commit abe11ddea1 "Enabling DeviceTree for Angel4 board" made
angel4.dts as default leaving the orphan skeleton file behind.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-03-31 19:20:35 +05:30
Geert Uytterhoeven 50be9eba83 m68k: Update defconfigs for v3.14-rc1
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2014-03-31 15:07:24 +02:00
Jeff Layton 5d50ffd7c3 locks: add new fcntl cmd values for handling file private locks
Due to some unfortunate history, POSIX locks have very strange and
unhelpful semantics. The thing that usually catches people by surprise
is that they are dropped whenever the process closes any file descriptor
associated with the inode.

This is extremely problematic for people developing file servers that
need to implement byte-range locks. Developers often need a "lock
management" facility to ensure that file descriptors are not closed
until all of the locks associated with the inode are finished.

Additionally, "classic" POSIX locks are owned by the process. Locks
taken between threads within the same process won't conflict with one
another, which renders them useless for synchronization between threads.

This patchset adds a new type of lock that attempts to address these
issues. These locks conflict with classic POSIX read/write locks, but
have semantics that are more like BSD locks with respect to inheritance
and behavior on close.

This is implemented primarily by changing how fl_owner field is set for
these locks. Instead of having them owned by the files_struct of the
process, they are instead owned by the filp on which they were acquired.
Thus, they are inherited across fork() and are only released when the
last reference to a filp is put.

These new semantics prevent them from being merged with classic POSIX
locks, even if they are acquired by the same process. These locks will
also conflict with classic POSIX locks even if they are acquired by
the same process or on the same file descriptor.

The new locks are managed using a new set of cmd values to the fcntl()
syscall. The initial implementation of this converts these values to
"classic" cmd values at a fairly high level, and the details are not
exposed to the underlying filesystem. We may eventually want to push
this handing out to the lower filesystem code but for now I don't
see any need for it.

Also, note that with this implementation the new cmd values are only
available via fcntl64() on 32-bit arches. There's little need to
add support for legacy apps on a new interface like this.

Signed-off-by: Jeff Layton <jlayton@redhat.com>
2014-03-31 08:24:43 -04:00
Hans de Goede 536a44d427 ARM: sun7i/sun6i: dts: Fix IRQ number for sun6i NMI controller
The IRQ line used in sun6i-a31.dtsi for the NMI controller is wrong.
This causes a IRQ storm since the NMI controller is repeatedly fired.
This patch fixes this problem assigning the correct IRQ number to the
NMI controller.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Carlo Caione <carlo@caione.org>
Cc: maxime.ripard@free-electrons.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-sunxi@googlegroups.com
Link: http://lkml.kernel.org/r/1395939759-11135-2-git-send-email-carlo@caione.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-31 11:12:57 +02:00
Huacai Chen c14af233fb MIPS: Hibernate: Flush TLB entries in swsusp_arch_resume()
The original MIPS hibernate code flushes cache and TLB entries in
swsusp_arch_resume(). But they are removed in Commit 44eeab6741
(MIPS: Hibernation: Remove SMP TLB and cacheflushing code.). A cross-
CPU flush is surely unnecessary because all but the local CPU have
already been disabled. But a local flush (at least the TLB flush) is
needed. When we do hibernation on Loongson-3 with an E1000E NIC, it is
very easy to produce a kernel panic (kernel page fault, or unaligned
access). The root cause is E1000E driver use vzalloc_node() to allocate
pages, the stale TLB entries of the booting kernel will be misused by
the resumed target kernel.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/6643/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 10:16:53 +02:00
Manuel Lauss 61d3edb862 MIPS: Alchemy: remove duplicate UART register offset definitions
The UART register names are identical to the ones in uapi/linux/serial_reg.h,
which causes build failures in various drivers when they indirectly pull in
the au1000.h header, for example via gpio.h:

In file included from arch/mips/include/asm/mach-au1x00/gpio.h:13:0,
                 from arch/mips/include/asm/gpio.h:4,
                 from include/linux/gpio.h:48,
                 from include/linux/ssb/ssb.h:9,
                 from drivers/ssb/driver_mipscore.c:11:
arch/mips/include/asm/mach-au1x00/au1000.h:1171:0: note: this is the location of the previous definition
 #define UART_LSR 0x1C /* Line Status Register */

Get rid of the altogether, nothing in the core Alchemy code depends
on them any more.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/6664/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 10:16:53 +02:00
Ralf Baechle e60865572f MIPS: Fix build error due to multiple prom_putchar() definitions.
This can happen if both the generic 8250 and another early console
driver are enable.  Fixed by using an auxilliary kconfig symbol to
restrict that choice.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31 10:16:52 +02:00
Grant Likely d88cf7d7b4 Merge remote-tracking branch 'robh/for-next' into devicetree/next 2014-03-31 08:10:55 +01:00
Chen Gang 2601566d01 arch/avr32/mm/cache.c: export symbol flush_icache_range() for module using
Need export symbol flush_icache_range() to modules, just like another
platforms have done, or can not pass compiling.

The related error (with allmodconfig under avr32):

  ERROR: "flush_icache_range" [drivers/misc/lkdtm.ko] undefined!
  make[1]: *** [__modpost] Error 1
  make: *** [modules] Error 2

Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Acked-by: Hans-Christian Egtvedt <egtvedt@samfundet.no>
2014-03-31 08:41:52 +02:00
Wolfram Sang 8acc8722d3 avr32: remove cpu_data macro to fix compiles
Having cpu_data as a parameterless macro can easily cause build failures
because it can be a variable name like in linux/pm_domain.h [1]. So,
remove the macro and convert its only user. Because this architecture
cannot do SMP, remove the whole SMP block, too. Only compile tested due
to no hardware.

Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Acked-by: Hans-Christian Egtvedt <egtvedt@samfundet.no>

[1] https://lists.01.org/pipermail/kbuild-all/2014-February/003252.html
2014-03-31 08:41:36 +02:00
Daniel Borkmann f8bbbfc3b9 net: filter: add jited flag to indicate jit compiled filters
This patch adds a jited flag into sk_filter struct in order to indicate
whether a filter is currently jited or not. The size of sk_filter is
not being expanded as the 32 bit 'len' member allows upper bits to be
reused since a filter can currently only grow as large as BPF_MAXINSNS.

Therefore, there's enough room also for other in future needed flags to
reuse 'len' field if necessary. The jited flag also allows for having
alternative interpreter functions running as currently, we can only
detect jit compiled filters by testing fp->bpf_func to not equal the
address of sk_run_filter().

Joint work with Alexei Starovoitov.

Signed-off-by: Alexei Starovoitov <ast@plumgrid.com>
Signed-off-by: Daniel Borkmann <dborkman@redhat.com>
Cc: Pablo Neira Ayuso <pablo@netfilter.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-03-31 00:45:08 -04:00
Andy Lutomirski 37c975545e x86, vdso: Fix the symbol versions on the 32-bit vDSO
The new symbols provide the same API as the 64-bit variants, so they
should have the same symbol version name.  This can't break
userspace, since these symbols are new for 32-bit Linux.

Signed-off-by: Andy Lutomirski <luto@amacapital.net>
Cc: Stefani Seibold <stefani@seibold.net>
Link: http://lkml.kernel.org/r/0a869bce03d25619565b1eee7d69a4fd15fd203a.1396124118.git.luto@amacapital.net
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2014-03-30 10:08:38 -07:00
David S. Miller 64c27237a0 Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Conflicts:
	drivers/net/ethernet/marvell/mvneta.c

The mvneta.c conflict is a case of overlapping changes,
a conversion to devm_ioremap_resource() vs. a conversion
to netdev_alloc_pcpu_stats.

Signed-off-by: David S. Miller <davem@davemloft.net>
2014-03-29 18:48:54 -04:00
Paolo Bonzini 7227fc0666 Merge branch 'kvm-ppchv-next' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc into kvm-next 2014-03-29 15:44:05 +01:00
Barry Song 2e041c9462 dmaengine: sirf: enable generic dt binding for dma channels
move to support of_dma_request_slave_channel() and dma_request_slave_channel.
we add a xlate() to let dma clients be able to find right dma_chan by generic
"dmas" properties in dts.

Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-03-29 19:20:13 +05:30
Heiko Carstens 1e4ec6217d s390/compat: add copyright statement
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
2014-03-29 10:51:28 +01:00
Paul Mackerras 72cde5a88d KVM: PPC: Book3S HV: Save/restore host PMU registers that are new in POWER8
Currently we save the host PMU configuration, counter values, etc.,
when entering a guest, and restore it on return from the guest.
(We have to do this because the guest has control of the PMU while
it is executing.)  However, we missed saving/restoring the SIAR and
SDAR registers, as well as the registers which are new on POWER8,
namely SIER and MMCR2.

This adds code to save the values of these registers when entering
the guest and restore them on exit.  This also works around the bug
in POWER8 where setting PMAE with a counter already negative doesn't
generate an interrupt.

Signed-off-by: Paul Mackerras <paulus@samba.org>
Acked-by: Scott Wood <scottwood@freescale.com>
2014-03-29 19:58:52 +11:00
Paul Mackerras c5fb80d3b2 KVM: PPC: Book3S HV: Fix decrementer timeouts with non-zero TB offset
Commit c7699822bc21 ("KVM: PPC: Book3S HV: Make physical thread 0 do
the MMU switching") reordered the guest entry/exit code so that most
of the guest register save/restore code happened in guest MMU context.
A side effect of that is that the timebase still contains the guest
timebase value at the point where we compute and use vcpu->arch.dec_expires,
and therefore that is now a guest timebase value rather than a host
timebase value.  That in turn means that the timeouts computed in
kvmppc_set_timer() are wrong if the timebase offset for the guest is
non-zero.  The consequence of that is things such as "sleep 1" in a
guest after migration may sleep for much longer than they should.

This fixes the problem by converting between guest and host timebase
values as necessary, by adding or subtracting the timebase offset.
This also fixes an incorrect comment.

Signed-off-by: Paul Mackerras <paulus@samba.org>
Acked-by: Scott Wood <scottwood@freescale.com>
2014-03-29 19:58:39 +11:00
Paul Mackerras 797f9c07eb KVM: PPC: Book3S HV: Don't use kvm_memslots() in real mode
With HV KVM, some high-frequency hypercalls such as H_ENTER are handled
in real mode, and need to access the memslots array for the guest.
Accessing the memslots array is safe, because we hold the SRCU read
lock for the whole time that a guest vcpu is running.  However, the
checks that kvm_memslots() does when lockdep is enabled are potentially
unsafe in real mode, when only the linear mapping is available.
Furthermore, kvm_memslots() can be called from a secondary CPU thread,
which is an offline CPU from the point of view of the host kernel,
and is not running the task which holds the SRCU read lock.

To avoid false positives in the checks in kvm_memslots(), and to avoid
possible side effects from doing the checks in real mode, this replaces
kvm_memslots() with kvm_memslots_raw() in all the places that execute
in real mode.  kvm_memslots_raw() is a new function that is like
kvm_memslots() but uses rcu_dereference_raw_notrace() instead of
kvm_dereference_check().

Signed-off-by: Paul Mackerras <paulus@samba.org>
Acked-by: Scott Wood <scottwood@freescale.com>
2014-03-29 19:58:35 +11:00
Paul Mackerras 739e2425fe KVM: PPC: Book3S HV: Return ENODEV error rather than EIO
If an attempt is made to load the kvm-hv module on a machine which
doesn't have hypervisor mode available, return an ENODEV error,
which is the conventional thing to return to indicate that this
module is not applicable to the hardware of the current machine,
rather than EIO, which causes a warning to be printed.

Signed-off-by: Paul Mackerras <paulus@samba.org>
Acked-by: Scott Wood <scottwood@freescale.com>
2014-03-29 19:58:29 +11:00
Paul Mackerras b24f36f33e KVM: PPC: Book3S: Trim top 4 bits of physical address in RTAS code
The in-kernel emulation of RTAS functions needs to read the argument
buffer from guest memory in order to find out what function is being
requested.  The guest supplies the guest physical address of the buffer,
and on a real system the code that reads that buffer would run in guest
real mode.  In guest real mode, the processor ignores the top 4 bits
of the address specified in load and store instructions.  In order to
emulate that behaviour correctly, we need to mask off those bits
before calling kvm_read_guest() or kvm_write_guest().  This adds that
masking.

Signed-off-by: Paul Mackerras <paulus@samba.org>
Acked-by: Scott Wood <scottwood@freescale.com>
2014-03-29 19:58:23 +11:00
Michael Neuling a7d80d01c6 KVM: PPC: Book3S HV: Add get/set_one_reg for new TM state
This adds code to get/set_one_reg to read and write the new transactional
memory (TM) state.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Acked-by: Scott Wood <scottwood@freescale.com>
2014-03-29 19:58:17 +11:00
Michael Neuling e4e3812150 KVM: PPC: Book3S HV: Add transactional memory support
This adds saving of the transactional memory (TM) checkpointed state
on guest entry and exit.  We only do this if we see that the guest has
an active transaction.

It also adds emulation of the TM state changes when delivering IRQs
into the guest.  According to the architecture, if we are
transactional when an IRQ occurs, the TM state is changed to
suspended, otherwise it's left unchanged.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Acked-by: Scott Wood <scottwood@freescale.com>
2014-03-29 19:58:02 +11:00
Arnd Bergmann 9e0c42ea3d Exynos cleanup for v3.15
- reorganize code for
 - add support reserve memory for mfc-v7
 - consolidate exynos4 and exynos5 machine codes
 - add generic compatible strings for exynos4 and exynos5
 - update DT with generic compatible strings
 - move clk related dt-binding header file in dt-bindings/clock
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Merge tag 'exynos-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup3

Merge "Exynos cleanup for v3.15" from Kukjin Kim:

- reorganize code for
- add support reserve memory for mfc-v7
- consolidate exynos4 and exynos5 machine codes
- add generic compatible strings for exynos4 and exynos5
- update DT with generic compatible strings
- move clk related dt-binding header file in dt-bindings/clock

* tag 'exynos-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  dt-bindings: clock: Move exynos-audss-clk.h to dt-bindings/clock
  ARM: dts: Update Exynos DT files with generic compatible strings
  ARM: EXYNOS: Add generic compatible strings
  ARM: EXYNOS: Consolidate exynos4 and exynos5 machine files
  ARM: EXYNOS: Consolidate CPU init code
  ARM: SAMSUNG: Introduce generic Exynos4 and 5 helpers
  ARM: EXYNOS: Add support to reserve memory for MFC-v7
  ARM: SAMSUNG: Reorganize calls to reserve memory for MFC

Conflicts:
	arch/arm/mach-exynos/exynos.c

Signed-off-by; Arnd Bergmann <arnd@arndb.de>
2014-03-29 02:03:39 +01:00
Arnd Bergmann 2c793fa349 Samsung PM related 2nd updates for v3.15
From Tomasz Figa <t.figa@samsung.com>:
 Current Samsung PM code is heavily unprepared for multiplatform
 systems. The design implies accessing functions and global
 variables defined in particular mach- subdirectory from common
 code in plat-, which is not allowed when building ARCH_MULTIPLATFORM.
 In addition there is a lot of forced code unification, which makes
 common function handle any possible quirks of all supported SoCs.
 In the end this design turned out to not work too well, ending with
 a lot of empty functions exported from mach-, just because code in
 common pm.c calls them. Moreover, recent trend of moving lower level
 suspend/resume code to proper drivers, like pinctrl or clk, made a
 lot of code there redundant, especially on DT-only platforms like
 Exynos.
 
 Note that this branch is based on previous tags/samsung-pm-1 and merge
 tags/samsung-cleanup-2 because of fix build error from recent changes
 of <linux/serial_s3c.h>
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Merge tag 'samsung-pm-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup3

Merge "Samsung PM related 2nd updates for v3.15" from Kukjin Kim:

From Tomasz Figa <t.figa@samsung.com>:
Current Samsung PM code is heavily unprepared for multiplatform
systems. The design implies accessing functions and global
variables defined in particular mach- subdirectory from common
code in plat-, which is not allowed when building ARCH_MULTIPLATFORM.
In addition there is a lot of forced code unification, which makes
common function handle any possible quirks of all supported SoCs.
In the end this design turned out to not work too well, ending with
a lot of empty functions exported from mach-, just because code in
common pm.c calls them. Moreover, recent trend of moving lower level
suspend/resume code to proper drivers, like pinctrl or clk, made a
lot of code there redundant, especially on DT-only platforms like
Exynos.

Note that this branch is based on previous tags/samsung-pm-1 and merge
tags/samsung-cleanup-2 because of fix build error from recent changes
of <linux/serial_s3c.h>

* tag 'samsung-pm-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: EXYNOS: Fix compilation error in cpuidle.c
  ARM: S5P64X0: Explicitly include linux/serial_s3c.h in mach/pm-core.h
  ARM: S3C64XX: Fix build for implicit serial_s3c.h inclusion
  serial: s3c: Fix build of header without serial_core.h preinclusion
  ARM: EXYNOS: Allow wake-up using GIC interrupts
  ARM: EXYNOS: Stop using legacy Samsung PM code
  ARM: EXYNOS: Remove PM initcalls and useless indirection
  ARM: EXYNOS: Fix abuse of CONFIG_PM
  ARM: SAMSUNG: Move s3c_pm_check_* prototypes to plat/pm-common.h
  ARM: SAMSUNG: Move common save/restore helpers to separate file
  ARM: SAMSUNG: Move Samsung PM debug code into separate file
  ARM: SAMSUNG: Consolidate PM debug functions
  ARM: SAMSUNG: Use debug_ll_addr() to get UART base address
  ARM: SAMSUNG: Save UART DIVSLOT register based on SoC type
  ARM: SAMSUNG: Add soc_is_s3c2410() helper
  ARM: EXYNOS: Do not resume l2x0 if not enabled before suspend

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-29 02:02:56 +01:00
Arnd Bergmann c441ab93d2 Samsung 3rd DT updates for v3.15
- Arndale Octa board updates:
   LDO3 and LDO23 enabled for soft-reset
   LDO9 enabled for USB operation
   MDMA1 disabled to avoid imprecise external abort
 
 Note that this is based on previous tags/samsung-dt-2
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Merge tag 'samsung-dt-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup3

Merge "Samsung 3rd DT updates for v3.15" from Kukjin Kim:

- Arndale Octa board updates:
  LDO3 and LDO23 enabled for soft-reset
  LDO9 enabled for USB operation
  MDMA1 disabled to avoid imprecise external abort

Note that this is based on previous tags/samsung-dt-2

* tag 'samsung-dt-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: dts: Keep some essential LDOs enabled for arndale-octa board
  ARM: dts: Disable MDMA1 node for arndale-octa board

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-29 02:02:27 +01:00
Arnd Bergmann efa25ffdd6 Samsung 3rd cleanup for v3.15
- Remove <mach/hardware.h> in mach-exynos
 - Remove invalid code from <mach/hardware.h> in mach-s3c24xx
 
 Note that this is based on previous tags/samsung-cleanup-2
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Merge tag 'samsung-cleanup-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup3

Merge "Samsung 3rd cleanup for v3.15" from Kukjin Kim:

- Remove <mach/hardware.h> in mach-exynos
- Remove invalid code from <mach/hardware.h> in mach-s3c24xx

Note that this is based on previous tags/samsung-cleanup-2

* tag 'samsung-cleanup-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: EXYNOS: Remove hardware.h file
  ARM: SAMSUNG: Remove hardware.h inclusion
  ARM: S3C24XX: Remove invalid code from hardware.h

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-29 02:01:57 +01:00
Arnd Bergmann cd5f48a7ac Samsung 2nd DT updates for v3.15
- add DT entry for AHCI SATA and SATA PHY with using generic
   PHY framework for exynos5250 and arndale, smdk5250 boards.
 - add SSS DT node for exynos5420 and exynos5250
 - remove leftover spi0 node for smdk5250 board
 - add ADC and thermistor nodes for exynos4412-trats2 board
 - move common irq-combiner node for exynos4x12 from exynos4212
   and exynos4412
 - add ADC, PMU and GPS_ALIVE power domain nodes for exynos4x12
 
 Note that based on previous tags/samsung-dt and tags/exynos-clk
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Merge tag 'samsung-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup3

Merge "Samsung 2nd DT updates for v3.15" from Kukjin Kim:

- add DT entry for AHCI SATA and SATA PHY with using generic
  PHY framework for exynos5250 and arndale, smdk5250 boards.
- add SSS DT node for exynos5420 and exynos5250
- remove leftover spi0 node for smdk5250 board
- add ADC and thermistor nodes for exynos4412-trats2 board
- move common irq-combiner node for exynos4x12 from exynos4212
  and exynos4412
- add ADC, PMU and GPS_ALIVE power domain nodes for exynos4x12

Note that based on previous tags/samsung-dt and tags/exynos-clk

* tag 'samsung-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: dts: enable ahci sata and sata phy for exynos5250
  ARM: dts: add dt node for sss module for exynos5250/5420
  ARM: dts: Remove leftover spi0 node for smdk5250
  ARM: dts: Add ADC and themistor nodes for exynos4412-trats2
  ARM: dts: Move common dt data for interrupt combiner controller for exynos4x12
  ARM: dts: Add GPS_ALIVE power domain for exynos4x12
  ARM: dts: Add PMU dt data to support PMU for exynos4x12
  ARM: dts: Add ADC's dt data to read raw data for exynos4x12

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-29 01:59:22 +01:00
Arnd Bergmann 2b23e9a51d Samsung cleanup-2 for v3.15
- use generic uncompress.h and remove all custom
   uncompress.h in mach-s3c24xx, s3c64xx, s5p64x0,
   s5pc100, s5pv210 and plat-samsung directories.
 
 Note that based on previous tags/samsung-cleanup
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Merge tag 'samsung-cleanup-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup3

Merge "Samsung cleanup-2 for v3.15" from Kukjin Kim:

- use generic uncompress.h and remove all custom
  uncompress.h in mach-s3c24xx, s3c64xx, s5p64x0,
  s5pc100, s5pv210 and plat-samsung directories.

Note that based on previous tags/samsung-cleanup

* tag 'samsung-cleanup-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: SAMSUNG: remove all custom uncompress.h
  ARM: SAMSUNG: use generic uncompress.h

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-29 01:58:19 +01:00
Arnd Bergmann cf2afdc59d Merge branches 'samsung/cleanup', 'samsung/exynos-clk' and 'samsung/exynos-clk2' into next/cleanup3
These are dependencies for the following Samsung branches

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-29 01:51:51 +01:00
Arnd Bergmann f1d7d8c86b Samsung S2R PM updates for v3.15
From Tomasz Figa:
 This series reworks suspend/resume handling of Samsung clock drivers
 to cover more SoC specific aspects that are beyond simple register
 save and restore. The goal is to have all the suspend/resume code
 that touches the clock controller in single place, which is the clock
 driver.
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Merge tag 'samsung-pm-1' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers

Merge "Samsung S2R PM updates for v3.15" from Kukjin Kim:

From Tomasz Figa:
This series reworks suspend/resume handling of Samsung clock drivers
to cover more SoC specific aspects that are beyond simple register
save and restore. The goal is to have all the suspend/resume code
that touches the clock controller in single place, which is the clock
driver.

* tag 'samsung-pm-1' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: EXYNOS: Drop legacy Exynos4 clock suspend/resume code
  clk: samsung: exynos4: Add remaining suspend/resume handling
  clk: samsung: Drop old suspend/resume code
  clk: samsung: s3c64xx: Move suspend/resume handling to SoC driver
  clk: samsung: exynos5420: Move suspend/resume handling to SoC driver
  clk: samsung: exynos5250: Move suspend/resume handling to SoC driver
  clk: samsung: exynos4: Move suspend/resume handling to SoC driver
  clk: samsung: Provide common helpers for register save/restore
  clk: exynos4: Remove remnants of non-DT support

Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-29 01:47:15 +01:00
Dinh Nguyen 2755e18748 dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac.
This patch adds the dts bindings documenation for the Altera SOCFPGA glue
layer for the Synopsys STMMAC ethernet driver.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-29 01:11:46 +01:00
Kees Cook 4c332c3238 [IA64] Keep format strings from leaking into printk
The buffer being sent to printk has already had format strings
resolved. The string should not be reinterpreted again to avoid any
unintended format strings from leaking into printk.

Signed-off-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2014-03-28 15:49:04 -07:00
Artem Fetishev 825600c0f2 x86: fix boot on uniprocessor systems
On x86 uniprocessor systems topology_physical_package_id() returns -1
which causes rapl_cpu_prepare() to leave rapl_pmu variable uninitialized
which leads to GPF in rapl_pmu_init().

See arch/x86/kernel/cpu/perf_event_intel_rapl.c.

It turns out that physical_package_id and core_id can actually be
retreived for uniprocessor systems too.  Enabling them also fixes
rapl_pmu code.

Signed-off-by: Artem Fetishev <artem_fetishev@epam.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: <stable@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2014-03-28 13:56:58 -07:00
Chen, Gong 27f6c573e0 x86, CMCI: Add proper detection of end of CMCI storms
When CMCI storm persists for a long time(at least beyond predefined
threshold. It's 30 seconds for now), we can watch CMCI storm is
detected immediately after it subsides.

...
Dec 10 22:04:29 kernel: CMCI storm detected: switching to poll mode
Dec 10 22:04:59 kernel: CMCI storm subsided: switching to interrupt mode
Dec 10 22:04:59 kernel: CMCI storm detected: switching to poll mode
Dec 10 22:05:29 kernel: CMCI storm subsided: switching to interrupt mode
...

The problem is that our logic that determines that the storm has
ended is incorrect. We announce the end, re-enable interrupts and
realize that the storm is still going on, so we switch back to
polling mode. Rinse, repeat.

When a storm happens we disable signaling of errors via CMCI and begin
polling machine check banks instead. If we find any logged errors,
then we need to set a per-cpu flag so that our per-cpu tests that
check whether the storm is ongoing will see that errors are still
being logged independently of whether mce_notify_irq() says that the
error has been fully processed.

cmci_clear() is not the right tool to disable a bank. It disables the
interrupt for the bank as desired, but it also clears the bit for
this bank in "mce_banks_owned" so we will skip the bank when polling
(so we fail to see that the storm continues because we stop looking).
New cmci_storm_disable_banks() just disables the interrupt while
allowing polling to continue.

Reported-by: William Dauchy <wdauchy@gmail.com>
Signed-off-by: Chen, Gong <gong.chen@linux.intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2014-03-28 13:40:16 -07:00
Maxime Ripard 9233087dc4 ARM: sunxi: Select HAVE_ARM_ARCH_TIMER
In order for the architected timers support to be enabled in the kernel, this
option has to be enabled. Otherwise, the architected timers driver won't be
compiled in, and we will not get to use them.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
2014-03-27 14:26:27 -07:00
Jason Wang ca3ba2a2f4 x86, hyperv: Bypass the timer_irq_works() check
This patch bypass the timer_irq_works() check for hyperv guest since:

- It was guaranteed to work.
- timer_irq_works() may fail sometime due to the lpj calibration were inaccurate
  in a hyperv guest or a buggy host.

In the future, we should get the tsc frequency from hypervisor and use preset
lpj instead.

[ hpa: I would prefer to not defer things to "the future" in the future... ]

Cc: K. Y. Srinivasan <kys@microsoft.com>
Cc: Haiyang Zhang <haiyangz@microsoft.com>
Cc: <stable@vger.kernel.org>
Acked-by: K. Y. Srinivasan <kys@microsoft.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Link: http://lkml.kernel.org/r/1393558229-14755-1-git-send-email-jasowang@redhat.com
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2014-03-27 11:02:45 -07:00
Paolo Bonzini 920c837785 KVM: vmx: fix MPX detection
kvm_x86_ops is still NULL at this point.  Since kvm_init_msr_list
cannot fail, it is safe to initialize it before the call.

Fixes: 93c4adc7af
Reported-by: Fengguang Wu <fengguang.wu@intel.com>
Tested-by: Jet Chen <jet.chen@intel.com>
Cc: kvm@vger.kernel.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-03-27 13:06:51 +01:00
Arnd Bergmann 027f3f9696 ARM: cache-tauros2: remove ARMv6 code
When building a kernel with support for both ARMv6 and ARMv7 but
no MMU, the call from tauros2_internal_init to adjust_cr causes
a link error. While that could probably be resolved, we don't
actually support cache-tauros2 on ARMv6 any more. All PJ4 CPU
implementations support both ARMv6 and ARMv7 and we already assume
that we are using them only in ARMv7 mode.

Removing the ARMv6 code path reduces the code size and avoids
the linker error.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
2014-03-27 02:49:24 +01:00
Arnd Bergmann f8afae40a0 ARM: moxart: fix CPU selection
Moxart uses an FA526 CPU core, which is ARMv4 based, not ARMv4T.
Before moxart, we had no CONFIG_MULTI_V4 option, since no ARMv4 platform
was enabled for multiplatform. This now adds the missing option, which
will give us slightly more efficient code on pure moxart kernels,
because we can build a pure FA526 kernel now rather than a combined
FA526+ARM920T kernel that we used to.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-27 02:35:44 +01:00
Arnd Bergmann 32adc19d4b Merge tag 'zynq-cleanup-for-3.15-v2' of git://git.xilinx.com/linux-xlnx into next/cleanup2
Merge "arm: Xilinx Zynq cleanup patches for v3.15" from Michal Simek:

- Redesign SLCR initialization to enable
  driver developing which targets SLCR space

* tag 'zynq-cleanup-for-3.15-v2' of git://git.xilinx.com/linux-xlnx:
  ARM: zynq: Add waituart implementation
  ARM: zynq: Move of_clk_init from clock driver
  ARM: zynq: Introduce zynq_slcr_unlock()
  ARM: zynq: Add and use zynq_slcr_read/write() helper functions
  ARM: zynq: Make zynq_slcr_base static
  ARM: zynq: Map I/O memory on clkc init
  ARM: zynq: Hang iomapped slcr address on device_node
  ARM: zynq: Split slcr in two parts
  ARM: zynq: Move clock_init from slcr to common
  arm: dt: zynq: Add fclk-enable property to clkc node

[Arnd: remove SOC_BUS support from pull request]

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-27 02:19:41 +01:00
Arnd Bergmann a1b6b737de Includes a patch to enable appended
DTB support for DT booting on DA850
 boards with older bootloaders.
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Merge tag 'davinci-for-v3.15/soc-2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/soc

Merge "DaVinci SoC fixes for v3.15" from Sekhar Nori:

Includes a patch to enable appended
DTB support for DT booting on DA850
boards with older bootloaders.

* tag 'davinci-for-v3.15/soc-2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
  ARM: davinci: fix DT booting with default defconfig

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-27 02:06:36 +01:00
Lee Jones ab3607dbb8 ARM: STi: stih41x: Add support for the FSM Serial Flash Controller
Here we add the necessary device nodes required for successful device
probing and Pinctrl setup for the FSM when booting on an STiH415 (Orly1)
or STiH416 (Orly2) based b2020 development board.

Acked-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Acked-by Angus Clark <angus.clark@st.com>
Acked-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-27 02:01:25 +01:00
Lee Jones 77f8d9b7e6 ARM: STi: stih416: Add support for the FSM Serial Flash Controller
Here we add the necessary device nodes required for successful device
probing and Pinctrl setup for the FSM when booting on an STiH416 (Orly2).

Acked-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Acked-by Angus Clark <angus.clark@st.com>
Acked-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-27 02:01:05 +01:00
Arnd Bergmann 4de6732f88 Keystone DTS fixes for 3.15
- Few fixes found during NAND ubifs testing
 - Fix to build all dtbs together with dtbs
 - Last patch is follow up comment from previous pull request
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Merge tag 'keystone-dts-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into next/dt

Merge "Keystone DTS fixes for 3.15" from Santosh Shilimkar:

- Few fixes found during NAND ubifs testing
- Fix to build all dtbs together with dtbs
- Last patch is follow up comment from previous pull request

* tag 'keystone-dts-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone:
  ARM: dts: keystone: use common "ti,keystone" compatible instead of -evm
  ARM: dts: k2hk-evm: set ubifs partition size for 512M NAND
  ARM: dts: Build all keystone dt blobs
  ARM: dts: keystone: Fix control register range for clktsip
  ARM: dts: keystone: Fix domain register range for clkfftc1

Conflicts:
	arch/arm/boot/dts/Makefile

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-27 01:54:39 +01:00
Arnd Bergmann b80a6373d6 Revert "dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac."
This reverts commit 7e0b4cd062.

The binding changes need to be done differently as well, let's
take them through netdev, and merge the dts changes in a new
patch here.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-27 01:26:00 +01:00
Alexandre Courbot 077492acce ARM: enable fhandle in multi_v7_defconfig
CONFIG_FHANDLE is required by systemd >= 210 to spawn a serial TTY.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-26 23:20:03 +01:00
Alexandre Courbot 38c5cbd78e ARM: tegra: enable fhandle in tegra_defconfig
CONFIG_FHANDLE is required by systemd >= 210 to spawn a serial TTY.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-26 23:19:23 +01:00
Stephen Warren 0c86f089e6 ARM: update multi_v7_defconfig for Tegra
This patch adds the same options to multi_v7_defconfig as were added to
tegra_defconfig in commit d1c912c100 "ARM: tegra: defconfig updates".
(CONFIG_POWER_RESET_AS3722 is already enabled here.)

Suggested-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-26 23:17:34 +01:00
Stephen Warren bf5fd5bf0a ARM: tegra: fix board DT pinmux setup
Neither Tegra114 nor Tegra124 allow "low power mode" to be configured
on SDIO1 or SDIO3 drive groups. Remove the attempt to configure that
option from the Dalmore and Venice2 DTs.

The Venice2 DT contained duplicate configurations for most sdmmc1_*
pins. Remove the duplicate pins from one of the nodes, and fix the
configuration since the remaining clk pin is output-only.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-26 23:13:16 +01:00
Alexander Shiyan 27addb96db ARM: nspire: Fix compiler warning
CC      arch/arm/mach-nspire/nspire.o
arch/arm/mach-nspire/nspire.c:79:2: warning: initialization from incompatible pointer type [enabled by default]
arch/arm/mach-nspire/nspire.c:79:2: warning: (near initialization for '__mach_desc_NSPIRE.restart') [enabled by default]

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-26 23:12:04 +01:00
Jingoo Han 823cf3cdd7 MIPS: JZ4740: Don't select HAVE_PWM
The HAVE_PWM symbol is only for legacy platforms that provide the PWM
API without using the generic framework. The jz4740 platform uses the
generic PWM framework, after the commit "f6b8a57 pwm: Add Ingenic
JZ4740 support".

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Lars-Peter Clausen <lars@metafoo.de>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6525/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:23 +01:00
Paul Gortmaker d9c0390a28 MIPS: Restore init.h usage to arch/mips/ar7/time.c
Commit 0046be10e0c502705fc74d91408eba13a73bc201 ("mips: delete
non-required instances of include <linux/init.h>") inadvertently
removed an include that was actually correct.  Restore it.

Note that it gets init.h implicitly anyway, so this is largely a
cosmetic fixup; no build regressions were caused by this.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6416/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:23 +01:00
Cody P Schafer 0dae62edfd MIPS: BCM47XX: Add Belkin F7Dxxxx board detection
Add a few Belkin F7Dxxxx entries, with F7D4401 sourced from online
documentation and the "F7D7302" being observed. F7D3301, F7D3302, and
F7D4302 are reasonable guesses which are unlikely to cause
mis-detection.

Signed-off-by: Cody P Schafer <devel@codyps.com>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Cc: linux-mips@linux-mips.org
Cc: zajec5@gmail.com
Cc: Cody P Schafer <devel@codyps.com>
Patchwork: https://patchwork.linux-mips.org/patch/6594/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:23 +01:00
Hauke Mehrtens d508eb79ab MIPS: BCM47XX: Add detection and GPIO config for Siemens SE505v2
This adds board detection for the Siemens SE505v2 and the led gpio
configuration. This board does not have any buttons.
This is based on OpenWrt broadcom-diag and Manuel Munz's nvram dump.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Cc: linux-mips@linux-mips.org
Cc: zajec5@gmail.com
Patchwork: https://patchwork.linux-mips.org/patch/6593/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:23 +01:00
Hauke Mehrtens 96c10de32f MIPS: BCM47XX: Add button and led configuration for some Linksys devices
This adds led and button GPIO configuration for Linksys wrt54g3gv2,
wrt54gsv1 and wrtsl54gs. This is based on OpenWrt broadcom-diag code.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Cc: linux-mips@linux-mips.org
Cc: zajec5@gmail.com
Patchwork: https://patchwork.linux-mips.org/patch/6592/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:23 +01:00
Hauke Mehrtens 848eeb66c7 MIPS: BCM47XX: Detect some more Linksys devices
The Linksys WRT54G/GS/GL family uses the same boardtype numbers, and
the same gpio configuration. The boardtype numbers are changing with
the hardware versions, but these hardware numbers are different or each
model.
Detect them all as one device, this also worked in OpenWrt.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Cc: linux-mips@linux-mips.org
Cc: zajec5@gmail.com
Patchwork: https://patchwork.linux-mips.org/patch/6591/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:22 +01:00
Leonid Yegoshin 9943ed921b MIPS: cpu-probe: Add support for probing M5150 cores
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6597/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:22 +01:00
Leonid Yegoshin f36c4720fc MIPS: Add support for the M5150 processor
The M5150 core is a 32-bit MIPS RISC which implements the
MIPS Architecture Release-5  in a 5-stage pipeline.
In addition, it includes the MIPS Architecture Virtualization Module
that enables virtualization of operating systems,
which provides a scalable, trusted, and secure execution environment.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6596/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:22 +01:00
Leonid Yegoshin 4975b86add MIPS: Add processor identifier for the M5150 processor
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6595/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:22 +01:00
Markos Chandras 8562580c5b MIPS: Add defconfig for Malta SMVP with EVA
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6581/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:22 +01:00
Paul Burton 77908561a6 MIPS: Default NR_CPUS=8 for malta SMP defconfigs
The previous NR_CPUS=2 default is not an optimal default for current
Malta setups where it is common to have more than 2 CPUs available. It
makes sense to increase this to a number which covers all common setups
currently in use, such that all of those cores are usable. 8 seems to
fit that description.

If the user has less than 8 CPUs & they wish to have a more optimal
kernel they can simply reduce this in their config. It makes sense for
the default to work on as many systems as possible.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6580/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:21 +01:00
Paul Burton a9c0c91cdc MIPS: Set page size to 16KB for malta SMP defconfigs
For Malta defconfigs which may run on an SMP configuration without
hardware cache anti-aliasing, a 16KB page size is a safer default.
Most notably at the moment it will avoid cache aliasing issues for
multicore proAptiv systems.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6579/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:21 +01:00
Markos Chandras 68f30ba7f8 MIPS: Malta: Enable DEVTMPFS
Recent versions of udev and systemd require the kernel
to be compiled with CONFIG_DEVTMPFS in order to populate
the /dev directory. Most MIPS platforms have it enabled by
default, so enable it for Malta configs as well.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6582/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:21 +01:00
Paul Burton a86dc81288 MIPS: Regenerate malta defconfigs
This patch simply regenerates the malta defconfigs such that they don't
change after being used & saved as a defconfig again. ie. it is the
result of running the following:

for cfg in arch/mips/configs/malta*; do
	ARCH=mips make `basename ${cfg}`
	ARCH=mips make savedefconfig
	mv -v defconfig ${cfg}
done

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6578/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:21 +01:00
Manuel Lauss 54ff4a1d17 MIPS: Alchemy: pata_platform for DB1200
The au1xxx-ide driver isn't any faster than pata_platform since it
spends a lot of time busy waiting for DMA to finish; faster PIO/DMA
modes only work on the db1200 with a certain cpu speed, UDMA is broken,
and finally the old IDE layer is on death row, so time to switch to
the newer ATA layer.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/6662/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:21 +01:00
Manuel Lauss a16afa5327 MIPS: Alchemy: fold mach-db1xxx/db1x00 headers into board code
Merge the db1200.h and db1300.h headers into their only users.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/6660/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:21 +01:00
Manuel Lauss 970e268d6e MIPS: Alchemy: Unify Devboard support.
This patch merges support for all DB1xxx and PB1xxx
boards into a single image, along with a new single defconfig
for them.

Run-tested on DB1300 and DB1500.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/6577/
Patchwork: https://patchwork.linux-mips.org/patch/6659/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:21 +01:00
Manuel Lauss 88e9a93c9d MIPS: Alchemy: Determine cohereny at runtime based on cpu type
All Alchemy chips have coherent DMA, but for example the USB or AC97
peripherals on the Au1000/1500/1100 are not.
This patch uses DMA_MAYBE_COHERENT on Alchemy and sets coherentio based
on CPU type.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/6576/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:21 +01:00
Manuel Lauss 8005711c8d MIPS: Extend DMA_MAYBE_COHERENT logic to DMA_NONCOHERENT use
Setting DMA_MAYBE_COHERENT gives a platform the opportunity to select
use of cache ops at boot.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/6575/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:20 +01:00
Markos Chandras bfc3c5a6c7 MIPS: Enable MIPS 3.5 features on Malta
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:20 +01:00
Markos Chandras d0ba3544a5 MIPS: malta: Add support for SMP EVA
Allow secondary cores to program their segment control registers
during smp bootstrap code. This enables EVA on Malta SMP
configurations

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:20 +01:00
Leonid Yegoshin 2f284eac28 MIPS: malta: malta-init: Fix System Controller memory mapping for EVA
Shift System Controller memory mapping to 0x80000000

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:20 +01:00
Markos Chandras d1965c0616 MIPS: malta: malta-memory: Add free_init_pages_eva() callback
Use a Malta specific function to free the init section once the
kernel has booted. When operating in EVA mode, the physical memory
is shifted to 0x80000000. Kernel is loaded into 0x80000000 (virtual)
so the offset between physical and virtual addresses is 0.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:20 +01:00
Markos Chandras 3bdd8e6e09 MIPS: malta: malta-memory: Use the PHYS_OFFSET to build the memory map
PHYS_OFFSET is used to denote the physical start address of the
first bank of RAM. When the Malta board is in EVA mode, the physical
start address of RAM is shifted to 0x80000000 so it's necessary to use
this macro in order to make the code EVA agnostic.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:20 +01:00
Markos Chandras e6ca4e5bf1 MIPS: malta: malta-memory: Add support for the 'ememsize' variable
The 'ememsize' variable is used to denote the real RAM which is
present on the Malta board. This is different compared to 'memsize'
which is capped to 256MB. The 'ememsize' is used to get the actual
physical memory when setting up the Malta memory layout. This only
makes sense in case the core operates in the EVA mode, and it's
ignored otherwise.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:20 +01:00
Markos Chandras c9fede2afc MIPS: malta: spaces.h: Add spaces.h file for Malta (EVA)
Add a spaces.h file for Malta to override certain memory macros
when operating in EVA mode.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:19 +01:00
Markos Chandras f8b7faf17b MIPS: malta: Configure Segment Control registers for EVA boot
The Malta board aliases 0x80000000 - 0xffffffff to 0x00000000
- 0x7fffffff ignoring the 256 MB IO hole in 0x10000000.
The physical memory is shifted to 0x80000000 so up to 2GB
can be used. Kuseg is expanded to 3GB (due to board limitations
only 2GB can be accessed) and lowmem (kernel space) is expanded to 2GB.

The Segment Control registers are programmed as follows:

Virtual memory           Physical memory           Mapping
0x00000000 - 0x7fffffff  0x80000000 - 0xfffffffff   MUSUK (kuseg)
0x80000000 - 0x9fffffff  0x00000000 - 0x1ffffffff   MUSUK (kseg0)
0xa0000000 - 0xbf000000  0x00000000 - 0x1ffffffff   MUSUK (kseg1)
0xc0000000 - 0xdfffffff             -                 MK  (kseg2)
0xe0000000 - 0xffffffff             -                 MK  (kseg3)

The location of exception vectors remain the same since 0xbfc00000
(traditional exception base) still maps to 0x1fc00000 physical.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:19 +01:00
Leonid Yegoshin 4676f9359f MIPS: mm: c-r4k: Flush scache to avoid cache aliases
There is a chance for the secondary cache to have memory
aliases. This can happen if the bootloader is in a non-EVA mode
(or even in EVA mode but with different mapping from the kernel)
and the kernel switching to EVA afterwards. It's best to flush
the icache to avoid having the secondary CPUs fetching stale
data from it.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:19 +01:00
Markos Chandras 80ca69f40f MIPS: mm: c-r4k: Add support for flushing user pages from cache
Use the userspace cache flushing functions if the interrupted
process is a userspace one.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:19 +01:00
Leonid Yegoshin 4caa906ee9 MIPS: mm: c-r4k: Build EVA {d,i}cache flushing functions
Build EVA specific cache flushing functions (ie cachee).
They will be used by a subsequent patch.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:19 +01:00
Markos Chandras 0893d3fb8d MIPS: mm: init: Add free_init_pages() callback for EVA
A core in EVA mode can have any possible segment mapping, so the
default free_initmem_default() function may not always work as expected.
Therefore, add a callback that platforms can use to free up the init section.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:18 +01:00
Markos Chandras 91119686f3 MIPS: kernel: proc: Add EVA to the list of CPU features
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:18 +01:00
Markos Chandras 49016748ec MIPS: kernel: cpu-probe: Enable EVA option on supported cores
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:18 +01:00
Markos Chandras 7ae6696656 MIPS: asm: cpu: Add cpu flag for Enhanced Virtual Addressing
The MIPS *Aptiv family uses bit 28 in Config5 CP0 register to
indicate whether the core supports EVA or not.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:18 +01:00
Leonid Yegoshin 27b3db2031 MIPS: asm: page: Allow __pa_symbol overrides
This will allow platforms to use an alternative way to get
the physical address of a symbol.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:18 +01:00
Leonid Yegoshin 6ebda44f36 MIPS: kernel: {ftrace,kgdb}: Set correct address limit for cache flushes
When flushing the icache, make sure the address limit is correct
so the appropriate 'cache' instruction will be used. This has no
impact on cores operating in non-eva mode. However, when EVA is
enabled, we ensure that 'cache' will be used instead of 'cachee'.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:18 +01:00
Leonid Yegoshin de8974e3f7 MIPS: asm: r4kcache: Add EVA cache flushing functions
Add EVA cache flushing functions similar to non-EVA configurations.
Because the cache may or may not contain user virtual addresses, we
need to use the 'cache' or 'cachee' instruction based on whether we
flush the cache on behalf of kernel or user respectively.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:18 +01:00
Leonid Yegoshin a805385499 MIPS: asm: r4kcache: Add protected cache operation for EVA
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:18 +01:00
Leonid Yegoshin 41e62b0411 MIPS: asm: r4kcache: Build flushing code for instruction cache
Build code to invalidate an address range in the  instruction cache
using the Hit Invalidate cache operation.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:18 +01:00
Leonid Yegoshin ca750649e0 MIPS: kernel: signal: Prevent save/restore FPU context in user memory
EVA does not have FPU specific instructions for reading or writing
FPU registers from userspace memory.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:17 +01:00
Leonid Yegoshin c2d85bc104 MIPS: asm: checksum: Add MIPS specific csum_and_copy_from_user function
A MIPS specific csum_and_copy_from_user function is necessary because
the generic one from include/net/checksum.h will not work for EVA.
This is because the generic one will link to symbols from lib/checksum.c
which are not EVA aware.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:17 +01:00
Leonid Yegoshin fb316913f8 MIPS: asm: checksum: Split kernel and user copy operations
In EVA mode, different instructions need to be used to read/write
from kernel and userland. In non-EVA mode, there is no functional
difference. The current address limit is checked to decide the
type of operation that will be performed.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:17 +01:00
Markos Chandras 6f85cebe49 MIPS: lib: csum_partial: Add EVA support
Use EVA specific functions to read and write data to
user address space.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:17 +01:00
Markos Chandras e89fb56c8b MIPS: lib: csum_partial: Add macro to build csum_partial symbols
In preparation for EVA support, we use a macro to build the
__csum_partial_copy_user main code so it can be shared across
multiple implementations. EVA uses the same code but it replaces
the load/store/prefetch instructions with the EVA specific ones
therefore using a macro avoids unnecessary code duplications.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:17 +01:00
Markos Chandras 2ab82e6648 MIPS: lib: csum_partial: Merge EXC and load/store macros
Each load/store macro always adds an entry to the __ex_table
using the EXC macro. There are cases where a load instruction may
never fail such as when we are sure the load happens in the kernel
address space. Therefore, we merge these the EXC and LOADX/STOREX
macros into a single one. We also expand the argument list in the EXC
macro to make the macro more flexible. The extra 'type' argument is not
used by this commit, but it will be used when EVA support is added to
memcpy.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:17 +01:00
Markos Chandras ac85227f76 MIPS: checksum: Split the 'copy_user' symbol
The 'copy_user' symbol can be used to copy from or to
userland so we will use two different symbols for these
operations. This makes no difference in the existing code,
but when the core is operating in EVA mode, different instructions
need to be used to read and write to userland address space.
The old function has also been renamed to 'copy_kernel' to denote
that it is suitable for copy data to and from kernel space.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:17 +01:00
Leonid Yegoshin c1771216ab MIPS: kernel: unaligned: Handle unaligned accesses for EVA
Handle unaligned accesses when we access userspace memory
EVA mode.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:16 +01:00
Markos Chandras 9d8e573683 MIPS: kernel: unaligned: Add EVA instruction wrappers
Use the load/store instruction wrappers from asm/asm.h to
perform such operations when operating in EVA mode.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:16 +01:00
Markos Chandras e3a9b07a9c MIPS: asm: uaccess: Add EVA support for str*_user operations
The str*_user functions are used to securely access NULL terminated
strings from userland. Therefore, it's necessary to use the appropriate
EVA function. However, if the string is in kernel space, then the normal
instructions are being used to access it. The __str*_kernel_asm and
__str*_user_asm symbols are the same for non-EVA mode so there is no
functional change for the non-EVA kernels.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:16 +01:00
Markos Chandras 05c6516005 MIPS: asm: uaccess: Add EVA support to copy_{in, to,from}_user
Use the EVA specific functions from memcpy.S to perform
userspace operations. When get_fs() == get_ds() the usual load/store
instructions are used because the destination address is located in
the kernel address space region. Otherwise, the EVA specifc load/store
instructions are used which will go through th TLB to perform the virtual
to physical translation for the userspace address.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:16 +01:00
Markos Chandras 0081ad2486 MIPS: asm: uaccess: Rename {get,put}_user_asm macros
The {get,put}_user_asm functions can be used to load data from
kernel or the user address space so rename them to avoid
confusion.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:16 +01:00
Markos Chandras ac1d8590d3 MIPS: asm: uaccess: Use EVA instructions wrappers
Use the EVA instruction wrappers from asm.h to perform
read/write operations from userland.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:16 +01:00
Leonid Yegoshin 18e900185b MIPS: asm: uaccess: Disable unaligned access macros for EVA
ulb, ulh, ulw are macros which emulate unaligned access for MIPS.
However, no such macros exist for EVA mode, so the only way to do
EVA unaligned accesses is in the ADE exception handler. As a result
of which, disable these macros for EVA.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:15 +01:00
Markos Chandras ec56b1d461 MIPS: asm: uaccess: Move duplicated code to common function
Similar to __get_user_* functions, move common code to
__put_user_*_common so it can be shared among similar users.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:15 +01:00
Markos Chandras d84869a19f MIPS: asm: uaccess: Add instruction argument to __{put,get}_user_asm
In preparation for EVA support, an instruction argument is needed
for the __get_user_asm{,_ll32} functions to allow instruction overrides in
EVA mode. Even though EVA only works for MIPS 32-bit, both codepaths are
changed (32-bit and 64-bit) for consistency reasons.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:15 +01:00
Markos Chandras fd9720e96e MIPS: lib: memset: Add EVA support for the __bzero function.
Build the __bzero function using the EVA load/store instructions
when operating in the EVA mode. This function is only used when
accessing user code so there is no need to build two distinct symbols
for user and kernel operations respectively.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:15 +01:00
Markos Chandras 6d5155c2a6 MIPS: lib: memset: Use macro to build the __bzero symbol
Build the __bzero symbol using a macor. In EVA mode we will
need to use similar code to do the userspace load operations so
it is better if we use a macro to avoid code duplications.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:15 +01:00
Markos Chandras 8483b14aaa MIPS: lib: memset: Whitespace fixes
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:14 +01:00
Markos Chandras cd26cb41ec MIPS: lib: memcpy: Add EVA support
Add copy_{to,from,in}_user when the CPU operates in EVA mode.
This is necessary so the EVA specific instructions can be used
to perform the virtual to physical translation for user space
addresses. We will use the non-EVA functions to read from kernel
if needed.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:14 +01:00
Markos Chandras cf62a8b813 MIPS: lib: memcpy: Use macro to build the copy_user code
The code can be shared between EVA and non-EVA configurations,
therefore use a macro to build it to avoid code duplications.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:14 +01:00
Markos Chandras bda4d986a6 MIPS: lib: memcpy: Split source and destination prefetch macros
In preparation for EVA support, the PREF macro is split into two
separate macros, PREFS and PREFD, for source and destination data
prefetching respectively.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:14 +01:00
Markos Chandras 5bc05971d3 MIPS: lib: memcpy: Merge EXC and load/store macros
Each load/store macro always adds an entry to the __ex_table
using the EXC macro. Therefore, these load/store macros are now merged
with the EXC one. The argument list is also expanded in order to make
the macro more flexible. The extra 'type' argument is not used by this
commit, but it will be used when the EVA support is added to the memcpy.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:14 +01:00
Markos Chandras b3c3025b2c MIPS: lib: strncpy_user: Add EVA support
In non-EVA mode, strncpy_from_user* aliases are used for the
strncpy_from_kernel* symbols since the code is identical. In EVA
mode, new strcpy_from_user* symbols are used which use the EVA
specific instructions to load values from userspace.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:14 +01:00
Markos Chandras cc59fe5b88 MIPS: lib: strncpy_user: Use macro to build the strncpy_from_user symbol
Build the __strncpy_from_user symbol using a macro. In EVA mode we will
need to use similar code to do the userspace load operations so
it is better if we use a macro to avoid code duplications.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:14 +01:00
Markos Chandras 053970542f MIPS: lib: strlen_user: Add EVA support
In non-EVA mode, strlen_user* aliases are used for the
strlen_kernel* symbols since the code is identical. In EVA
mode, new strlen_user* symbols are used which use the EVA
specific instructions to load values from userspace.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:13 +01:00
Markos Chandras 5cc494972a MIPS: lib: strlen_user: Use macro to build the strlen_user symbol
Build the __strlen_user symbol using a macro. In EVA mode we will
need to use similar code to do the userspace load operations so
it is better if we use a macro to avoid code duplications.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:13 +01:00
Markos Chandras 4968db4b9c MIPS: lib: strnlen_user: Add EVA support
In non-EVA mode, a strlen_user* alias is used for the
strlen_kernel* symbols since the code is identical. In EVA
mode, a new strlen_user* symbol is used which uses the EVA
specific instructions to load values from userspace.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:13 +01:00
Markos Chandras c48be43eb5 MIPS: lib: strnlen_user: Use macro to build the strnlen_user symbol
Build the __strnlen_user symbol using a macro. In EVA mode we will
need to use similar code to do the userspace load operations so
it is better if we use a macro to avoid code duplications.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:13 +01:00
Leonid Yegoshin 078dde5e21 MIPS: traps: Set correct address limit for breakpoints and traps
When a breakpoint or trap happens when operating in kernel mode but
on users behalf (eg syscall) it is necessary to change the address
limit to KERNEL_DS so any address checking can be bypassed and print
the correct stack trace.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:13 +01:00
Markos Chandras b08a9c95f8 MIPS: kernel: traps: Whitespace clean up
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:13 +01:00
Markos Chandras 86bdb2779d MIPS: kernel: scall32-o32: Use EVA wrappers to fetch syscall arguments
Arguments 4-8 are stored on user's stack, so use the EVA instructions
to fetch them if EVA is enabled.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:13 +01:00
Leonid Yegoshin aa1af47f5d MIPS: uapi: inst: Add instruction format for SPECIAL3 instructions
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:12 +01:00
Leonid Yegoshin a442c9e7b8 MIPS: uapi: inst: Add new EVA opcodes
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:12 +01:00
Markos Chandras a6813fe5c2 MIPS: futex: Add EVA support for futex operations
Use LLE/SCE instructions for performing an address translation for
userspace when EVA is enabled.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:12 +01:00
Markos Chandras 9324494595 MIPS: asm: Add wrappers for EVA/non-EVA instructions
EVA uses specific instructions for accessing user memory.
Instead of polluting the kernel with numerous #ifdef CONFIG_EVA
we add wrappers for all the instructions that need special
handling when EVA is enabled.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:12 +01:00
Leonid Yegoshin 5b736cd243 MIPS: asm: Add prefetch instruction for EVA
EVA can use the PREFE instruction to perform the virtual address
translation using the user mapping of the address rather than the
kernel mapping.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:12 +01:00
Leonid Yegoshin a6e18781c5 MIPS: Kconfig: Add Kconfig symbols for EVA support
Add basic Kconfig support for EVA. Not selectable by any platform
at this point.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26 23:09:12 +01:00
James Hogan 8c7f6ba342 MIPS: OProfile: Add CPU_P5600 cases
Add a CPU_P5600 cpu type case in oprofile_arch_init() to use the MIPS
model, and in mipsxx_init() to set the cpu_type string to "mips/P5600".

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Robert Richter <rric@kernel.org>
Cc: oprofile-list@lists.sf.net
Patchwork: https://patchwork.linux-mips.org/patch/6410/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:12 +01:00
James Hogan d83b0e82ad MIPS: Allow FTLB to be turned on for CPU_P5600
Allow FTLB to be turned on or off for CPU_P5600 as well as CPU_PROAPTIV.
The existing if statement is converted into a switch to allow for future
expansion.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6411/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:11 +01:00
James Hogan 829dcc0a95 MIPS: Add MIPS P5600 probe support
Add a case in cpu_probe_mips for the MIPS P5600 processor ID, which sets
the CPU type to the new CPU_P5600.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6409/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:11 +01:00
James Hogan aced4cbd6e MIPS: Add cases for CPU_P5600
Add a CPU_P5600 case to various switch statements, doing the same thing
as for CPU_PROAPTIV.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6408/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:11 +01:00
James Hogan f43e4dfd39 MIPS: Add MIPS P5600 PRid and cputype identifiers
Add a Processor ID and CPU type for the MIPS P5600 core.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6407/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:11 +01:00
Paul Burton eec43a224c MIPS: Save/restore MSA context around signals
This patch extends sigcontext in order to hold the most significant 64
bits of each vector register in addition to the MSA control & status
register. The least significant 64 bits are already saved as the scalar
FP context. This makes things a little awkward since the least & most
significant 64 bits of each vector register are not contiguous in
memory. Thus the copy_u & insert instructions are used to transfer the
values of the most significant 64 bits via GP registers.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6533/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:11 +01:00
Paul Burton a8ad136789 MIPS: Warn if vector register partitioning is implemented
No current systems implementing MSA include support for vector register
partitioning which makes it somewhat difficult to implement support for
it in the kernel. Thus for the moment the kernel includes no such
support. However if the kernel were to be run on a system which
implemented register partitioning then it would not function correctly,
mishandling MSA disabled exceptions. Print a warning if run on a system
with vector register partitioning implemented to indicate this problem
should it occur.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6494/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:11 +01:00
Paul Burton 2bcb3fbc3f MIPS: Dumb MSA FP exception handler
This patch adds a simple handler for MSA FP exceptions which delivers a
SIGFPE to the running task. In the future it should probably be extended
to re-execute the instruction with the MSACSR.NX bit set in order to
generate results for any elements which did not cause an exception
before delivering the SIGFPE signal.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6432/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:10 +01:00
Paul Burton 1db1af84d6 MIPS: Basic MSA context switching support
This patch adds support for context switching the MSA vector registers.
These 128 bit vector registers are aliased with the FP registers - an
FP register accesses the least significant bits of the vector register
with which it is aliased (ie. the register with the same index). Due to
both this & the requirement that the scalar FPU must be 64-bit (FR=1) if
enabled at the same time as MSA the kernel will enable MSA & scalar FP
at the same time for tasks which use MSA. If we restore the MSA vector
context then we might as well enable the scalar FPU since the reason it
was left disabled was to allow for lazy FP context restoring - but we
just restored the FP context as it's a subset of the vector context. If
we restore the FP context and have previously used MSA then we have to
restore the whole vector context anyway (see comment in
enable_restore_fp_context for details) so similarly we might as well
enable MSA.

Thus if a task does not use MSA then it will continue to behave as
without this patch - the scalar FP context will be saved & restored as
usual. But if a task executes an MSA instruction then it will save &
restore the vector context forever more.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6431/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:10 +01:00
Paul Burton a5e9a69e2c MIPS: Detect the MSA ASE
This patch adds support for probing the MSAP bit within the Config3
register in order to detect the presence of the MSA ASE. Presence of the
ASE will be indicated in /proc/cpuinfo. The value of the MSA
implementation register will be displayed at boot to aid debugging and
verification of a correct setup, as is done for the FPU.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6430/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:10 +01:00
Paul Burton 7f65afb97f MIPS: Add MSA register definitions & access
This patch introduces definitions for the MSA control registers and
functions which allow access to both the control & vector registers. If
the toolchain being used to build the kernel includes support for MSA
then this patch will make use of that support & use MSA instructions
directly. However toolchain support for MSA is very new & far from a
point where it can be reasonably expected that everyone building the
kernel uses a toolchain with support. Thus fallbacks using .word
assembler directives are also provided for now as a temporary measure.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6429/
Patchwork: https://patchwork.linux-mips.org/patch/6607/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:10 +01:00
Paul Burton 02987633df MIPS: Don't assume 64-bit FP registers for context switch
When saving or restoring scalar FP context we want to access the least
significant 64 bits of each FP register. When the FP registers are 64
bits wide that is trivially the start of the registers value in memory.
However when the FP registers are wider this equivalence will no longer
be true for big endian systems. Define a new set of offset macros for
the least significant 64 bits of each saved FP register within thread
context, and make use of them when saving and restoring scalar FP
context.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6428/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:10 +01:00
Paul Burton 72b22bbad1 MIPS: Don't assume 64-bit FP registers for FP regset
When we want to access 64-bit FP register values we can only treat
consecutive registers as being consecutive in memory when the width of
an FP register equals 64 bits. This assumption will not remain true once
MSA support is introduced, so provide a code path which copies each 64
bit FP register value in turn when the width of an FP register differs
from 64 bits.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6427/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:10 +01:00
Paul Burton 6cec7c4ad7 MIPS: Don't assume 64-bit FP registers for dump_{,task_}fpu
This code assumed that saved FP registers are 64 bits wide, an
assumption which will no longer be true once MSA is introduced. This
patch modifies the code to copy the lower 64 bits of each register in
turn, which is safe for any FP register width >= 64 bits.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6425/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:10 +01:00
Paul Burton ef1c47afc0 MIPS: Clear upper bits of FP registers on emulator writes
The upper bits of an FP register are architecturally defined as
unpredictable following an instructions which only writes the lower
bits. The prior behaviour of the kernel is to leave them unmodified.
This patch modifies that to clear the upper bits to zero. This is what
the MSA architecture reference manual specifies should happen for its
wider registers and is still permissible for scalar FP instructions
given the bits unpredictability there.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: sergei.shtylyov@cogentembedded.com
Patchwork: https://patchwork.linux-mips.org/patch/6435/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:10 +01:00
Paul Burton 6bbfd65e28 MIPS: Replace hardcoded 32 with NUM_FPU_REGS in ptrace
NUM_FPU_REGS just makes it clearer what's going on, rather than the
magic hard coded 32.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6424/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:09 +01:00
Paul Burton ff3aa5f296 MIPS: Don't require FPU on sigcontext setup/restore
When a task which has used the FPU at some point in its past takes a
signal the kernel would previously always require the task to take
ownership of the FPU whilst setting up or restoring from the sigcontext.
That means that if the task has not used the FPU within this timeslice
then the kernel would enable the FPU, restore the task's FP context into
FPU registers and then save them into the sigcontext. This seems
inefficient, and if the signal handler doesn't use FP then enabling the
FPU & the extra memory accesses are entirely wasted work.

This patch modifies the sigcontext setup & restore code to copy directly
between the tasks saved FP context & the sigcontext for any tasks which
have used FP in the past but are not currently the FPU owner (ie. have
not used FP in this timeslice).

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Qais Yousef <qais.yousef@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6423/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:09 +01:00
Paul Burton b2ead52828 MIPS: Move & rename fpu_emulator_{save,restore}_context
These functions aren't directly related to the FPU emulator at all, they
simply copy between a thread's saved context & a sigcontext. Thus move
them to the appropriate signal files & rename them accordingly. This
makes it clearer that the functions don't require the FPU emulator in
any way.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Qais Yousef <qais.yousef@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6422/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:09 +01:00
Paul Burton e87ce94822 MIPS: Update outdated comment
The hard-coded offsets mentioned in this comment seem to not exist
anymore, so remove mention of them from the comment.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Qais Yousef <qais.yousef@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6421/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:09 +01:00
Paul Burton bbd426f542 MIPS: Simplify FP context access
This patch replaces the fpureg_t typedef with a "union fpureg" enabling
easier access to 32 & 64 bit values. This allows the access macros used
in cp1emu.c to be simplified somewhat. It will also make it easier to
expand the width of the FP registers as will be done in a future
patch in order to support the 128 bit registers introduced with MSA.

No behavioural change is intended by this patch.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Qais Yousef <qais.yousef@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6532/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:09 +01:00
Markos Chandras 490b004feb MIPS: Select HAVE_ARCH_SECCOMP_FILTER
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6401/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:09 +01:00
Markos Chandras 4c21b8fd8f MIPS: seccomp: Handle indirect system calls (o32)
When userland uses syscall() to perform an indirect system call
the actually system call that needs to be checked by the filter
is on the first argument. The kernel code needs to handle this case
by looking at the original syscall number in v0 and if it's
NR_syscall, then it needs to examine the first argument to
identify the real system call that will be executed.
Similarly, we need to 'virtually' shift the syscall() arguments
so the syscall_get_arguments() function can fetch the correct
arguments for the indirect system call.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6404/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:08 +01:00
Markos Chandras 9d37c405ed MIPS: kernel: scalls: Skip the syscall if denied by the seccomp filter
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6399/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:08 +01:00
Markos Chandras 1225eb8252 MIPS: ptrace: Move away from secure_computing_strict
MIPS now has the infrastructure for dynamic seccomp-bpf
filtering

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6400/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:08 +01:00
Markos Chandras 137f7df8ce MIPS: asm: thread_info: Add _TIF_SECCOMP flag
Add _TIF_SECCOMP flag to _TIF_WORK_SYSCALL_ENTRY to indicate
that the system call needs to be checked against a seccomp filter.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6405/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:08 +01:00
Markos Chandras 6e34574603 MIPS: asm: syscall: Define syscall_get_arch
This effectively renames __syscall_get_arch to syscall_get_arch
and implements a compatible interface for the seccomp API.
The seccomp code (kernel/seccomp.c) expects a syscall_get_arch
function to be defined for every architecture, so we drop
the leading underscores from the existing function.

This also makes use of the 'task' argument to determine the type
the process instead of assuming the process has the same
characteristics as the kernel it's running on.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6398/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:08 +01:00
Markos Chandras 22feadbe4c MIPS: asm: syscall: Add the syscall_rollback function
The syscall_rollback function is used by seccomp-bpf but it was never
added for MIPS. It doesn't need to do anything as none of the registers
are clobbered if the system call has been denied by the seccomp filter.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6403/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:08 +01:00
Paul Burton 5cac93b35c MIPS: Deprecate CONFIG_MIPS_CMP
CONFIG_MIPS_CPS is a better option for systems where it is supported,
which as far as I am aware should be all systems where CONFIG_MIPS_CMP
could provide any value (ie. where there are multiple cores for YAMON to
bring up). This option is therefore deprecated, and marked as such. It
is left intact for the time being in order to provide a fallback should
someone find a system where CONFIG_MIPS_CPS will not function (ie. where
the reset vector cannot be moved), and should be removed entirely in the
future assuming that does not happen.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6369/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:08 +01:00
Paul Burton a6ce202ead MIPS: MIPS_CMP should depend upon !SMTC, not upon SMVP
Commit f55afb0969cc "MIPS: Clean up MIPS MT and CMP configuration
options." introduced a dependency upon MIPS_MT_SMP (ie. SMVP) for the
MIPS_CMP (ie. CMP framework support) Kconfig option. It did not specify
why, and that dependency is bogus. It is perfectly valid to have a
multi-core system with the YAMON bootloader but without MT support -
an example of this would be any multi-core proAptiv bitstream running on
a Malta. Forcing MT support to be enabled in a kernel for such a system
is incorrect. I suspect that the dependency was actually meant to
reflect the fact that YAMON will only bind 1 TC per VPE on an MT system,
and only describe those 1:1 TC:VPE pairs as CPUs through the AMON
interface. Thus an SMTC kernel makes little sense on a system using
MIPS_CMP, and the Kconfig dependencies should reflect that rather than
introducing the bogus SMVP dependency.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6368/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:08 +01:00
Paul Burton 044505c780 MIPS: More helpful CONFIG_MIPS_CMP label, help text
The prior help text introduced in commit f55afb0969cc "MIPS: Clean up
MIPS MT and CMP configuration options." reads as though this option
enables the kernel to make use of the CM hardware, which is not true.
What it actually does is allow the kernel to interact with the YAMON
bootloader which actually interacts with the CM hardware to bring up
secondary cores. Re-introduce the word "framework" which that commit
removed to avoid misleading people.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6367/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:07 +01:00
Paul Burton 9d9812706f MIPS: Remove gcmpregs.h
This header was used only by Malta but is used no longer. Remove it. It
was also included unnecessarily in irq-gic.c, so that include is also
removed.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6366/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:07 +01:00
Paul Burton e56b6aa6da MIPS: Malta: Allow use of MIPS CPS SMP implementation
This patch simply attempts to register the MIPS Coherent Processing
System SMP implementation when it is enabled. If registering that fails
for some reason (like the Kconfig option being disabled or a lack of
hardware support) then we fall back to the same SMP implementations as
before.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6365/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:07 +01:00
Paul Burton 7dc2834fd5 MIPS: Malta: Probe CPC when supported
When CPC support is compiled into the kernel (ie. CONFIG_MIPS_CPC=y),
probe the CPC on boot for Malta in order to allow any users of the CPC
to detect its presence & function correctly.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6363/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:06 +01:00
Paul Burton 237036de65 MIPS: Malta: Make use of generic CM support
Remove the Malta-specific CM probe code and instead make use of the
newly added generic CM code.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6364/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:09:06 +01:00
Krzysztof Halasa 00e1b3a3d1 IXP4xx: Fix DMA masks.
Now, devices will have 32-bit default DMA masks (0xFFFFFFFF) as per DMA API.

Fixes:
$ ifconfig eth0 up
net eth0: coherent DMA mask is unset

$ ifconfig hdlc0 up
net hdlc0: coherent DMA mask is unset

Also fixes a cosmetic off-by-one bug which caused DMA transfers ending exactly
on the 64 MiB boundary to go through dmabounce unnecessarily.

Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
Tested-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-26 23:08:11 +01:00
Arnd Bergmann 53ad835ce7 Revert "ARM: ixp4xx: Make dma_set_coherent_mask common, correct implementation"
This reverts commit bfdad565ae.

The patch turned out to be incorrect, and will be replaced
with a correct patch.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-26 23:07:17 +01:00
Krzysztof Halasa e1a4018f93 IXP4xx: Fix Goramo Multilink GPIO conversion.
Commit 098e30f655 "ARM: ixp4xx: stop broadcasting the custom GPIO API"
changed the internal gpio code of ixp4xx to be accessible only from
common.c, but unfortunately that broke the Goramo MultiLink code, which
uses this API.

arch/arm/mach-ixp4xx/goramo_mlr.c: In function 'set_scl':
arch/arm/mach-ixp4xx/goramo_mlr.c:82: error: implicit declaration of function 'gpio_line_set'

arch/arm/mach-ixp4xx/goramo_mlr.c: In function 'output_control':
arch/arm/mach-ixp4xx/goramo_mlr.c:111: error: implicit declaration of function 'gpio_line_config'
arch/arm/mach-ixp4xx/goramo_mlr.c:111: error: 'IXP4XX_GPIO_OUT' undeclared

arch/arm/mach-ixp4xx/goramo_mlr.c: In function 'hss_dcd_irq':
arch/arm/mach-ixp4xx/goramo_mlr.c:155: error: implicit declaration of function 'gpio_line_get'

arch/arm/mach-ixp4xx/goramo_mlr.c: In function 'gmlr_init':
arch/arm/mach-ixp4xx/goramo_mlr.c:416: error: 'IXP4XX_GPIO_OUT' undeclared
arch/arm/mach-ixp4xx/goramo_mlr.c:421: error: 'IXP4XX_GPIO_IN' undeclared

Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-26 23:04:20 +01:00
Arnd Bergmann 9c9c6c55a8 Revert "ARM: ixp4xx: fix gpio rework"
This reverts commit 48ba81f6fd.

A better fix was sent by Krzysztof Halasa.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-26 23:03:18 +01:00
Paul Burton 0ee958e102 MIPS: Coherent Processing System SMP implementation
This patch introduces a new SMP implementation for systems implementing
the MIPS Coherent Processing System architecture. The kernel will make
use of the Coherence Manager, Cluster Power Controller & Global
Interrupt Controller in order to detect, bring up & make use of other
cores in the system. SMTC is not supported, so only a single TC per VPE
in the system is used. That is, this option enables an SMVP style setup
but across multiple cores.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6362/
Patchwork: https://patchwork.linux-mips.org/patch/6611/
Patchwork: https://patchwork.linux-mips.org/patch/6651/
Patchwork: https://patchwork.linux-mips.org/patch/6652/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:00:12 +01:00
Paul Burton b86c2247a2 MIPS: Add cpu_vpe_id macro
The vpe_id field of struct cpuinfo_mips is only present when one of
CONFIG_MIPS_MT_{SMP,SMTC} is enabled. That means that any code accessing
which may compile without MT is currently forced to use an #ifdef.
Instead this patch provides an accessor macro, #ifdef'd appropriately
to prevent further #ifdef's elsewhere.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6646/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26 23:00:05 +01:00
Tom Herbert 61b905da33 net: Rename skb->rxhash to skb->hash
The packet hash can be considered a property of the packet, not just
on RX path.

This patch changes name of rxhash and l4_rxhash skbuff fields to be
hash and l4_hash respectively. This includes changing uses of the
field in the code which don't call the access functions.

Signed-off-by: Tom Herbert <therbert@google.com>
Signed-off-by: Eric Dumazet <edumazet@google.com>
Cc: Mahesh Bandewar <maheshb@google.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-03-26 15:58:20 -04:00
Matt Fleming 204b0a1a4b x86, efi: Abstract x86 efi_early calls
The ARM EFI boot stub doesn't need to care about the efi_early
infrastructure that x86 requires in order to do mixed mode thunking. So
wrap everything up in an efi_call_early() macro.

This allows x86 to do the necessary indirection jumps to call whatever
firmware interface is necessary (native or mixed mode), but also allows
the ARM folks to mask the fact that they don't support relocation in the
boot stub and need to pass 'sys_table_arg' to every function.

[ hpa: there are no object code changes from this patch ]

Signed-off-by: Matt Fleming <matt.fleming@intel.com>
Link: http://lkml.kernel.org/r/20140326091011.GB2958@console-pimps.org
Cc: Roy Franz <roy.franz@linaro.org>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2014-03-26 11:30:03 -07:00
Anton Blanchard 7505258c5f KVM: PPC: Book3S HV: Fix KVM hang with CONFIG_KVM_XICS=n
I noticed KVM is broken when KVM in-kernel XICS emulation
(CONFIG_KVM_XICS) is disabled.

The problem was introduced in 48eaef05 (KVM: PPC: Book3S HV: use
xics_wake_cpu only when defined). It used CONFIG_KVM_XICS to wrap
xics_wake_cpu, where CONFIG_PPC_ICP_NATIVE should have been
used.

Signed-off-by: Anton Blanchard <anton@samba.org>
Cc: stable@vger.kernel.org
Signed-off-by: Paul Mackerras <paulus@samba.org>
Acked-by: Scott Wood <scottwood@freescale.com>
2014-03-26 23:34:56 +11:00
Laurent Dufour 69e9fbb278 KVM: PPC: Book3S: Introduce hypervisor call H_GET_TCE
This introduces the H_GET_TCE hypervisor call, which is basically the
reverse of H_PUT_TCE, as defined in the Power Architecture Platform
Requirements (PAPR).

The hcall H_GET_TCE is required by the kdump kernel, which uses it to
retrieve TCEs set up by the previous (panicked) kernel.

Signed-off-by: Laurent Dufour <ldufour@linux.vnet.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2014-03-26 23:34:27 +11:00
Greg Kurz e59d24e612 KVM: PPC: Book3S HV: Fix incorrect userspace exit on ioeventfd write
When the guest does an MMIO write which is handled successfully by an
ioeventfd, ioeventfd_write() returns 0 (success) and
kvmppc_handle_store() returns EMULATE_DONE.  Then
kvmppc_emulate_mmio() converts EMULATE_DONE to RESUME_GUEST_NV and
this causes an exit from the loop in kvmppc_vcpu_run_hv(), causing an
exit back to userspace with a bogus exit reason code, typically
causing userspace (e.g. qemu) to crash with a message about an unknown
exit code.

This adds handling of RESUME_GUEST_NV in kvmppc_vcpu_run_hv() in order
to fix that.  For generality, we define a helper to check for either
of the return-to-guest codes we use, RESUME_GUEST and RESUME_GUEST_NV,
to make it easy to check for either and provide one place to update if
any other return-to-guest code gets defined in future.

Since it only affects Book3S HV for now, the helper is added to
the kvm_book3s.h header file.

We use the helper in two places in kvmppc_run_core() as well for
future-proofing, though we don't see RESUME_GUEST_NV in either place
at present.

[paulus@samba.org - combined 4 patches into one, rewrote description]

Suggested-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2014-03-26 23:33:44 +11:00
Vineet Gupta f8b34c3fd5 ARC: [clockevent] simplify timer ISR
* Remove one liner IRQ ACK accessor, it was coming in the way of readability.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-03-26 14:31:30 +05:30
Vineet Gupta 35571f4bdc ARC: [clockevent] can't be SoC specific
So no point keeping it weak

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-03-26 14:31:29 +05:30
Richard Weinberger d345ea2892 ARC: Remove ARC_HAS_COH_RTSC
The symbol is an orphan, get rid of it.

Fixes: 7d0857a54a ("ARC: [SMP] Disallow RTSC")
Signed-off-by: Richard Weinberger <richard@nod.at>
Acked-by: Paul Bolle <pebolle@tiscali.nl>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-03-26 14:31:28 +05:30
Vineet Gupta ec7ac6afd0 ARC: switch to generic ENTRY/END assembler annotations
With commit 9df62f0544 "arch: use ASM_NL instead of ';'" the generic
macros can handle the arch specific newline quirk. Hence we can get rid
of ARC asm macros and use the "C" style macros.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-03-26 14:31:28 +05:30
Noam Camus d6579e99bc ARC: support external initrd
Currently ARC only supports embedded initrd. This patch enables
external ones too.

[vgupta: Changed from "rt_start"=start/"rd_size"=sz to unified "initrd"=start,sz]
Signed-off-by: Noam Camus <noamc@ezchip.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-03-26 14:31:27 +05:30
Mischa Jonker 80c1fe4c0d ARC: add uImage to .gitignore
Signed-off-by: Mischa Jonker <mjonker@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-03-26 14:31:26 +05:30
Mischa Jonker 18bff65e37 ARC: [arcfpga] Fix __initconst data const-correctness
Signed-off-by: Mischa Jonker <mjonker@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-03-26 14:31:25 +05:30
David S. Miller 04f58c8854 Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Conflicts:
	Documentation/devicetree/bindings/net/micrel-ks8851.txt
	net/core/netpoll.c

The net/core/netpoll.c conflict is a bug fix in 'net' happening
to code which is completely removed in 'net-next'.

In micrel-ks8851.txt we simply have overlapping changes.

Signed-off-by: David S. Miller <davem@davemloft.net>
2014-03-25 20:29:20 -04:00
Andy Lutomirski b9a4a56c1e x86, vdso, build: Don't rebuild 32-bit vdsos on every make
vdso32/vclock_gettime.o was confusing kbuild.

Signed-off-by: Andy Lutomirski <luto@amacapital.net>
Cc: Stefani Seibold <stefani@seibold.net>
Link: http://lkml.kernel.org/r/d741449340642213744dd659471a35bb970a0c4c.1395789923.git.luto@amacapital.net
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2014-03-25 17:08:58 -07:00
Carlo Caione 8ff973a267 ARM: sun7i/sun6i: dts: Add NMI irqchip support
This patch adds DTS entries for NMI controller as child of GIC.

Signed-off-by: Carlo Caione <carlo@caione.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-sunxi@googlegroups.com
Cc: mark.rutland@arm.com
Cc: hdegoede@redhat.com
Acked-by: maxime.ripard@free-electrons.com
Link: http://lkml.kernel.org/r/1395256879-8475-3-git-send-email-carlo@caione.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-26 01:00:50 +01:00
Mark Brown a23af4ab6b Merge remote-tracking branches 'asoc/fix/cs42l51', 'asoc/fix/cs42l52', 'asoc/fix/cs42l73', 'asoc/fix/rcar', 'asoc/fix/spear' and 'asoc/fix/tegra' into asoc-linus 2014-03-25 21:21:57 +00:00
H. Peter Anvin 26f5ef2e3c x86, vdso: Actually discard the .discard sections
The .discard/.discard.* sections are used to generate intermediate
results for the assembler (effectively "test assembly".)  The output
is waste and should not be retained.

Cc: Stefani Seibold <stefani@seibold.net>
Cc: Andy Lutomirski <luto@amacapital.net>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Link: http://lkml.kernel.org/n/tip-psizrnant8x3nrhbgvq2vekr@git.kernel.org
2014-03-25 13:41:36 -07:00
Bartlomiej Zolnierkiewicz 080c492df0 ARM: davinci: da850: update SATA AHCI support
Update SATA AHCI support to make use of the new ahci_da850 host
driver (instead of the generic ahci_platform one) and remove
deprecated ahci_platform_data code.

Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
2014-03-25 15:17:13 -04:00
Thomas Gleixner b712c8dae0 x86: hpet: Use proper destructor for delayed work
destroy_timer_on_stack() is hardly the right thing for a delayed
work. We leak a tracking object for the work itself when DEBUG_OBJECTS
is enabled.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Cc: x86@kernel.org
Link: http://lkml.kernel.org/r/20140323141940.034005322@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-25 17:34:01 +01:00
Paolo Bonzini f7b9ddb8a5 3 fixes
- memory leak on certain SIGP conditions
 - wrong size for idle bitmap (always too big)
 - clear local interrupts on initial CPU reset
 
 1 performance improvement
 - improve performance with many guests on certain workloads
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Merge tag 'kvm-s390-20140325' of git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux into kvm-next

3 fixes
- memory leak on certain SIGP conditions
- wrong size for idle bitmap (always too big)
- clear local interrupts on initial CPU reset

1 performance improvement
- improve performance with many guests on certain workloads
2014-03-25 15:44:06 +01:00
Jens Freimann 2ed10cc15e KVM: s390: clear local interrupts at cpu initial reset
Empty list of local interrupts when vcpu goes through initial reset
to provide a clean state

Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com>
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2014-03-25 13:27:12 +01:00
Thomas Huth 91880d07fc KVM: s390: Fix possible memory leak in SIGP functions
When kvm_get_vcpu() returned NULL for the destination CPU in
__sigp_emergency() or __sigp_external_call(), the memory for the
"inti" structure was not released anymore. This patch fixes this
issue by moving the check for !dst_vcpu before the kzalloc() call.

Signed-off-by: Thomas Huth <thuth@linux.vnet.ibm.com>
Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2014-03-25 13:27:11 +01:00
Jens Freimann 609433fbed KVM: s390: fix calculation of idle_mask array size
We need BITS_TO_LONGS, not sizeof(long) to calculate
the correct size.

idle_mask is a bitmask, each bit representing the state
of a cpu. The desired outcome is an array of unsigned long
fields that can fit KVM_MAX_VCPUS bits. We should not use
sizeof(long) which returnes the size in bytes, but BITS_TO_LONGS

Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com>
Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2014-03-25 13:27:11 +01:00
Christian Borntraeger f6c137ff00 KVM: s390: randomize sca address
We allocate a page for the 2k sca, so lets use the space to improve
hit rate of some internal cpu caches. No need to change the freeing
of the page, as this will shift away the page offset bits anyway.

Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
Reviewed-by: David Hildenbrand <dahi@linux.vnet.ibm.com>
2014-03-25 13:27:10 +01:00
Mathias Krause 37b2894717 crypto: x86/sha1 - reduce size of the AVX2 asm implementation
There is really no need to page align sha1_transform_avx2. The default
alignment is just fine. This is not the hot code but only the entry
point, after all.

Cc: Chandramouli Narayanan <mouli@linux.intel.com>
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-by: H. Peter Anvin <hpa@linux.intel.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2014-03-25 20:25:43 +08:00
Mathias Krause 6c8c17cc7a crypto: x86/sha1 - fix stack alignment of AVX2 variant
The AVX2 implementation might waste up to a page of stack memory because
of a wrong alignment calculation. This will, in the worst case, increase
the stack usage of sha1_transform_avx2() alone to 5.4 kB -- way to big
for a kernel function. Even worse, it might also allocate *less* bytes
than needed if the stack pointer is already aligned bacause in that case
the 'sub %rbx, %rsp' is effectively moving the stack pointer upwards,
not downwards.

Fix those issues by changing and simplifying the alignment calculation
to use a 32 byte alignment, the alignment really needed.

Cc: Chandramouli Narayanan <mouli@linux.intel.com>
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-by: H. Peter Anvin <hpa@linux.intel.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2014-03-25 20:25:43 +08:00
Mathias Krause 6ca5afb8c2 crypto: x86/sha1 - re-enable the AVX variant
Commit 7c1da8d0d0 "crypto: sha - SHA1 transform x86_64 AVX2"
accidentally disabled the AVX variant by making the avx_usable() test
not only fail in case the CPU doesn't support AVX or OSXSAVE but also
if it doesn't support AVX2.

Fix that regression by splitting up the AVX/AVX2 test into two
functions. Also test for the BMI1 extension in the avx2_usable() test
as the AVX2 implementation not only makes use of BMI2 but also BMI1
instructions.

Cc: Chandramouli Narayanan <mouli@linux.intel.com>
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-by: H. Peter Anvin <hpa@linux.intel.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2014-03-25 20:25:42 +08:00
David Vrabel 5926f87fda Revert "xen: properly account for _PAGE_NUMA during xen pte translations"
This reverts commit a9c8e4beee.

PTEs in Xen PV guests must contain machine addresses if _PAGE_PRESENT
is set and pseudo-physical addresses is _PAGE_PRESENT is clear.

This is because during a domain save/restore (migration) the page
table entries are "canonicalised" and uncanonicalised". i.e., MFNs are
converted to PFNs during domain save so that on a restore the page
table entries may be rewritten with the new MFNs on the destination.
This canonicalisation is only done for PTEs that are present.

This change resulted in writing PTEs with MFNs if _PAGE_PROTNONE (or
_PAGE_NUMA) was set but _PAGE_PRESENT was clear.  These PTEs would be
migrated as-is which would result in unexpected behaviour in the
destination domain.  Either a) the MFN would be translated to the
wrong PFN/page; b) setting the _PAGE_PRESENT bit would clear the PTE
because the MFN is no longer owned by the domain; or c) the present
bit would not get set.

Symptoms include "Bad page" reports when munmapping after migrating a
domain.

Signed-off-by: David Vrabel <david.vrabel@citrix.com>
Acked-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Cc: <stable@vger.kernel.org>        [3.12+]
2014-03-25 11:11:42 +00:00
Linus Torvalds 822316461b Merge branch 'parisc-3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux
Pull parisc updates from Helge Deller:
 - revert parts of the latest patch regarding font selection with STICON
   console
 - wire up the utimes() syscall for parisc
 - remove the unused parisc tmpalias code and unnecessary arch*relax
   defines

* 'parisc-3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux:
  parisc: locks: remove redundant arch_*_relax operations
  parisc: wire up sys_utimes
  parisc: Remove unused CONFIG_PARISC_TMPALIAS code
  partly revert commit 8a10bc9: parisc/sti_console: prefer Linux fonts over built-in ROM fonts
2014-03-24 17:36:58 -07:00
Linus Torvalds 56f1f4b24e Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc
Pull sparc fixes from David Miller:

 1) Do serial locking in a way that makes things clear that these are
    IRQ spinlocks.

 2) Conversion to generic idle loop broke first generation Niagara
    machines, need to have %pil interrupts enabled during cpu yield
    hypervisor call.

 3) Do not use magic constants for iterations over tsb tables, from Doug
    Wilson.

 4) Fix erroneous truncation of 64-bit system call return values to
    32-bit.  From Dave Kleikamp.

* git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc:
  sparc64: Make sure %pil interrupts are enabled during hypervisor yield.
  sparc64:tsb.c:use array size macro rather than number
  sparc64: don't treat 64-bit syscall return codes as 32-bit
  sparc: serial: Clean up the locking for -rt
2014-03-24 17:30:44 -07:00
Eric W. Biederman fabfb91d50 uml/net_kern: Call dev_consume_skb_any instead of dev_kfree_skb.
Replace dev_kfree_skb with dev_consume_skb_any in uml_net_start_xmit
as it can be called in hard irq and other contexts.

dev_consume_skb_any is used as uml_net_start_xmit typically
consumes (not drops) packets.

Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2014-03-24 15:13:35 -07:00
David S. Miller cb3042d609 sparc64: Make sure %pil interrupts are enabled during hypervisor yield.
In arch_cpu_idle() we must enable %pil based interrupts before
potentially invoking the hypervisor cpu yield call.

As per the Hypervisor API documentation for cpu_yield:

	Interrupts which are blocked by some mechanism other that
	pstate.ie (for example %pil) are not guaranteed to cause
	a return from this service.

It seems that only first generation Niagara chips are hit by this
bug.  My best guess is that later chips implement this in hardware
and wake up anyways from %pil events, whereas in first generation
chips the yield is implemented completely in hypervisor code and
requires %pil to be enabled in order to wake properly from this
call.

Fixes: 87fa05aeb3 ("sparc: Use generic idle loop")
Reported-by: Fabio M. Di Nitto <fabbione@fabbione.net>
Reported-by: Jan Engelhardt <jengelh@inai.de>
Tested-by: Jan Engelhardt <jengelh@inai.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-03-24 14:45:12 -04:00
Kees Cook 9dd721c6db x86, kaslr: fix module lock ordering problem
There was a potential lock ordering problem with the module kASLR patch
("x86, kaslr: randomize module base load address"). This patch removes
the usage of the module_mutex and creates a new mutex to protect the
module base address offset value.

Chain exists of:
  text_mutex --> kprobe_insn_slots.mutex --> module_mutex

[    0.515561]  Possible unsafe locking scenario:
[    0.515561]
[    0.515561]        CPU0                    CPU1
[    0.515561]        ----                    ----
[    0.515561]   lock(module_mutex);
[    0.515561]                                lock(kprobe_insn_slots.mutex);
[    0.515561]                                lock(module_mutex);
[    0.515561]   lock(text_mutex);
[    0.515561]
[    0.515561]  *** DEADLOCK ***

Reported-by: Fengguang Wu <fengguang.wu@intel.com>
Signed-off-by: Andy Honig <ahonig@google.com>
Signed-off-by: Kees Cook <keescook@chromium.org>
Reviewed-by: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2014-03-24 10:18:26 -07:00
Stefani Seibold 645a387ecb x86, vdso: Fix size of get_unmapped_area()
The size of the reserved memory for a 32 bit vdso must be the size of the
32 bit vDSO in pages + HPET page + VVAR page.

One page is not enough for this. Grrrr.... silly copy and paste bug,
was right in previous patch.

Signed-off-by: Stefani Seibold <stefani@seibold.net>
Cc: Andy Lutomirski <luto@amacapital.net>
Link: http://lkml.kernel.org/r/1395592694-20571-1-git-send-email-stefani@seibold.net
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2014-03-24 09:31:23 -07:00
Kuninori Morimoto 6fa387b2ed ARM: bockw: fixup SND_SOC_DAIFMT_CBx_CFx flags
SND_SOC_DAIFMT_CBx_CFx means "codec" side master/slave mode.
Then, rcar will be master mode if it was SND_SOC_DAIFMT_CBS_CFS.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
2014-03-24 10:41:20 +00:00
Catalin Marinas 196adf2f30 arm64: Remove pgprot_dmacoherent()
Since this macro is identical to pgprot_writecombine() and is only used
in a single place, remove it completely to avoid confusion. On ARMv7+
processors, the coherent DMA mapping must be Normal NonCacheable (a.k.a.
writecombine) to avoid mismatched hardware attribute aliases (with the
kernel linear mapping as Normal Cacheable).

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-03-24 10:35:35 +00:00
Laura Abbott 214fdbe74a arm64: Support DMA_ATTR_WRITE_COMBINE
DMA_ATTR_WRITE_COMBINE is currently ignored. Set the pgprot
appropriately for non coherent opperations.

Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-03-24 10:26:10 +00:00
Laura Abbott 6e8d7968e9 arm64: Implement custom mmap functions for dma mapping
The current dma_ops do not specify an mmap function so maping
falls back to the default implementation. There are at least
two issues with using the default implementation:

1) The pgprot is always pgprot_noncached (strongly ordered)
memory even with coherent operations
2) dma_common_mmap calls virt_to_page on the remapped non-coherent
address which leads to invalid memory being mapped.

Fix both these issue by implementing a custom mmap function which
correctly accounts for remapped addresses and sets vm_pg_prot
appropriately.

Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
[catalin.marinas@arm.com: replaced "arm64_" with "__" prefix for consistency]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-03-24 10:01:17 +00:00
Benjamin Herrenschmidt cd42748535 Merge remote-tracking branch 'scott/next' into next
Freescale updates from Scott. Mostly support for critical
and machine check exceptions on 64-bit BookE, some new
PCI suspend/resume work and misc bits.
2014-03-24 10:26:10 +11:00
Mahesh Salgaonkar d410ae2126 powerpc/book3s: Fix CFAR clobbering issue in machine check handler.
While checking powersaving mode in machine check handler at 0x200, we
clobber CFAR register. Fix it by saving and restoring it during beq/bgt.

Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24 10:16:09 +11:00
Anton Blanchard 422b9b9684 powerpc/compat: 32-bit little endian machine name is ppcle, not ppc
I noticed this when testing setarch. No, we don't magically
support a big endian userspace on a little endian kernel.

Signed-off-by: Anton Blanchard <anton@samba.org>
Cc: stable@vger.kernel.org # v3.10+
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24 10:16:04 +11:00
Greg Kurz 599d287042 powerpc/le: Big endian arguments for ppc_rtas()
The ppc_rtas() syscall allows userspace to interact directly with RTAS.
For the moment, it assumes every thing is big endian and returns either
EINVAL or EFAULT when called in a little endian environment.

As suggested by Benjamin, to avoid bugs when userspace wants to pass
a non 32 bit value to RTAS, it is far better to stick with a simple
rationale: ppc_rtas() should be called with a big endian rtas_args
structure.

With this patch, it is now up to userspace to forge big endian arguments,
as expected by RTAS.

Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24 09:48:36 +11:00
Anton Blanchard e45fbae515 powerpc: Use default set of netfilter modules (CONFIG_NETFILTER_ADVANCED=n)
Our netfilter options are stale and important things like masquerading
are no longer enabled. Instead of trying to keep up with any updates,
set CONFIG_NETFILTER_ADVANCED=n on ppc64* and pseries* defconfigs.
This enables the most common netfilter modules for us.

While here, enable the network bridge module which is heavily used in
KVM setups.

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24 09:48:35 +11:00
Aneesh Kumar K.V 1907a2c2c3 powerpc/defconfigs: Enable THP in pseries defconfig
We also set it to be enabled always. This helps in wider testing

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24 09:48:35 +11:00
Aneesh Kumar K.V 346519a160 powerpc/mm: Make sure a local_irq_disable prevent a parallel THP split
We have generic code like the one in get_futex_key that assume that
a local_irq_disable prevents a parallel THP split. Support that by
adding a dummy smp call function after setting _PAGE_SPLITTING. Code
paths like get_user_pages_fast still need to check for _PAGE_SPLITTING
after disabling IRQ which indicate that a parallel THP splitting is
ongoing. Now if they don't find _PAGE_SPLITTING set, then we can be
sure that parallel split will now block in pmdp_splitting flush
until we enables IRQ

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Acked-by: Rik van Riel <riel@redhat.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24 09:48:34 +11:00
Michael Neuling ee4ed6fa5a powerpc: Rate-limit users spamming kernel log buffer
The facility unavailable exception can be triggered from userspace by
accessing PMU registers when EBB is not enabled.  This causes the
included pr_err() to run, hence spamming the kernel log buffer.

This avoids this by rate limiting these messages.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24 09:48:34 +11:00
Michael Ellerman e9aaac1ac3 powerpc/perf: Fix handling of L3 events with bank == 1
Currently we reject events which have the L3 bank == 1, such as
0x000084918F, because the cache field is non-zero.

However that is incorrect, because although the bank is non-zero, the
value we would write into MMCRC is zero, and so we can count the event.

So fix the check to ignore the bank selector when checking whether the
cache selector is non-zero.

Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24 09:48:33 +11:00
Cody P Schafer 30daeb6c8f powerpc/perf: Add kconfig option for hypervisor provided counters
The commit adds a Kconfig option which allows the hv_gpci and hv_24x7
PMUs, added in the preceeding commits, to be built.

Signed-off-by: Cody P Schafer <cody@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24 09:48:32 +11:00
Cody P Schafer 0e93a6edd9 powerpc/perf: Add support for the hv 24x7 interface
This provides a basic interface between hv_24x7 and perf. Similar to
the one provided for gpci, it lacks transaction support and does not
list any events.

Example usage via perf tool:

	perf stat -e 'hv_24x7/domain=2,offset=8,starting_index=0,lpar=0xffffffff/' -r 0 -C 0 -x ' ' sleep 0.1

Signed-off-by: Cody P Schafer <cody@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24 09:48:32 +11:00
Cody P Schafer 220a0c609a powerpc/perf: Add support for the hv gpci (get performance counter info) interface
This provides a basic link between perf and hv_gpci. Notably, it does
not yet support transactions and does not list any events (they can
still be manually composed).

Example usage via perf tool:

	perf stat -e 'hv_gpci/counter_info_version=3,offset=0,length=8,secondary_index=0,starting_index=0xffffffff,request=0x10/' -r 0 -C 0 -x ' ' sleep 0.1

Signed-off-by: Cody P Schafer <cody@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24 09:48:31 +11:00
Cody P Schafer 7b43c67950 powerpc/perf: Add macros for defining event fields & formats
Add two macros which generate functions to extract the relevent bits
from event->attr.config{,1,2}.

EVENT_DEFINE_RANGE() defines an accessor for a range of bits in the
event, as well as a "max" function that gives the maximum value of the
field based on the bit width.

EVENT_DEFINE_RANGE_FORMAT() defines the accessor & max routine and also
a format attribute for use in the PMU's attr_groups.

Signed-off-by: Cody P Schafer <cody@linux.vnet.ibm.com>
[mpe: move to powerpc, ugly but descriptive macro names]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24 09:48:31 +11:00
Cody P Schafer 2d1b21ad7d powerpc/perf: Add a shared interface to get gpci version and capabilities
This exposes a simple way to grab the firmware provided
collect_priveliged, ga, expanded, and lab capability bits. All of these
bits come in from the same gpci request, so we've exposed all of them.

Only the collect_priveliged bit is really used by the hv-gpci/hv-24x7
code, the other bits are simply exposed in sysfs to inform the user.

Signed-off-by: Cody P Schafer <cody@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24 09:48:30 +11:00
Cody P Schafer a8b2c43671 powerpc/perf: Add 24x7 interface headers
24x7 (also called hv_24x7 or H_24X7) is an interface to obtain
performance counters from the hypervisor. These counters do not have a
fixed format/possition and are instead documented in a "24x7 Catalog",
which is provided by the hypervisor (that interface is also documented
paritialy in the included hv-24x7-catalog.h and fully in at
https://raw.githubusercontent.com/jmesmon/catalog-24x7/master/hv-24x7-catalog.h ).

The 24x7 data access is simply a copy operation into a 4 dimentional
array of 64bit counters (from hypervisor to kernel memory). There is no
interupt triggered on overflow, these are completely disjoint from the
typical power pmu.

This method of obtaining performance counters from the hypervisor is
intended to paritialy replace the gpci interface.

Signed-off-by: Cody P Schafer <cody@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24 09:48:29 +11:00
Cody P Schafer a67f144739 powerpc/perf: Add hv_gpci interface header
"H_GetPerformanceCounterInfo" (refered to as hv_gpci or just gpci from
here on) is an interface to retrieve specific performance counters and
other data from the hypervisor. All outputs have a fixed format. This
header only describes the portions of the interface that we plan on
using in linux at this time.

Signed-off-by: Cody P Schafer <cody@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24 09:48:29 +11:00
Cody P Schafer 827f798ac1 powerpc: Add hvcalls for 24x7 and gpci (Get Performance Counter Info)
Signed-off-by: Cody P Schafer <cody@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24 09:48:28 +11:00
Michael Ellerman 76cb8a783a powerpc/perf: Enable BHRB access for EBB events
The previous commit added constraint and register handling to allow
processes using EBB (Event Based Branches) to request access to the BHRB
(Branch History Rolling Buffer).

With that in place we can allow processes using EBB to access the BHRB.
This is achieved by setting BHRBA in MMCR0 when we enable EBB access. We
must also clear BHRBA when we are disabling.

Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24 09:48:27 +11:00
Michael Ellerman ba969237cf powerpc/perf: Add BHRB constraint and IFM MMCRA handling for EBB
We want a way for users of EBB (Event Based Branches) to also access the
BHRB (Branch History Rolling Buffer). EBB does not interoperate with our
existing BHRB support, which is wired into the generic Linux branch
stack sampling support.

To support EBB & BHRB we add three new bits to the event code. The first
bit indicates that the event wants access to the BHRB, and the other two
bits indicate the desired IFM (Instruction Filtering Mode).

We allow multiple events to request access to the BHRB, but they must
agree on the IFM value. Events which are not interested in the BHRB can
also interoperate with events which do.

Finally we program the desired IFM value into MMCRA. Although we do this
for every event, we know that the value will be identical for all events
that request BHRB access.

Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24 09:48:27 +11:00
Michael Ellerman 7cbba63028 powerpc/perf: Avoid mutating event in power8_get_constraint()
We only need to mask the EBB bit out of the event for the check of the
special PMC 5 & 6 events. So use a local to do it just for that code,
rather than changing the event value for the life of the function.

While we're there move the set of mask and value after all the checks.

Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24 09:48:26 +11:00
Michael Ellerman fb568d763f powerpc/perf: Clean up the EBB hash defines a little
Rather than using PERF_EVENT_CONFIG_EBB_SHIFT everywhere, add an
EVENT_EBB_SHIFT like every other event and use that.

Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24 09:48:26 +11:00
Michael Ellerman 58b5fb0049 powerpc/perf: Reject EBB events which specify a sample_type
Although we already block EBB events which request sampling using
sample_period, technically it's possible for an event to set sample_type
but not sample_period.

Nothing terrible will happen if an EBB event does specify sample_type,
but it signals a major confusion on the part of userspace, and so we do
them the favor of rejecting it.

Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24 09:48:25 +11:00
Michael Ellerman c2e37a2626 powerpc/perf: Add lost exception workaround
Some power8 revisions have a hardware bug where we can lose a PMU
exception, this commit adds a workaround to detect the bad condition and
rectify the situation.

See the comment in the commit for a full description.

Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24 09:48:25 +11:00
Michael Ellerman 68f2f0d431 powerpc: Add a cpu feature CPU_FTR_PMAO_BUG
Some power8 revisions have a hardware bug where we can lose a
Performance Monitor (PMU) exception under certain circumstances.

We will be adding a workaround for this case, see the next commit for
details. The observed behaviour is that writing PMAO doesn't cause an
exception as we would expect, hence the name of the feature.

Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24 09:48:24 +11:00
Anshuman Khandual 5f6d0380c6 powerpc/perf: Define perf_event_print_debug() to print PMU register values
Currently the sysrq ShowRegs command does not print any PMU registers as
we have an empty definition for perf_event_print_debug(). This patch
defines perf_event_print_debug() to print various PMU registers.

Example output:

CPU: 0 PMU registers, ppmu = POWER7 n_counters = 6
PMC1:  00000000 PMC2: 00000000 PMC3: 00000000 PMC4: 00000000
PMC5:  00000000 PMC6: 00000000 PMC7: deadbeef PMC8: deadbeef
MMCR0: 0000000080000000 MMCR1: 0000000000000000 MMCRA: 0f00000001000000
SIAR:  0000000000000000 SDAR:  0000000000000000 SIER:  0000000000000000

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
[mpe: Fix 32 bit build and rework formatting for compactness]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24 09:48:23 +11:00
Anshuman Khandual 2f0695232c powerpc/perf: Make some new raw event codes available in sysfs
This patchset adds some missing event list for POWER7 PMU raw
events which are exported through sysfs interface. Also updates
the ABI documentation to add all the sysfs exported raw events.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24 09:48:23 +11:00
Neelesh Gupta 7224adbbb8 powerpc/powernv: Enable fetching of platform sensor data
This patch enables fetching of various platform sensor data through
OPAL and expects a sensor handle from the driver to pass to OPAL.

Signed-off-by: Neelesh Gupta <neelegup@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24 09:48:21 +11:00
Neelesh Gupta 4029cd6654 powerpc/powernv: Enable reading and updating of system parameters
This patch enables reading and updating of system parameters through
OPAL call.

Signed-off-by: Neelesh Gupta <neelegup@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24 09:47:30 +11:00
Neelesh Gupta 8d72482322 powerpc/powernv: Infrastructure to support OPAL async completion
This patch adds support for notifying the clients of their request
completion. Clients request for the token before making OPAL call
and then wait for the response.

This patch uses messaging infrastructure to pull the data to linux
by registering itself for the message type OPAL_MSG_ASYNC_COMP.

Signed-off-by: Neelesh Gupta <neelegup@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24 09:45:22 +11:00
Will Deacon a34fe10750 parisc: locks: remove redundant arch_*_relax operations
Now that the arch_{spin,read,write}_relax macros default to cpu_relax(),
remove the redundant definitions for parisc.

Cc: Helge Deller <deller@gmx.de>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Helge Deller <deller@gmx.de>
2014-03-23 17:01:23 +01:00
Helge Deller e9af8b7aba parisc: wire up sys_utimes
We seem to be nearly the only platform which does not provide the
sys_utimes syscall.  Adding it now makes our life much easier with
userspace applications (like dietlibc and e2fsprogs) since we then
behave like all other platforms too and don't need extra patches which
are hard to get upstream anyway because we are not a mainstream
architecture.

Signed-off-by: Helge Deller <deller@gmx.de>
Cc: stable@vger.kernel.org # v3.13
2014-03-23 16:57:13 +01:00
John David Anglin 4b02a72a26 parisc: Remove unused CONFIG_PARISC_TMPALIAS code
The attached change removes the unused and experimental
CONFIG_PARISC_TMPALIAS code. It doesn't work and I don't believe it will
ever be used.

Signed-off-by: John David Anglin <dave.anglin@bell.net>
Signed-off-by: Helge Deller <deller@gmx.de>
2014-03-23 16:46:30 +01:00
Andrzej Hajda 621c5d6663 ARM: dts: exynos4210-universal: add exynos/fimd node
The patch adds fimd node with display timings for exynos4210-universal device.
It also makes LCD regulators always on. This allow to re-use panel initialized
by boot loader.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2014-03-24 00:36:40 +09:00
Linus Torvalds 084c6c5013 ARM: SoC fixes for 3.14
Only two patches this time, one to fix ethernet probe order on at91 (better
 fix with proper device aliasing will be done for 3.15, this is stop-gap), and
 one update to MAINTAINERS due to Freescale moving their repo to kernel.org.
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Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
 "Only two patches this time, one to fix ethernet probe order on at91
  (better fix with proper device aliasing will be done for 3.15, this is
  stop-gap), and one update to MAINTAINERS due to Freescale moving their
  repo to kernel.org"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: at91: fix network interface ordering for sama5d36
  MAINTAINERS: update IMX kernel git tree
2014-03-22 09:13:13 -07:00
Arnd Bergmann 600a1dfae2 Merge branch 'randconfig-fixes' into next/fixes-non-critical
This is the first batch of a much longer series of bug fixes
found during randconfig testing. This part are all the simple
patches that are applicable for the arm-soc tree, while most
other fixes will likely go through other maintainers.

* randconfig-fixes: (50 commits)
  ARM: tegra: make debug_ll code build for ARMv6
  ARM: sunxi: fix build for THUMB2_KERNEL
  ARM: exynos: add missing include of linux/module.h
  ARM: exynos: fix l2x0 saved regs handling
  ARM: samsung: select CRC32 for SAMSUNG_PM_CHECK
  ARM: samsung: select ATAGS where necessary
  ARM: samsung: fix SAMSUNG_PM_DEBUG Kconfig logic
  ARM: samsung: allow serial driver to be disabled
  ARM: s5pv210: enable IDE support in MACH_TORBRECK
  ARM: s5p64x0: fix building with only one soc type
  ARM: s3c64xx: select power domains only when used
  ARM: s3c64xx: MACH_SMDK6400 needs HSMMC1
  ARM: s3c24xx: osiris dvs needs tps65010
  ARM: s3c24xx: fix gta02 build error
  ARM: s3c24xx: MINI2440 needs I2C for EEPROM_AT24
  ARM: integrator: only select pl01x if TTY is enabled
  ARM: realview: fix sparsemem build
  ARM: footbridge: make screen_info setup conditional
  ARM: footbridge: fix build with PCI disabled
  ARM: footbridge: don't build floppy code for addin mode
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-22 01:10:19 +01:00
Arnd Bergmann 9f3ba4567e ARM: tegra: make debug_ll code build for ARMv6
In a combined ARMv6/v7 kernel, we cannot use the
movt/movw instructions to load an immediate, as they
are not valid on ARMv6.

This changes the file to use an indirect load instead,
as lots of other implementations do.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: linux-tegra@vger.kernel.org
2014-03-22 01:06:58 +01:00
Arnd Bergmann 1146b60004 ARM: sunxi: fix build for THUMB2_KERNEL
Building an SMP kernel for the sunxi platform with THUMB2 instructions
fails with this error at the moment:

headsmp.S:7: Error: Thumb encoding does not support an immediate here -- `msr cpsr_fsxc,#0xd3'

Since the generic secondary_startup function already does
the same thing in a safe way, we can just drop the private
sunxi implementation and jump straight to secondary_startup.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-03-22 01:04:28 +01:00
Arnd Bergmann c7f094d5e8 ARM: mvebu: don't select CONFIG_NEON
CONFIG_NEON is meant to be user-selectable. Turning it on
unconditionally means we can't build a smaller kernel when
we don't need it, and causes build errors if CONFIG_VFP
is not also enabled.

To still have neon enabled however, we need to turn it on
now in multi_v7_defconfig and mvebu_v7_defconfig.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Acked-by: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-03-21 18:31:42 +01:00
Arnd Bergmann 8f881c6736 ARM: hisi: select HAVE_ARM_SCU only for SMP
The SCU code does not build unless we are compiling
an SMP kernel. This does the same as every other
platform with an SCU.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
2014-03-21 18:31:34 +01:00
Arnd Bergmann 886545ea7d ARM: efm32: allow uncompress debug output
efm32 has no mach/uncompress.h, but we can trivially use
the fallback to the ll_debug code by just allowing this
option in Kconfig.

Found during randconfig testing.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Uwe Kleine-König <kernel@pengutronix.de>
2014-03-21 18:31:34 +01:00
Arnd Bergmann 96c3a2506b ARM: exynos: add missing include of linux/module.h
After the restructuring of the module.h and init.h headers,
we now need to include this explicitly here.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Ben Dooks <ben-linux@fluff.org>
2014-03-21 18:26:25 +01:00
Arnd Bergmann 39378e4143 ARM: exynos: fix l2x0 saved regs handling
The exynos4_l2x0_cache_init function tries to flush the data cache
for the location of the saved l2x0 registers and pass the physical
address to the s5p-sleep implementation.

However, the s5p-sleep code is optional, and if it is disabled,
we get a linker error here when the l2x0_regs_phys variable does
not exist.

To solve this, use a compile-time conditional to drop this code
if we don't want it.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Ben Dooks <ben-linux@fluff.org>
2014-03-21 18:26:24 +01:00
Arnd Bergmann 714e330253 ARM: samsung: select CRC32 for SAMSUNG_PM_CHECK
The Samsung pm_check code uses the crc32 library code, which can
be built as a loadable module, in which case we get a link error
building the kernel.

A better solution is to use 'select CRC32', which is what all
other users of this code do, as it ensures it is always built-in.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Ben Dooks <ben-linux@fluff.org>
2014-03-21 18:26:23 +01:00
Arnd Bergmann 335cce74f2 ARM: samsung: select ATAGS where necessary
Most of the Samsung platforms do not yet allow building with
DT at all, so we should select CONFIG_ATAGS for now in all
cases we also select CONFIG_SAMSUNG_ATAGS.

Found during randconfig testing.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Ben Dooks <ben-linux@fluff.org>
2014-03-21 18:26:22 +01:00
Arnd Bergmann af960151ef ARM: samsung: fix SAMSUNG_PM_DEBUG Kconfig logic
The suspend debug code for Samsung has multiple dependencies
that we should not unconditionally enable. In particular,
we rely on the DEBUG_S3C_UART setting, which in turn depends
on the samsung UART driver.

Signed-off-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Ben Dooks <ben-linux@fluff.org>
2014-03-21 18:26:21 +01:00
Arnd Bergmann 0443a65398 ARM: samsung: allow serial driver to be disabled
If CONFIG_SERIAL_SAMSUNG is disabled, we run into build errors
with some samsung platforms. This adds a couple of #ifdef
statements to hopefully deal with this more gracefully.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Ben Dooks <ben-linux@fluff.org>
2014-03-21 18:26:20 +01:00
Arnd Bergmann 943fa72629 ARM: s5pv210: enable IDE support in MACH_TORBRECK
Building MACH_TORBRECK by itself results in a build error
because we try to reference the s3c_device_cfcon definition
that is hidden inside CONFIG_SAMSUNG_DEV_IDE. This changes
the Kconfig logic to ensure that option is enabled when we
need it.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Ben Dooks <ben-linux@fluff.org>
2014-03-21 18:26:19 +01:00
Arnd Bergmann 4f579c0391 ARM: s5p64x0: fix building with only one soc type
The s5p64x0 platform supports two distinct SoCs, s5p6440 and s5p6450,
and in the normal configuration, both are enabled. However if we build
a kernel that only enables one of the two, the #ifdef logic in common.c
breaks down, as some of the functions declared in the header are defined
to NULL using the preprocessor but then defined anyway.

This patch cleans up the mess and ensures that each function has either
exactly one C declaration and one matching C definition, or we have
a NULL defined function pointer but no C definition.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Ben Dooks <ben-linux@fluff.org>
2014-03-21 18:26:18 +01:00
Arnd Bergmann 4ab75a3f3d ARM: s3c64xx: select power domains only when used
The power domain code is only available when CONFIG_PM
is enabled, so we must not select that unconditionally for
s3c64xx. Changing it to 'select PM_GENERIC_DOMAINS if PM'
mirrors what we do on other platforms, and fixes a possible
randconfig build bug.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Ben Dooks <ben-linux@fluff.org>
2014-03-21 18:26:17 +01:00
Arnd Bergmann b25a1b64e1 ARM: s3c64xx: MACH_SMDK6400 needs HSMMC1
This board uses both MMC controllers, so we need to enable
the Kconfig option to define the platform data.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Ben Dooks <ben-linux@fluff.org>
2014-03-21 18:26:16 +01:00
Arnd Bergmann f88309c687 ARM: s3c24xx: osiris dvs needs tps65010
The osiris-dvs driver calls functions exported by the tps65010
driver, so we have to ensure that driver is enabled first.
Using 'select' here doesn't work all that well, because it
requires I2C to be enabled in turn.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-21 18:26:15 +01:00
Arnd Bergmann 645e27b052 ARM: s3c24xx: fix gta02 build error
The gta02 has always been broken in the case when CONFIG_PCF50633_ADC
is not used, since gta02_charger_worker then passes a nonexisting
variable into the pcf50633_mbc_usb_curlim_set() function.

This addresses the obvious typo by using the variable that is
used everywhere else in this file.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Ben Dooks <ben-linux@fluff.org>
2014-03-21 18:26:14 +01:00
Arnd Bergmann 37373f161b ARM: s3c24xx: MINI2440 needs I2C for EEPROM_AT24
If I2C is disabled, we cannot build the AT24 driver, so we
should not select it.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Ben Dooks <ben-linux@fluff.org>
2014-03-21 18:26:13 +01:00
Arnd Bergmann 152c55553e ARM: integrator: only select pl01x if TTY is enabled
Building the integrator platform without TTY support currently
results in a build failure because we always turn on the
pl010 or pl011 drivers. Changing this to a conditional 'select'
statement enables us to build more random configurations, although
it should have little impact for practical configurations.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Linus Walleij <linus.walleij@linaro.org>
2014-03-21 18:26:12 +01:00
Arnd Bergmann dd94d35589 ARM: realview: fix sparsemem build
Commit b713aa0b15 "ARM: fix asm/memory.h build error" broke some
configurations on mach-realview with sparsemem enabled, which
is missing a definition of PHYS_OFFSET:

arch/arm/include/asm/memory.h:268:42: error: 'PHYS_OFFSET' undeclared (first use in this function)
 #define PHYS_PFN_OFFSET ((unsigned long)(PHYS_OFFSET >> PAGE_SHIFT))
arch/arm/include/asm/dma-mapping.h:104:9: note: in expansion of macro 'PHYS_PFN_OFFSET'
  return PHYS_PFN_OFFSET + dma_to_pfn(dev, *dev->dma_mask);

An easy workaround is for realview to define PHYS_OFFSET itself,
in the same way we define it for platforms that don't have a private
__virt_to_phys function.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Linus Walleij <linus.walleij@linaro.org>
2014-03-21 18:26:11 +01:00
Arnd Bergmann 617d1464ab ARM: footbridge: make screen_info setup conditional
The global screen_info structure is used to communicate
data about the console from platform code to the console
driver, but is only defined on ARM if either the VGA or
dummy consoles are in use.

This changes the footbridge code so we don't try to access
this structure in case it is not defined, which prevents
a possible randconfig build error.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Russell King <linux@arm.linux.org.uk>
2014-03-21 18:26:10 +01:00
Arnd Bergmann 570977a1fc ARM: footbridge: fix build with PCI disabled
The dc21285.c source file cannot be built when CONFIG_PCI is
disabled, because it calls a number of PCI core interfaces.

This changes the Makefile so we don't include this file in the
build if CONFIG_PCI is disabled. No other code references anything
defined inside of this file in this case.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Russell King <linux@arm.linux.org.uk>
2014-03-21 18:26:09 +01:00
Arnd Bergmann ad9faf4c4c ARM: footbridge: don't build floppy code for addin mode
The ARCH_EBSA285_ADDIN platform does not provide the
ISA_DMA API, which is required by the floppy driver.

Let's ensure that the floppy code can only be built
when ISA_DMA is also enabled, by moving the select
statement into ARCH_EBSA285_HOST.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Russell King <linux@arm.linux.org.uk>
2014-03-21 18:26:08 +01:00
Arnd Bergmann fa04e209ae ARM: rpc: autoselect CPU_SA110
ARCH_RPC no longer supports other CPUs aside from StrongARM110,
so we can make the option implicitly selected by the platform
and no longer give the option of building a kernel without CPU
support.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Russell King <linux@arm.linux.org.uk>
2014-03-21 18:26:07 +01:00
Arnd Bergmann edd4c7208b ARM: pxa: trizeps4 and trizeps4wl use the same file
The trizeps4 and trizeps4wl platforms are both implemented
using the same board file. Since the trizeps4wl code is a
superset of trizeps4, it makes no sense to enable just the
latter, but with the current Kconfig logic, it causes the
board file not to be built at all.

Selecting MACH_TRIZEPS4 from MACH_TRIZEPS4WL ensures that
we are actually building the board file.

Found during randconfig testing.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Eric Miao <eric.y.miao@gmail.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: Daniel Mack <zonque@gmail.com>
2014-03-21 18:26:06 +01:00
Arnd Bergmann c7dc7d49fa ARM: pxa: select I2C_GPIO only if I2C is on
The Arcom/Eurotech VIPER SBC enables the I2C_GPIO driver, but
that has a dependency on I2C, and causes build failures if I2C
is disabled. To keep existing configurations running while fixing
the randconfig problems, this changes the logic to only enable
I2C_GPIO if I2C is already enabled.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: Eric Miao <eric.y.miao@gmail.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Daniel Mack <zonque@gmail.com>
2014-03-21 18:26:05 +01:00
Arnd Bergmann 419606ec4d ARM: pxa: remove broken balloon3_gpio_vbus reference
balloon3_udc_init() tries to register a balloon3_gpio_vbus
device, but this has never been defined in the mainline
kernel. To avoid the obvious build failure when this function
is enabled, remove the bogus reference here.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Eric Miao <eric.y.miao@gmail.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: Daniel Mack <zonque@gmail.com>
2014-03-21 18:26:04 +01:00
Arnd Bergmann 847e34969d ARM: pxa: fix colibri build
The colibri_ohci_init function performs a register access through
the io_p2v() macro, which requires the IOMEM macro to be defined.

By explicitly including the asm/io.h header file that contains
this macro, we avoid the build error:

arch/arm/mach-pxa/colibri-evalboard.c: In function 'colibri_ohci_init':
arch/arm/mach-pxa/colibri-evalboard.c:68:2: error: implicit declaration of function 'IOMEM' [-Werror=implicit-function-declaration]
  UP2OCR = UP2OCR_HXS | UP2OCR_HXOE | UP2OCR_DPPDE | UP2OCR_DMPDE;

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Eric Miao <eric.y.miao@gmail.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: Daniel Mack <zonque@gmail.com>
2014-03-21 18:26:02 +01:00
Arnd Bergmann e914f19f03 ARM: pxa: enable pxafb unconditionally for some boards
The SAAR and TAVOREVB machines try to call functions from
the PXAFB frame buffer driver from their platform code,
which only works if that driver is built-in.

This patch ensures that both the generic frame buffer
code and the specific pxafb driver are always enabled
when we build a kernel for one of the two boards.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Eric Miao <eric.y.miao@gmail.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: Daniel Mack <zonque@gmail.com>
2014-03-21 18:26:01 +01:00
Arnd Bergmann a0ad0fdb88 ARM: pxa: don't "select" SMC91X on MACH_XCEP
We normally don't hard-enable Kconfig options just because
a board contains a specific piece of hardware. In this case,
selecting SMC91X causes a build error, if we don't also enable
basic network device driver support.

Since the platform has no direct dependency on this driver
at link time, we can just remove the 'select' statement.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Eric Miao <eric.y.miao@gmail.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: Daniel Mack <zonque@gmail.com>
2014-03-21 18:26:00 +01:00
Arnd Bergmann 32ff4971ec ARM: orion5x: make dns323 independent of PHY support
The D-Link DNS-323 machine tries to unconditionally select CONFIG_PHYLIB,
but that has other dependencies that might not necessarily be enabled,
causing random build errors.

To work around this, this patch removes the 'select' statement and
instead uses a compile-time check to skip the phy_register_fixup_for_uid()
call if PHYLIB is not available in the kernel.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-03-21 18:25:59 +01:00
Arnd Bergmann 9e1280419e ARM: mvebu: add missing header
The definition for SIGBUS may not be visible without including
linux/signal.h, as I found during randconfig testing.

Adding an explicit include is certainly the right thing to do.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Acked-by: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-03-21 18:23:35 +01:00
Arnd Bergmann 0b31c53b13 ARM: omap1: don't rely on tps65010
The code for h2 and osk implicitly assumes that the tps65010
driver is built-in, in order to perform the initial regulator
setup.

This is fine for most real uses, but it does get into the way
of build testing with 'make randconfig', since we don't want
platforms to implicitly select device drivers and subsystems
such as I2C.

This patch by contrast changes the board files to not call
into the tps65010 driver when that is not built-in, allowing
us to build all configurations including some that will not
work properly on this hardware.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Tony Lindgren <tony@atomide.com>
2014-03-21 18:23:34 +01:00
Felipe Balbi 84bef11710 ARM: omap1: fix build when !CONFIG_OMAP_32K_TIMER
If CONFIG_OMAP_32K_TIMER isn't enabled, we will
try to use enable_dyn_sleep which wasn't defined
anywhere.

In order to fix the problem, we always define
enable_dyn_sleep as 0 when !CONFIG_OMAP_32K_TIMER.

Signed-off-by: Felipe Balbi <balbi@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-21 18:23:33 +01:00
Arnd Bergmann b25a7912eb ARM: msm: export legacy DMA interfaces
The msm_sdcc MMC driver and the msm_serial_hs uart driver both
use the pre-dmaengine interfaces provided by the MSM platform.

Since these drivers can be loadable modules, we should export
the functions used in the drivers.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: David Brown <davidb@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
2014-03-21 18:23:32 +01:00
Arnd Bergmann d967b0100f ARM: msm: avoid calling debug_ll_addr on !MMU
MSM7X00A has an open-coded version of debug_ll_io_init so it
can use MT_DEVICE_NONSHARED as required by the platform.

However, this fails to build on no-MMU kernels because the
debug_ll_addr function is not available. Since the iotable_init
function doesn't actually do anyting in this configuration,
we can simply get away by enclosing the broken function call
in an #ifdef, which seems to be the least ugly workaround.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: David Brown <davidb@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
2014-03-21 18:23:31 +01:00
Arnd Bergmann 404ed596de ARM: msm: add missing include of linux/module.h
After the restructuring of the module.h and init.h headers,
we now need to include this explicitly here.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: David Brown <davidb@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
2014-03-21 18:23:30 +01:00
Arnd Bergmann 22833d5574 ARM: lpc32xx: export lpc32xx_return_iram_size
This symbol is used by the lpc_eth driver, which may
be a loadable module.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Roland Stigge <stigge@antcom.de>
2014-03-21 18:23:29 +01:00
Arnd Bergmann de94abfa0f ARM: ks8695/og: make PCI setup conditional
The 'og' machine tries to always initialized the PCI code, but that
may be disabled in Kconfig, leading to a build error.

This patch changes the code to use the same Kconfig symbol to decide
about calling the ks8695_init_pci function at build time that we
use to decide about building the ks8695 PCI support.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Greg Ungerer <gerg@uclinux.org>
2014-03-21 18:23:28 +01:00
Arnd Bergmann 48ba81f6fd ARM: ixp4xx: fix gpio rework
Commit 098e30f655 "ARM: ixp4xx: stop broadcasting the custom GPIO API"
changed the internal gpio code of ixp4xx to be accessible only from
common.c, but unfortunately that broke the Goramo MultiLink code, which
uses this API.

This tries to restore the previous state without exposing the
API globally again. A better solution might be needed.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Krzysztof Halasa <khc@pm.waw.pl>
Cc: Imre Kaloz <kaloz@openwrt.org>
2014-03-21 18:23:27 +01:00
Arnd Bergmann 926aabde63 ARM: ixp4xx: avoid use of PCIBIOS_MIN_MEM in io.h
When using CONFIG_IXP4XX_INDIRECT_PCI, we run into a recursive
header file dependency between mach/io.h and asm/pci.h, resulting
in a build failure:

mach-ixp4xx/include/mach/io.h: In function 'is_pci_memory':
mach-ixp4xx/include/mach/io.h:53:18: error: 'PCIBIOS_MIN_MEM' undeclared (first use in this function)
  return (addr >= PCIBIOS_MIN_MEM) && (addr <= 0x4FFFFFFF);
                  ^
mach-ixp4xx/include/mach/io.h:53:18: note: each undeclared identifier is reported only once for each function it appears in

We can work around this by referencing the pcibios_min_mem variable
directly through an extern declaration, rather than using the macro.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Imre Kaloz <kaloz@openwrt.org>
Cc: Krzysztof Halasa <khc@pm.waw.pl>
2014-03-21 18:23:26 +01:00
Arnd Bergmann e9c610a49b ARM: ixp4xx/omixp: always include linux/leds.h
The omixp board code unconditionally defines a gpio-led
device, but for some reason includes the header file
for this only if CONFIG_LEDS_CLASS is enabled, causing
a build error otherwise.

Removing the #ifdef fixes the build error with no downsides
whatsoever.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Imre Kaloz <kaloz@openwrt.org>
Cc: Krzysztof Halasa <khc@pm.waw.pl>
2014-03-21 18:23:25 +01:00
Arnd Bergmann 1d858f3177 ARM: hisi: fix building without CONFIG_HOTPLUG_CPU
The hisi SMP code always uses the hi3xxx_set_cpu() function
defined in the hotplug.c file, so we cannot build without
this when CONFIG_SMP is enabled. This patch slightly restructures
the code so we always build the parts of hotplug.c that we need
but just leave out the CPU disable logic if CONFIG_HOTPLUG_CPU
is turned off.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
2014-03-21 18:22:09 +01:00
Arnd Bergmann 67e108c530 ARM: ep93xx: export ep93xx_chip_revision
ep93xx_chip_revision is used by the pata_ep93xx driver,
which can be a loadable module. Exporting the symbol
avoids a link error in this case.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Hartley Sweeten <hsweeten@visionengravers.com>
Cc: Ryan Mallon <rmallon@gmail.com>
2014-03-21 18:22:08 +01:00
Arnd Bergmann 1df13d9d0f ARM: efm32: select AUTO_ZRELADDR
The efm32 platform does not provide a zreladdr-y line its Makefile.boot,
so we always have to use CONFIG_AUTO_ZRELADDR in order to successfully
build and link a zImage.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Uwe Kleine-König <kernel@pengutronix.de>
2014-03-21 18:22:07 +01:00
Arnd Bergmann 06f07c9ec7 ARM: davinci: fix Kconfig for DA850_EVM
The DAVINCI_DA850_EVM board uses an unusual method to
enable the GPIO_PCA953X and KEYBOARD_GPIO_POLLED symbols,
which leads to the dependencies on these symbols being
ignored. As GPIO_PCA953X actually requires I2C, that
can lead to build failures when I2C is disabled.

This patch removes the duplicate symbol definitions
and instead enables them from the davinci_all_defconfig
file.

A different question whether we actually want to automatically
enable them at all or rather put them into defconfig,
but that should be a separate patch.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Sekhar Nori <nsekhar@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: davinci-linux-open-source@linux.davincidsp.com
2014-03-21 18:19:33 +01:00