Граф коммитов

89 Коммитов

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Geert Uytterhoeven 43a51cd5d6 pinctrl: sh-pfc: Add SH_PFC_PIN_GROUP_ALIAS()
Add a macro to refer to another pin group with a different name.

This will be used to rename wrongly-named pin groups, while retaining
backwards compatibility with old DTBs.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2018-03-21 18:18:05 +01:00
Sergei Shtylyov f59125248a pinctrl: sh-pfc: Add R8A77980 PFC support
Add the PFC support for the R8A77980 SoC including pin groups for some
on-chip devices such as AVB, CAN-FD, GETHER, [H]SCIF, I2C, INTC-EX, MMC,
MSIOF, PWM, and VIN...

Based on the original (and large) patch by Vladimir Barinov.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-03-09 13:55:30 +01:00
Sergei Shtylyov c21a3e30e8 pinctrl: sh-pfc: Add PORT_GP_CFG_25() helper macro
They follow the style of the existing PORT_GP_CFG_<n>() macros and
will be used by a follow-up patch for the R8A77980 SoC.

Based on the original (and large) patch by Vladimir Barinov.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-03-09 13:55:26 +01:00
Jacopo Mondi 490e687eb8 pinctrl: sh-pfc: Initial R-Car M3-N support
Add initial PFC support for R-Car M3-N (r8a77965) SoC.
No groups or functions defined, just pin and registers enumeration.

Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-20 19:32:58 +01:00
Sergei Shtylyov b92ac66a18 pinctrl: sh-pfc: Add R8A77970 PFC support
Add the PFC support for the R8A77970 SoC including pin groups for some
on-chip devices such as CAN-FD, [H]SCIF, I2C, INTC-EX, MMC, MSIOF, PWM,
VIN...

Based on the original (and large) patch by Daisuke Matsushita
<daisuke.matsushita.ns@hitachi.com>.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Rob Herring <robh@kernel.org>
[geert: Drop EtherAVB for now]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-12-05 14:14:39 +01:00
Sergei Shtylyov 5a0e698876 pinctrl: sh-pfc: Add PORT_GP_CFG_{6|22}() helper macros
They follow the style of the existing PORT_GP_CFG_<n>() macros and
will be used by a follow-up  patch for the R8A77970 SoC.

Based on the original (and large) patch by Daisuke Matsushita
<daisuke.matsushita.ns@hitachi.com>.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-11-28 10:43:12 +01:00
Geert Uytterhoeven 8843797df3 pinctrl: sh-pfc: Save/restore registers for PSCI system suspend
During PSCI system suspend, R-Car Gen3 SoCs are powered down, and their
pinctrl register state is lost.  Note that as the boot loader skips most
initialization after system resume, pinctrl register state differs from
the state encountered during normal system boot, too.

To fix this, save all GPIO and peripheral function select, module
select, drive strength control, bias, and other I/O control registers
during system suspend, and restore them during system resume.

Note that to avoid overhead on platforms not needing it, the
suspend/resume code has a build time dependency on sleep and PSCI
support, and a runtime dependency on PSCI.

Inspired by a patch in the BSP by Hien Dang.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-10-20 11:37:43 +02:00
Geert Uytterhoeven 9e9bd06a35 pinctrl: sh-pfc: Add generic IOCTRL register description
Add a generic way to describe IOCTRL registers (for e.g. SD I/O voltage
and time delay control), like is already done for config, drive, and
bias registers.

This makes the sh-pfc core code aware of these registers, which will
ease introducing suspend/resume support later.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-10-20 11:37:21 +02:00
Geert Uytterhoeven 1860bb134f pinctrl: sh-pfc: Remove obsolete sh_pfc_pin_to_bias_info()
All users of sh_pfc_pin_to_bias_info() and the related data structures
have been converted to sh_pfc_pin_to_bias_reg(), so those can be
removed.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2017-10-20 11:37:19 +02:00
Geert Uytterhoeven beaa34d908 pinctrl: sh-pfc: Add generic bias register description
Add a generic way to describe bias registers (for pull-up/down control),
like is already done for config and drive registers.

This makes the sh-pfc core code aware of these registers, which will
ease introducing suspend/resume support later.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2017-10-20 11:37:00 +02:00
Takeshi Kihara 794a671176 pinctrl: sh-pfc: Initial R8A77995 PFC support
This patch adds initial pinctrl driver to support for the R8A77995 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
[geert: whitespace]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-08-16 14:26:30 +02:00
Yoshihiro Shimoda afdf04c151 pinctrl: sh-pfc: Add PORT_GP_{10,2[01]} helper macros
This follows the style of existion PORT_GP_X macros and
will be used by a follow-up patch for the r8a77995 SoC.

Extracted from the initial r8a77995 patch in the BSP by Takeshi Kihara.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-08-16 14:26:30 +02:00
Sergei Shtylyov c8bac70f07 pinctrl: sh-pfc: r8a7794: Add R8A7745 support
Renesas RZ/G1E (R8A7745) is pin compatible with R-Car E2 (R8A7794),
however it doesn't have several automotive specific peripherals.
Annotate all the items that only exist on the R-Car SoCs...

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Rob Herring <robh@kernel.org>
[geert: Drop annotations, as they are implied by pin groups/functions]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-16 13:53:15 +02:00
Sergei Shtylyov 8df6270149 pinctrl: sh-pfc: r8a7791: Add R8A7743 support
Renesas RZ/G1M (R8A7743) is pin compatible with R-Car M2-W/N (R8A7791/3),
however it doesn't have several automotive specific peripherals.  Annotate
all the items that only exist on the R-Car SoCs and only supply the pin
groups/functions existing on a given SoC...

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Rob Herring <robh@kernel.org>
[geert: Drop annotations, as they are implied by pin groups/functions]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-16 13:45:28 +02:00
Geert Uytterhoeven b205914c8f pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0
The Pin Function Controller module in the R-Car H3 ES2.0 differs from
ES1.x in many ways.

The goal is twofold:
  1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
     for now,
  2. Make it clear which code supports ES1.x, so it can easily be
     identified and removed later, when production SoCs are deemed
     ubiquitous.

Hence this patch:
  1. Extracts the support for R-Car H3 ES1.x into a separate file, as
     the differences are quite large,
  2. Adds code for detecting the SoC revision at runtime using the new
     soc_device_match() API, and selecting pinctrl tables for the actual
     SoC revision,
  3. Replaces the core register and bitfield definitions by their
     counterparts for R-Car H3 ES2.0.

The addition of pins, groups, and functions for the various on-chip
devices is left to subsequent patches.

The R-Car H3 ES2.0 register and bitfield definitions were extracted from
a patch in the BSP by Takeshi Kihara.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>
2017-03-30 13:43:45 +02:00
Niklas Söderlund 1ce56aea7c pinctrl: sh-pfc: Support named pins with custom configuration
Pins not associated with a GPIO port can still have other configuration
parameters. Add a new macro SH_PFC_PIN_NAMED_CFG which allows for named
pins to be declared with a set of configurations. The new macro is an
modification of SH_PFC_PIN_NAMED to allow for optional configuration to
be assigned.

The flag SH_PFC_PIN_CFG_NO_GPIO is still enforced as this should only be
used to define pins not associated with a GPIO port.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-16 10:29:12 +01:00
Niklas Söderlund c314c9f15a pinctrl: sh-pfc: Add helper to handle bias lookup table
On some SoC there are no simple mapping of pins to bias register bits
and a lookup table is needed. This logic is already implemented in some
SoC specific drivers that could benefit from a generic implementation.

Add helpers to deal with the lookup which later can be used by the SoC
specific drivers. The logic used to lookup are different from the one it
aims to replace, this is intentional. This new method reduces the memory
consumption at the cost of increased CPU usage and fix a bug where a
WARN() would incorrectly be triggered if the register offset is 0.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-15 11:01:09 +01:00
Simon Horman 9a6caa13f8 pinctrl: sh-pfc: Add PORT_GP_24 helper macro
This follows the style of existing PORT_GP_X macros and
will be used by a follow-up patch for the r8a7791 SoC.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-14 09:26:35 +02:00
Takeshi Kihara f9aece7344 pinctrl: sh-pfc: Initial R8A7796 PFC support
This patch adds initial pinctrl driver to support for the R8A7796 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[uli: rebased on top of renesas-drivers]
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-08-19 09:37:11 +02:00
Sergei Shtylyov 2cf59e0c20 pinctrl: sh-pfc: Add R8A7792 PFC support
Add the PFC support for the R8A7792 SoC including pin groups for some
on-chip devices such as SCIF, INTC, and LBSC...

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
[geert: s/LSBC/LBSC/]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-08-08 12:33:38 +02:00
Sergei Shtylyov e729bbc19e pinctrl: sh-pfc: Fix overly long lines
The PORT_GP_CFG_<n>() macros take up more than 80 columns -- and not for
a good reason. Make the header file checkpatch.pl-proof at least in this
respect...

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-08-08 12:00:18 +02:00
Geert Uytterhoeven c29e2f2cb6 pinctrl: sh-pfc: Convert to devm_gpiochip_add_data()
This allows to remove the .remove() callback, and all functions and data
it needed for its own bookkeeping.

Suggested-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-21 09:24:58 +02:00
Geert Uytterhoeven 07d36d2908 pinctrl: sh-pfc: Improve core and user API separation
The Renesas Pin Function Controller uses two header files:
  - sh_pfc.h, for use by both core code and SoC-specific drivers,
  - core.h, for internal use by the core code only.

Several SoC-specific drivers include core.h, as they need the sh_pfc
structure, which is passed explicitly to the various SoC-specific
callbacks, and used there.

Hence move its definition from core.h to sh_pfc.h, and remove the
inclusion of core.h from all SoC-specific files.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-21 09:24:55 +02:00
Geert Uytterhoeven 9f4ca14e16 pinctrl: sh-pfc: Move SoC-specific forward declarations to sh_pfc.h
With C=1:

    drivers/pinctrl/sh-pfc/pfc-emev2.c:1695:30: warning: symbol 'emev2_pinmux_info' was not declared. Should it be static?
    drivers/pinctrl/sh-pfc/pfc-r8a7779.c:3888:30: warning: symbol 'r8a7779_pinmux_info' was not declared. Should it be static?

Note that there are more warnings on SH.

The sh_pfc_soc_info structure is defined in sh_pfc.h, while all forward
declarations for the SoC-specific versions are in core.h.
Move the forward declarations from core.h to sh_pfc.h to fix this.

Reported-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-21 09:24:39 +02:00
Wolfram Sang 8775306dcf pinctrl: sh-pfc: refactor voltage setting
All known hardware being able to switch voltages has the same POCCTRL
register. So, factor out the common code to the core and keep only
the pin-to-bit mapping SoC specific. Convert the only user, r8a7790.
In case POCCTRL should ever get more complex (more voltages to select?),
we should probably switch over to a describing array like drive strength
does currently.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-06-10 09:00:19 +02:00
Laurent Pinchart 3caa7d8c3f pinctrl: sh-pfc: Add drive strength support
Add support for the drive-strengh pin configuration using the generic
pinconf DT bindings.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-03-29 09:23:01 +02:00
Kuninori Morimoto 93d2185dca pinctrl: sh-pfc: IPSRx and MOD_SELx should be set before GPSRx
Gen2 / Gen3 datasheet will have below note in next version.
This patch follows this note.

IPSRx and MOD_SELx registers shall be set before setting GPSRx
registers in case that they need to be configured.
MOD_SELx registers can be set either earlier or later than setting
IPSRx registers.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-03-29 09:23:01 +02:00
Geert Uytterhoeven e01678e35f pinctrl: sh-pfc: Rename PINMUX_IPSR_DATA() to PINMUX_IPSR_GPSR()
This macro describes a pinmux configuration that needs configuration in
both a Peripheral Function Select Register (IPSR) and in a
GPIO/Peripheral Function Select Register 1 (GPSR). Reflect that in the
macro name for clarity.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2016-02-08 16:50:08 +01:00
Geert Uytterhoeven cbc983f85c pinctrl: sh-pfc: Improve pinmux macros documentation
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2016-02-08 16:47:27 +01:00
Kuninori Morimoto 2d24fe675a pinctrl: sh-pfc: Share/reuse same PORT_GP_x() macros
Many SoC needs each PORT_GP_x() macros, but we can share/reuse
same one.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2015-11-30 13:41:35 +01:00
Geert Uytterhoeven dcd803bebc pinctrl: sh-pfc: Add PINMUX_SINGLE()
Add a macro to describe a pinmux configuration for a single-function
pin.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2015-11-30 13:41:31 +01:00
Geert Uytterhoeven 69af775a18 pinctrl: sh-pfc: Stop including <linux/platform_data/gpio-rcar.h>
This header file will be removed soon.

Copy the helper macro RCAR_GP_PIN(), which is used by the pinctrl
drivers only, to sh_pfc.h, and drop the #include.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-20 16:03:40 +02:00
Geert Uytterhoeven b8b47d678a pinctrl: sh-pfc: Rename .gpio_data[] to .pinmux_data[]
The sh_pfc_soc_info.gpio_data[] array contains not only GPIO data, but
also various other pinmux-related data (functions and marks).
Every single driver already calls its local array pinmux_data[].
Hence rename the sh_pfc_soc_info member to "pinmux_data".

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2015-10-20 16:03:30 +02:00
Ulrich Hecht 22768fc60a pinctrl: sh-pfc: Add macros defining GP ports with config flags
PORT_GP_CFG_1 and PORT_GP_CFG_32 work like their non-CFG counterparts
but accept an extra argument with config flags.

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2015-10-20 16:03:26 +02:00
Sergei Shtylyov 423caa5253 pinctrl: sh-pfc: r8a779[01]: Move 'union vin_data' to shared header file
R8A7790/1 PFC  drivers use almost identical  'union vin_data' and completely
identical VIN_DATA_PIN_GROUP() macro; we thus can  move them into the shared
header file...

Suggested-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2015-10-20 16:03:10 +02:00
Kuninori Morimoto 5451d09259 pinctrl: sh-pfc: remove unused PINMUX_IPSR_MODSEL_DATA()
Now, all PINMUX_IPSR_MODSEL_DATA() are replased to PINMUX_IPSR_MSEL()
Let's remove unused PINMUX_IPSR_MODSEL_DATA()

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2015-10-02 09:54:38 +02:00
Kuninori Morimoto 2b67bccb47 pinctrl: sh-pfc: modify PINMUX_IPSR_MSEL() macro order
The difference between PINMUX_IPSR_MSEL() and PINMUX_IPSR_MODSEL_DATA()
are FN_xxx order, and PINMUX_IPSR_MSEL() is used only from r8a7778.
Now it r8a7778 works correctly with PINMUX_IPSR_MODSEL_DATA() order.
This means we can merge PINMUX_IPSR_MSEL() and PINMUX_IPSR_MODSEL_DATA().

Current PFC driver is very difficult to read, because macro names are
using different length. Especially PINMUX_IPSR_MODSEL_DATA() is well
used macro

	PINMUX_IPSR_NOGP(ispr, ...)
	PINMUX_IPSR_DATA(ipsr, ...)
	PINMUX_IPSR_NOGM(ispr, ...)
	PINMUX_IPSR_NOFN(ipsr, ...)
	PINMUX_IPSR_MSEL(ipsr, ...)
	PINMUX_IPSR_MODSEL_DATA(ipsr, ...)

It can be readable if we can merge
PINMUX_IPSR_MSEL() and PINMUX_IPSR_MODSEL_DATA()

	PINMUX_IPSR_NOGP(ispr, ...)
	PINMUX_IPSR_DATA(ipsr, ...)
	PINMUX_IPSR_NOGM(ispr, ...)
	PINMUX_IPSR_NOFN(ipsr, ...)
	PINMUX_IPSR_MSEL(ipsr, ...)

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2015-10-02 09:54:35 +02:00
Laurent Pinchart 4adeabd042 pinctrl: sh-pfc: Remove hardcoded IRQ numbers
Now that all ARM-based Renesas SoCs use multiplatform kernels only the
hardcoded IRQ numbers can be dropped as they're dynamically allocated.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2015-10-02 09:54:35 +02:00
Geert Uytterhoeven 56f891b46d pinctrl: sh-pfc: Confine legacy function GPIOs to SH
Legacy function GPIOs are no longer used on ARM since commit
a27c5cd1a0 ("sh-pfc: sh73a0: Remove function GPIOs").
Extract its setup code into a separate function, and make all function
GPIO related code and data depend on CONFIG_SUPERH.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2015-10-02 09:54:33 +02:00
Linus Torvalds 88a99886c2 This is the bulk of pin control changes for the v4.3 development
cycle
 
 Core changes:
 
 - It is possible configure groups in debugfs.
 
 - Consolidation of chained IRQ handler install/remove replacing
   all call sites where irq_set_handler_data() and
   irq_set_chained_handler() were done in succession with a
   combined call to irq_set_chained_handler_and_data(). This
   series was created by Thomas Gleixner after the problem was
   observed by Russell King.
 
 - Tglx also made another series of patches switching
   __irq_set_handler_locked() for irq_set_handler_locked() which
   is way cleaner.
 
 - Tglx also wrote a good bunch of patches to make use of
   irq_desc_get_xxx() accessors and avoid looking up irq_descs
   from IRQ numbers. The goal is to get rid of the irq number
   from the handlers in the IRQ flow which is nice.
 
 Driver feature enhancements:
 
 - Power management support for the SiRF SoC Atlas 7.
 
 - Power down support for the Qualcomm driver.
 
 - Intel Cherryview and Baytrail: switch drivers to use raw
   spinlocks in IRQ handlers to play nice with the realtime
   patch set.
 
 - Rework and new modes handling for Qualcomm SPMI-MPP.
 
 - Pinconf power source config for SH PFC.
 
 New drivers and subdrivers:
 
 - A new driver for Conexant Digicolor CX92755.
 
 - A new driver for UniPhier PH1-LD4, PH1-Pro4, PH1-sLD8,
   PH1-Pro5, ProXtream2 and PH1-LD6b SoC pin control support.
 
 - Reverse-egineered the S/PDIF settings for the Allwinner
   sun4i driver.
 
 - Support for Qualcomm Technologies QDF2xxx ARM64 SoCs
 
 - A new Freescale i.mx6ul subdriver.
 
 Cleanup:
 
 - Remove platform data support in a number of SH PFC
   subdrivers.
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Merge tag 'pinctrl-v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v4.3 development
  cycle.

  Like with GPIO it's a lot of stuff.  If my subsystems are any sign of
  the overall tempo of the kernel v4.3 will be a gigantic diff.

[ It looks like 4.3 is calmer than 4.2 in most other subsystems, but
  we'll see - Linus ]

  Core changes:

   - It is possible configure groups in debugfs.

   - Consolidation of chained IRQ handler install/remove replacing all
     call sites where irq_set_handler_data() and
     irq_set_chained_handler() were done in succession with a combined
     call to irq_set_chained_handler_and_data().  This series was
     created by Thomas Gleixner after the problem was observed by
     Russell King.

   - Tglx also made another series of patches switching
     __irq_set_handler_locked() for irq_set_handler_locked() which is
     way cleaner.

   - Tglx also wrote a good bunch of patches to make use of
     irq_desc_get_xxx() accessors and avoid looking up irq_descs from
     IRQ numbers.  The goal is to get rid of the irq number from the
     handlers in the IRQ flow which is nice.

  Driver feature enhancements:

   - Power management support for the SiRF SoC Atlas 7.

   - Power down support for the Qualcomm driver.

   - Intel Cherryview and Baytrail: switch drivers to use raw spinlocks
     in IRQ handlers to play nice with the realtime patch set.

   - Rework and new modes handling for Qualcomm SPMI-MPP.

   - Pinconf power source config for SH PFC.

  New drivers and subdrivers:

   - A new driver for Conexant Digicolor CX92755.

   - A new driver for UniPhier PH1-LD4, PH1-Pro4, PH1-sLD8, PH1-Pro5,
     ProXtream2 and PH1-LD6b SoC pin control support.

   - Reverse-egineered the S/PDIF settings for the Allwinner sun4i
     driver.

   - Support for Qualcomm Technologies QDF2xxx ARM64 SoCs

   - A new Freescale i.mx6ul subdriver.

  Cleanup:

   - Remove platform data support in a number of SH PFC subdrivers"

* tag 'pinctrl-v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (95 commits)
  pinctrl: at91: fix null pointer dereference
  pinctrl: mediatek: Implement wake handler and suspend resume
  pinctrl: mediatek: Fix multiple registration issue.
  pinctrl: sh-pfc: r8a7794: add USB pin groups
  pinctrl: at91: Use generic irq_{request,release}_resources()
  pinctrl: cherryview: Use raw_spinlock for locking
  pinctrl: baytrail: Use raw_spinlock for locking
  pinctrl: imx6ul: Remove .owner field
  pinctrl: zynq: Fix typos in smc0_nand_grp and smc0_nor_grp
  pinctrl: sh-pfc: Implement pinconf power-source param for voltage switching
  clk: rockchip: add pclk_pd_pmu to the list of rk3288 critical clocks
  pinctrl: sun4i: add spdif to pin description.
  pinctrl: atlas7: clear ugly branch statements for pull and drivestrength
  pinctrl: baytrail: Serialize all register access
  pinctrl: baytrail: Drop FSF mailing address
  pinctrl: rockchip: only enable gpio clock when it setting
  pinctrl/mediatek: fix spelling mistake in dev_err error message
  pinctrl: cherryview: Serialize all register access
  pinctrl: UniPhier: PH1-Pro5: add I2C ch6 pin-mux setting
  pinctrl: nomadik: reflect current input value
  ...
2015-09-04 10:22:09 -07:00
Ben Hutchings 5b9eaa5659 pinctrl: sh-pfc: Implement pinconf power-source param for voltage switching
The pfc in the R8A7790 (and probably others in the R-Car gen 2 family)
supports switching SDHI signals between 3.3V and 1.8V nominal voltage,
and the SD driver should do that when switching to and from UHS modes.

Add a flag for pins that have configurable I/O voltage and SoC
operations to get and set the nominal voltage.  Implement the pinconf
power-source parameter using these operations.

Signed-off-by: Ben Hutchings <ben.hutchings@codethink.co.uk>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-08-24 10:44:54 +02:00
Sergei Shtylyov 61bb3aef92 sh-pfc: fix sparse GPIOs for R-Car SoCs
The PFC driver causes the kernel to hang on the R-Car gen2 SoC based  boards
when the CPU_ALL_PORT() macro is fixed to reflect the reality, i.e. when the
GPIO space becomes actually sparse.  This happens because the _GP_GPIO() macro
includes  an indexed initializer which causes the "holes" (array entries filled
with all 0s) between the groups  of the existing GPIOs; and the driver can't
cope with that.  There seems to  be no reason to use the indexed initializer,
so we can remove the index specifier and so avoid the "holes".

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-07-20 11:01:52 +02:00
Geert Uytterhoeven 1f34de05e7 pinctrl: sh-pfc: Use u32 to store register addresses
Currently all PFC registers lie in low 32-bit address space. Hence use
u32 instead of unsigned long to store PFC register addresses in pinctrl
tables.  All calculations of virtual addresses use a phys_addr_t
intermediate, so we know where to add an offset if the 32-bit assumption
ever becomes false.

While this doesn't impact 32-bit builds, it would save ca. 7 KiB on a
64-bit shmobile_defconfig kernel.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:15:40 +01:00
Geert Uytterhoeven dc70071550 pinctrl: sh-pfc: Store register/field widths in u8 instead of unsigned long
Register and field widths are in the range 1..32. Storing them in the
pinctrl data in (arrays of) unsigned long wastes space.

This decreases the size of a (32-bit) shmobile_defconfig kernel
supporting 7 SoCs by 26460 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:12:47 +01:00
Geert Uytterhoeven 05c5f265c6 pinctrl: sh-pfc: Do not overwrite bias configuration
After the last user of the in_pd/in_pu bias parameters of the _PCRH()
macro was removed in commit 80da8e02d2 ("sh-pfc: r8a7740: Add bias
(pull-up/down) pinconf support"), bias parameters are supposed to be
configured using the generic pinctl mechanism, which calls the
.set_bias() method.

However, the PORTCR() macro still represents the control register as
consisting of two 4-bit fields. Hence the bias configuration in the
uppermost 2 bits is always overwritten with zeroes when a pin is
configured for GPIO, disabling any previously configured bias.

Use the variable config register macro instead, to represent the
register as having 4 fields, and to make sure only the input/output
control and function fields are touched.

This affects R-Mobile APE6 (r8a73a4), R-Mobile A1 (r8a7740), SH-Mobile
AP4 (sh7372), and SH-Mobile AG5 (sh73a0).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09 18:10:56 +01:00
Niklas Söderlund 4c9e473541 sh-pfc: add macro to define pinmux without function
Used to define pinmux configurations where the pinmux function have no
representation in the configuration registers but instead solely depends
on a group selection.

Signed-off-by: Niklas Söderlund <niso@kth.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-27 08:47:53 +01:00
Laurent Pinchart 0a332c96c2 pinctrl: sh-pfc: sh73a0: Remove unnecessary SoC data allocation
The SoC data structure allocated at init time only holds a regulator
pointer that is only used in the init function. Replace it with a local
variable and get rid of the SoC data structure allocation altogether.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-09-23 17:11:22 +02:00
Laurent Pinchart 0e26e8dfb9 pinctrl: sh-pfc: Don't set the pinmux_irq irq field for multiplatform
In the multiplatform kernel case the IRQs associated with the PFC GPIOs
are specified through DT. The pinmux_irq irq field is thus ignored by
the code, and doesn't need to be set.

This will allow removing the mach/irq.h include from pfc-*.c files that
was required for the irq_pin() macro used to initialize the irq field.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:01:51 +02:00
Linus Torvalds a547df99aa Bulk pin control changes for the v3.14 cycle:
- New driver for the Qualcomm TLMM pin controller and its
   msm8x74 subdriver.
 
 - New driver for the Broadcom Capri BCM281xx SoC.
 
 - New subdriver for the imx25 pin controller.
 
 - New subdriver for the Tegra124 pin controller.
 
 - Lock GPIO lines as IRQs for select combined pin control and
   GPIO drivers for baytrail and sirf.
 
 - Some semi-big refactorings and extenstions to the sirf
   driver.
 
 - Lots of patching, cleanup and fixing in the Renesas "PFC"
   driver and associated subdrivers as usual. It is settling
   down a little bit now it seems.
 
 - Minor fixes and incremental updates here and there as usual.
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Merge tag 'pinctrl-v3.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull bulk pin control changes from Linus Walleij:
 "This has been queued and tested for a while.  Lots of action here,
  like in the GPIO tree, embedded stuff like this is really hot now it
  seems.  Details in the signed tag.  I'm especially happy about the
  Qualcomm driver as it is used in such a huge subset of mobile handsets
  out there, and these platforms in general need better upstream support

   - New driver for the Qualcomm TLMM pin controller and its msm8x74
     subdriver.

   - New driver for the Broadcom Capri BCM281xx SoC.

   - New subdriver for the imx25 pin controller.

   - New subdriver for the Tegra124 pin controller.

   - Lock GPIO lines as IRQs for select combined pin control and GPIO
     drivers for baytrail and sirf.

   - Some semi-big refactorings and extenstions to the sirf driver.

   - Lots of patching, cleanup and fixing in the Renesas "PFC" driver
     and associated subdrivers as usual.  It is settling down a little
     bit now it seems.

   - Minor fixes and incremental updates here and there as usual"

* tag 'pinctrl-v3.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits)
  pinctrl: sunxi: Honor GPIO output initial vaules
  pinctrl: capri: add dependency on OF
  ARM: bcm11351: Enable pinctrl for Broadcom Capri SoCs
  ARM: pinctrl: Add Broadcom Capri pinctrl driver
  pinctrl: Add pinctrl binding for Broadcom Capri SoCs
  pinctrl: Add void * to pinctrl_pin_desc
  pinctrl: st: Fix a typo in probe
  pinctrl: Fix some typos and grammar issues in the documentation
  pinctrl: sirf: lock IRQs when starting them
  pinctrl: sirf: put gpio interrupt pin into input status automatically
  pinctrl: sirf: use only one irq_domain for the whole device node
  pinctrl: single: fix infinite loop caused by bad mask
  pinctrl: single: fix pcs_disable with bits_per_mux
  pinctrl: single: fix DT bindings documentation
  pinctrl: as3722: Set pin to output mode for some function
  pinctrl: sirf: add pin group for USP0 with only RX or TX frame sync
  pinctrl: sirf: fix the pins of sdmmc5 connected with TriG
  pinctrl: sirf: add lost usp1_uart_nostreamctrl group for atlas6
  pinctrl: sunxi: Add Allwinner A20 clock output pin functions
  pinctrl/lantiq: fix typo
  ...
2014-01-21 10:14:10 -08:00
Laurent Pinchart 6d5bddd525 pinctrl: sh-pfc: Constify IRQ GPIOs arrays
The arrays are never modified, make them const.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-20 12:26:54 +01:00