Граф коммитов

11 Коммитов

Автор SHA1 Сообщение Дата
David Daney 1b362e3e35 MIPS: Decode c0_config4 for large TLBs.
For processors that have more than 64 TLBs, we need to decode both
config1 and config4 to determine the total number TLBs.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/866/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:13 +01:00
David VomLehn 010c108d7a MIPS: PowerTV: Fix support for timer interrupts with > 64 external IRQs
The MIPS processor is limited to 64 external interrupt sources. Using a
greater number without IRQ sharing requires reading platform-specific
registers. On such platforms, reading the IntCtl register to determine
which interrupt corresponds to a timer interrupt will not work.

On MIPSR2 systems there is a solution - the TI bit in the Cause register,
specifically indicates that a timer interrupt has occured. This patch uses
that bit to detect interrupts for MIPSR2 processors, which may be expected
to work regardless of how the timer interrupt may be routed in the hardware.

Signed-off-by: David VomLehn (dvomlehn@cisco.com)
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/804/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-01-28 00:03:31 +01:00
David Daney dd7943920b MIPS: Add hugetlbfs page defines.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:30 +01:00
Ralf Baechle 0b54352600 MIPS: Fix sign-extension bug in 32-bit kernel on 32-bit hardware.
Probably nobody does arithmetic on cp0 register values so this has never
bitten.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-05-14 13:50:29 +01:00
Ralf Baechle c52399bece MIPS: Cavium: Add support for 8k and 32k page sizes.
Beyond the requirements of the architecture standard Cavium also supports
8k and 32k pages.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Acked-by: David Daney <ddaney@caviumnetworks.com>
2009-05-14 13:50:27 +01:00
Kevin D. Kissell c34e6e8bdd MIPS: SMTC: Bring set/clear/change_c0_## return value semantics uptodate.
Signed-off-by: Kevin D. Kissell <kevink@paralogos.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-05-14 13:50:24 +01:00
Ralf Baechle 89e18eb331 MIPS: Change {set,clear,change}_c0_<foo> to return old value.
This is more standard and useful and need for the following fix to work
correctly.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-03-23 23:38:05 +01:00
David Daney 25c3000300 MIPS: Override assembler target architecture for octeon.
Gas from binutils 2.19 fails to compile some cop1 instructions with
-march=octeon.  Since the cop1 instructions are present in mips1, use
that arch instead.  This will be fixed in binutils 2.20.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11 09:57:21 +00:00
David Daney ed918c2daf MIPS: Add Cavium OCTEON specific register definitions to mipsregs.h
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11 09:57:21 +00:00
Shinya Kuribayashi 542c1020ac MIPS: Add CONFIG_CPU_R5500 for NEC VR5500 series processors
We already have sufficient infrastructure to support VR5500 and VR5500A
series processors.  Here's a Makefile support to make it selectable by
ports, and enable it for NEC EMMA2RH Markeins board.

This patch also fixes a confused target help, and adds 1Gb PageMask bits
supported by VR5500 and its variants.

Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-10-27 16:18:29 +00:00
Ralf Baechle 384740dc49 MIPS: Move headfiles to new location below arch/mips/include
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-10-11 16:18:52 +01:00