Граф коммитов

42 Коммитов

Автор SHA1 Сообщение Дата
Florian Vaussard 439f559109 ARM: dts: socfpga: Do not include skeleton.dtsi
The skeleton.dtsi file is now deprecated as noted in commit 9c0da3cc61
("ARM: dts: explicitly mark skeleton.dtsi as deprecated"). The SoCFPGA
device trees already contain the nodes that are defined in skeleton.dtsi
(#address-cells, #size-cells, chosen, aliases, memory).

Including skeleton.dtsi is useless and will produce the following
warning when compiled with W=1:

Node /memory has a reg or ranges property, but no unit name

Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-03-06 15:54:58 -06:00
Florian Vaussard 0c9ff61586 ARM: dts: socfpga: Remove unneeded unit names
Node eccmgr has a unit name, but do not have a reg property as only the
child nodes do have this property. Likewise the usbphy node do not have
a reg property. This will trigger the following warnings when compiled
with W=1:

Node /soc/eccmgr@ffd08140 has a unit name, but no reg property
Node /soc/usbphy@0 has a unit name, but no reg property

Remove the superfluous unit names.

Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-03-06 15:54:58 -06:00
Florian Vaussard 9f24e81659 ARM: dts: socfpga: Add unit name to clock nodes
Most clock nodes in Arria5, Cyclone5 and Arria10 have a reg property but
does not have a unit name. This will trigger several warnings like this
one (when compiled with W=1):

Node /soc/clkmgr@ffd04000/clocks/periph_pll has a reg or ranges
property, but no unit name

Add the corresponding unit name to each node.

Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-03-06 15:54:58 -06:00
Thor Thayer cda1ade6a2 ARM: dts: Add EMAC AXI settings for Arria10
Add the device tree entries needed to support the EMAC AXI
bus settings on the Arria10 SoCFPGA chip.

Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-02-02 21:33:47 -06:00
Dinh Nguyen 7f0f5460d4 ARM: dts: socfpga: add missing compatible string for SDRAM controller
Add "altr,sdr-ctl" to the SDRAM controller node.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-01-06 01:42:06 -06:00
Dinh Nguyen 984442b72c ARM: dts: socfpga: add fpga region support on Arria10
Add the base FPGA region for DT overlay support in FPGA programming.

Signed-off-by: Alan Tull <atull@opensource.altera.com>
Signed-off-by: Matthew Gerlach <mgerlach@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-01-06 01:42:05 -06:00
Graham Moore f549af06e9 ARM: dts: socfpga: Add NAND device tree for Arria10
Add socfpga_arria10_socdk_nand.dts board file for supporting NAND.

Signed-off-by: Graham Moore <grmoore@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v2: move nand dts node to socfpga_arria10.dtsi
2017-01-05 06:12:47 -06:00
Dinh Nguyen f8a892815f ARM: dts: socfpga: add fpga-manager node for Arria10
Add the FPGA manger DTS entry for Arria10.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-01-04 18:12:11 -06:00
Dinh Nguyen 5d662bf15d ARM: dts: socfpga: Add QSPI node for the Arria10
Add the QSPI device node for Arria10 SOC.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-11-08 15:40:34 -06:00
Thor Thayer f2d6f8f817 ARM: dts: socfpga: Add SPI Master1 for Arria10 SR chip
Add the Altera Arria10 SPI Master Node in preparation for
the A10SR MFD node.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-10-18 22:17:51 -05:00
Dinh Nguyen ecba2390e3 ARM: dts: socfpga: enable arm,shared-override in the pl310
Enable the bit(22) shared-override bit for the SoCFPGA family. While at it,
enable the prefetch-data and prefetch-instr settings for the Arria10.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-10-18 15:57:13 -05:00
Thor Thayer 7c51d98de6 ARM: dts: Add Arria10 USB EDAC devicetree entry
Add the device tree entries needed to support the Altera USB
FIFO buffer EDAC on the Arria10 chip.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1468512408-5156-11-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov <bp@suse.de>
2016-08-08 05:59:41 +02:00
Thor Thayer 15ef94f4ee ARM: dts: Add Arria10 DMA EDAC devicetree entry
Add the device tree entries needed to support the Altera DMA
FIFO buffer EDAC on the Arria10 chip.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1468512408-5156-10-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov <bp@suse.de>
2016-08-08 05:59:40 +02:00
Linus Torvalds 043248cd4e ARM: DT updates for v4.8
Device tree contents continue to be the largest branches we submit. This
 time around, some of the contents worth pointing out is:
 
 - New SoC platforms:
   - Freescale i.MX 7Solo
   - Broadcom BCM23550
   - Cirrus Logic EP7209 and EP7211 (clps711x platforms)_
   - Hisilicon HI3519
   - Renesas R8A7792
 
 Some of the other delta that is sticking out, line-count wise:
  - Exynos moves of IP blocks under an SoC bus, which causes a large delta due
    to indentation changes
  - A new Tegra K1 board: Apalis
  - A bunch of small updates to many Allwinner platforms; new hardware support,
    some cleanup, etc.
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM DT updates from Olof Johansson:
 "Device tree contents continue to be the largest branches we submit.
  This time around, some of the contents worth pointing out is:

  New SoC platforms:
   - Freescale i.MX 7Solo
   - Broadcom BCM23550
   - Cirrus Logic EP7209 and EP7211 (clps711x platforms)_
   - Hisilicon HI3519
   - Renesas R8A7792

  Some of the other delta that is sticking out, line-count wise:
   - Exynos moves of IP blocks under an SoC bus, which causes a large
     delta due to indentation changes
   - a new Tegra K1 board: Apalis
   - a bunch of small updates to many Allwinner platforms; new hardware
     support, some cleanup, etc"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (426 commits)
  ARM: dts: sun8i: Add dts file for inet86dz board
  ARM: dts: sun8i: Add dts file for Polaroid MID2407PXE03 tablet
  ARM: dts: sun8i: Use sun8i-reference-design-tablet for ga10h dts
  ARM: dts: sun8i: Use sun8i-reference-design-tablet for polaroid mid2809pxe04
  ARM: dts: sun8i: reference-design-tablet: Add drivevbus-supply
  ARM: dts: Copy sun8i-q8-common.dtsi sun8i-reference-design-tablet.dtsi
  ARM: dts: sun5i: Use sun5i-reference-design-tablet.dtsi for utoo p66 dts
  ARM: dts: sun5i: Use sun5i-reference-design-tablet.dtsi for dit4350 dts
  ARM: dts: sun5i: reference-design-tablet: Remove mention of q8
  ARM: dts: sun5i: reference-design-tablet: Set lradc vref to avcc
  ARM: dts: sun5i: Rename sun5i-q8-common.dtsi sun5i-reference-design-tablet.dtsi
  ARM: dts: sun5i: Move q8 display bits to sun5i-a13-q8-tablet.dts
  ARM: dts: sunxi: Rename sunxi-q8-common.dtsi sunxi-reference-design-tablet.dtsi
  ARM: dts: at91: Don't build unnecessary dtbs
  ARM: dts: at91: sama5d3x: separate motherboard gmac and emac definitions
  ARM: dts: at91: at91sam9g25ek: fix isi endpoint node
  ARM: dts: at91: move isi definition to at91sam9g25ek
  ARM: dts: at91: fix i2c-gpio node name
  ARM: dts: at91: vinco: fix regulator name
  ARM: dts: at91: ariag25 : fix onewire node
  ...
2016-08-01 18:37:45 -04:00
Thor Thayer a67adb32d9 ARM: dts: Add Arria10 Ethernet EDAC devicetree entry
Add the device tree entries needed to support the Altera Ethernet FIFO
buffer EDAC on the Arria10 chip.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1466603939-7526-9-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov <bp@suse.de>
2016-06-27 19:46:19 +02:00
Matthew Gerlach b65c0efa35 ARM: dts: socfpga: fix definitions of serial console
The notion of which uart instance is serial0 or serial1
is board specific rather than generic to the chip. This
patch removes the serial aliases from generic chip dtsi
and adds an appropriate alias to the board specific dtsi.
By making the alias for serial0 point to uart1 for the arria10_socdk,
the linux boot command line supports specifying console=ttyS0,115200
for backwards compatibility, and it supports not specifying
the console at all.

Signed-off-by: Matthew Gerlach <mgerlach@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-06-08 14:09:11 -05:00
Thor Thayer 4586e4ea7e ARM: dts: Move Arria10 SDRAM as child of ECC Manager
Changes to support ECC Manager as SDRAM IRQ parent by
1) updating IRQ property values to correct child IRQs
2) moving node under ECC Manager.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-06-03 11:03:07 -05:00
Thor Thayer a034a8d9e5 ARM: dts: Arria10 ECC Manager IRQ controller changes
Changes to support IRQ controller implementation including adding
new property irq-controller to eccmgr and adding IRQ property
to children.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-06-03 11:03:04 -05:00
Dinh Nguyen 249ff32e1f ARM: dts: socfpga: add reset control for USB
Add the resets property for the 2 USB controllers.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-04-11 14:04:06 -05:00
Thor Thayer a44a77115f ARM: dts: socfpga: Add Altera Arria10 OCRAM EDAC devicetree entry
Add the device tree entries needed to support the Altera On-Chip
RAM EDAC on the Arria10 chip.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-04-11 14:03:41 -05:00
Thor Thayer 64ded09d29 ARM: dts: socfpga: Add Altera Arria10 L2 Cache EDAC devicetree entry
Add the device tree entries needed to support the Altera L2
cache EDAC on the Arria10 chip.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-04-11 14:03:08 -05:00
Graham Moore a1e89630ea ARM: dts: socfpga: Add missing clock and interrupt fields for Arria10 DMA
The PL330 DMA driver will not load on Arria10 without devicetree entries
for clocks and clock_names.  This patch adds those entries.  It also adds
the ninth interrupt, which is required for error detection.

Signed-off-by: Graham Moore <grmoore@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-04-11 13:58:34 -05:00
Dinh Nguyen faf68cdfdf ARM: dts: socfpga: add the clk-phase property for sd/mmc clock
The CIU clock for the SD/MMC should be the sdmmc_clk and not the
sdmmc_free_clk. Also, add the correct phase shift the sdmmc_clk.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-04-11 13:47:22 -05:00
Masahiro Yamada 2ef7d5f342 ARM, ARM64: dts: drop "arm,amba-bus" in favor of "simple-bus"
The compatible string "simple-bus" is well defined in ePAPR, while
I see no documentation for the "arm,amba-bus" arnywhere in ePAPR or
Documentation/devicetree/.

DT is also used by other projects than Linux kernel.  It is not a
good idea to rely on such an unofficial binding.

This commit
  - replaces "arm,amba-bus" with "simple-bus"
  - drops "arm,amba-bus" where it is used along with "simple-bus"

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2016-03-12 17:40:34 -08:00
Dinh Nguyen e7604ae277 ARM: socfpga: dts: add clock fields for I2C, UART and USB on Arria10
Add the required clock fields for all the I2C nodes. Also add missing clock
fields for UART0 and USB1.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-10-06 04:42:29 -05:00
Olof Johansson 93621d7037 SoCFPGA DTS updates for v4.3, take 2
- Add DTS property "altr,modrst-offset" for reset driver to
   use
 - Add updated reset defines for the reset driver
 - Add reset property for EMACs on Arria10
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Merge tag 'socfpga_dts_for_v4.3_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt

SoCFPGA DTS updates for v4.3, take 2
- Add DTS property "altr,modrst-offset" for reset driver to
  use
- Add updated reset defines for the reset driver
- Add reset property for EMACs on Arria10

* tag 'socfpga_dts_for_v4.3_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  ARM: socfpga: dts: Add resets for EMACs on Arria10
  ARM: socfpga: dts: add "altr,modrst-offset" property
  dt-bindings: Add reset manager offsets for Arria10

Signed-off-by: Olof Johansson <olof@lixom.net>
2015-08-13 12:19:38 +02:00
Dinh Nguyen 6855e5b709 ARM: socfpga: dts: Add resets for EMACs on Arria10
Add the reset property for the EMAC controllers on Arria10.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-09 21:58:58 -05:00
Dinh Nguyen 1a94acf858 ARM: socfpga: dts: add "altr,modrst-offset" property
The "altr,modrst-offset" property represents the offset into the reset manager
that is the first register to be used by the driver to bring peripherals out
of reset.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-09 21:58:46 -05:00
Dinh Nguyen efc1985c8f ARM: dts: socfpga: use stdout-path for chosen node
Use stdout-path dts property for kernel console.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-07-20 10:07:50 -05:00
Linus Torvalds 3d9f96d850 ARM: SoC: DT updates for v4.2
As usual, quite a few device-tree updates in ARM land.  There was ome
 minor churn in DTs due to relicensing under a dual-license, and lots
 of little additions of new peripherals, features etc, but nothing
 really exciting to call to your attention.  Some higlights, focsuing
 on support for new SoCs and boards:
 
 - AT91: new boards: Overkiz,  Acme Systems' Arietta G25
 - tegra: HDA support
 - bcm: new platforms: Buffalo WXR-1900DHP, SmartRG SR400ac, ASUS RT-AC87U
 - mvebu: new platforms: Compulab CM-A510, Armada 385-based Linksys
   boards, DLink DNS-327L
 - OMAP: new platforms: Baltos IR5221, LogicPD Torpedo, Toby-Churchill SL50
 - ARM: added support for Juno r1 board
 - sunxi: A33 SoC support; new boards: A23 EVB, SinA33, GA10H-A33, Mele A1000G
 - imx: i.MX7D SoC support; new boards: Armadeus Systems APF6,
   Gateworks GW5510, and aristainetos2 boards
 - hisilicon: hi6220 SoC support; new boards: 96boards hikey
 
 Conflicts: None
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC DT updates from Kevin Hilman:
 "As usual, quite a few device-tree updates in ARM land.  There was one
  minor churn in DTs due to relicensing under a dual-license, and lots
  of little additions of new peripherals, features etc, but nothing
  really exciting to call to your attention.  Some higlights, focsuing
  on support for new SoCs and boards:

   - AT91: new boards: Overkiz,  Acme Systems' Arietta G25
   - tegra: HDA support
   - bcm: new platforms: Buffalo WXR-1900DHP, SmartRG SR400ac, ASUS
     RT-AC87U
   - mvebu: new platforms: Compulab CM-A510, Armada 385-based Linksys
     boards, DLink DNS-327L
   - OMAP: new platforms: Baltos IR5221, LogicPD Torpedo, Toby-Churchill
     SL50
   - ARM: added support for Juno r1 board
   - sunxi: A33 SoC support; new boards: A23 EVB, SinA33, GA10H-A33,
     Mele A1000G
   - imx: i.MX7D SoC support; new boards: Armadeus Systems APF6,
     Gateworks GW5510, and aristainetos2 boards
   - hisilicon: hi6220 SoC support; new boards: 96boards hikey"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (462 commits)
  ARM: hisi: revert changes from hisi/hip04-dt branch
  ARM: nomadik: set proper compatible for accelerometer
  ARM64: juno: add GPIO keys
  ARM: at91/dt: sama5d4: fix dma conf for aes, sha and tdes nodes
  ARM: dts: Introduce STM32F429 MCU
  ARM: socfpga: dts: enable ethernet for Arria10 devkit
  ARM: dts: k2l: fix the netcp range size
  ARM: dts: k2e: fix the netcp range size
  ARM: dts: k2hk: fix the netcp range size
  ARM: dts: k2l-evm: Add device bindings for netcp driver
  ARM: dts: k2e-evm: Add device bindings for netcp driver
  ARM: dts: k2hk-evm: Add device bindings for netcp driver
  ARM: BCM5301X: Add DT for Asus RT-AC87U
  ARM: BCM5301X: add IRQ numbers for PCIe controller
  ARM: BCM5301X: add NAND flash chip description
  arm64: dts: Add dts files for Hisilicon Hi6220 SoC
  clk: hi6220: Document devicetree bindings for hi6220 clock
  arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoC
  ARM: at91/dt: sama5d4ek: mci0 uses slot 0
  ARM: at91/dt: kizbox: fix mismatch LED PWM device
  ...
2015-06-26 11:43:59 -07:00
Thor Thayer 54b4a8f578 arm: socfpga: dts: Add Arria10 SDRAM EDAC DTS support
Add support for the Arria10 SDRAM EDAC. Update the bindings document for
the new match string.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: galak@codeaurora.org
Cc: grant.likely@linaro.org
Cc: ijc+devicetree@hellion.org.uk
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: m.chehab@samsung.com
Cc: mark.rutland@arm.com
Cc: pawel.moll@arm.com
Cc: robh+dt@kernel.org
Cc: tthayer.linux@gmail.com
Link: http://lkml.kernel.org/r/1433428128-7292-5-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov <bp@suse.de>
2015-06-24 18:16:10 +02:00
Dinh Nguyen 112cadfd43 ARM: socfpga: dts: enable ethernet for Arria10 devkit
Update the arria10 gmac nodes with all the necessary properties for ethernet
to function on the Arria10 devkit.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
2015-06-10 15:45:12 -07:00
Kevin Hilman da8d2b5d92 SoCFPGA updates for v4.2 part 3
- Add SCU node for Arria 10
 - Add enable-method for cpu nodes
 - Add SDRAM controller binding doc
 - Enable gpio-leds on SoCFPGA Socrates board
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Merge tag 'socfpga_dts_for_v4.2_part_3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt

SoCFPGA updates for v4.2 part 3
- Add SCU node for Arria 10
- Add enable-method for cpu nodes
- Add SDRAM controller binding doc
- Enable gpio-leds on SoCFPGA Socrates board

* tag 'socfpga_dts_for_v4.2_part_3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  ARM: socfpga: socrates: add gpio-leds
  ARM: socfpga: socrates: enable gpio0/1
  ARM: socfpga: dts: add sdram controller dt binding doc
  ARM: socfpga: dts: add enable-method property for cpu nodes
  ARM: socfpga: dts: add the a9-scu node for arria10
2015-06-10 15:40:59 -07:00
Dinh Nguyen ebbce1bbc4 ARM: socfpga: dts: add enable-method property for cpu nodes
Add the enable-method property for the cpu node on socfpga.dtsi and
socfpga_arria10.dtsi. This is for CPU_METHOD_OF_DECLARE to use to enable
the secondary core.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-06-02 14:18:15 -05:00
Dinh Nguyen 479f8df04c ARM: socfpga: dts: add the a9-scu node for arria10
Add a dts node for the A9 SCU on the Arria10 platform.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-06-02 14:18:06 -05:00
Dinh Nguyen da29d824a6 ARM: socfpga: dts: add clocks to the Arria10 platform
Add all the clock nodes for the Arria10 platform. At the same time, update
the peripherals with their respective clocks property.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v2: Add the l4_sys_free_clk node
2015-05-11 13:26:02 -05:00
Vince Bridgers c01e8cdb7b ARM: socfpga: dts: Add tx-fifo-depth and rx-fifo-depth properties
Add tx-fifo-depth and rx-fifo-depth devicetree properties for socfpga
stmmac. These devicetree properties will be used to configure certain
features of the stmmac on the socfpga.

Signed-off-by: Vince Bridgers <vbridger@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-05-11 13:15:00 -05:00
Vince Bridgers be9863cac2 ARM: socfpga: dts: Add multicast bins and unicast filter entries
Add multicast-filter-bins and perfect-filter-entries configuration properties
to the socfpga devicetree for the Arria 10 socfpga.

Signed-off-by: Vince Bridgers <vbridger@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-05-11 13:14:59 -05:00
Dinh Nguyen 74568da48f ARM: socfpga: dts: enable UART1 for the debug uart
Arria10 devkit is using UART1 for the debug uart port. Remove
unused aliases.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v2: Add removal of unused aliases
2015-05-11 13:14:59 -05:00
Dinh Nguyen 1dfb7d2fd6 ARM: socfpga: dts: disable the sdmmc, and uart nodes in the base arria10
Add status = "disabled" in the base DTSI for Arria10.  The SDMMC and uart
nodes should be enabled in the appropriate board file.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-05-11 13:14:59 -05:00
Dinh Nguyen 08d6638f1a ARM: socfpga: dts: add cpu1-start-addr for Arria 10
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-05-11 13:14:58 -05:00
Dinh Nguyen 475dc86d08 arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC
The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10
SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there
are enough differences to warrant a new base dtsi.

The differences are:
* 3 EMAC controllers
* 5 I2C controllers
* 3 SPI controllers
* 1.5 GHZ dual A9s
* Support for DDR4

Besides the usual memory map and IRQ changes, the clock framework will be
different, so this patch just adds the fixed-clocks.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-11-20 23:08:42 -06:00