* 'davinci-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci: (62 commits)
DaVinci: DM646x - platform changes for vpif capture and display drivers
davinci: DM355 - platform changes for vpfe capture
davinci: DM644x platform changes for vpfe capture
davinci: audio: move tlv320aic33 i2c setup into board files
DaVinci: EDMA: Adding 2 new APIs for allocating/freeing PARAMs
DaVinci: DM365: Adding entries for DM365 IRQ's
DaVinci: DM355: Adding PINMUX entries for DM355 Display
davinci: Handle pinmux conflict between mmc/sd and nor flash
davinci: Add NOR flash support for da850/omap-l138
davinci: Add NAND flash support for DA850/OMAP-L138
davinci: Add MMC/SD support for da850/omap-l138
davinci: Add platform support for da850/omap-l138 GLCD
davinci: Macro to convert GPIO signal to GPIO pin number
davinci: Audio support for DA850/OMAP-L138 EVM
davinci: Audio support for DA830 EVM
davinci: Correct the number of GPIO pins for da850/omap-l138
davinci: Configure MDIO pins for EMAC
DaVinci: DM365: Add Support for new Revision of silicon
DaVinci: DM365: Fix Compilation issue due to PINMUX entry
DaVinci: EDMA: Updating default queue handling
...
* fix/asoc:
ASoC: remove unused #include <linux/version.h>
ASoC: S3C lrsync function made to work with IRQs disabled.
ASoC: Fix display of stream name in DAPM debugfs
ASoC: Clean up error handling in MPC5200 DMA setup
s3c2412_snd_lrsync() maybe reached with IRQs disabled and if LRCLK
is dead due to improper initialization of CPU or CODEC, the system
gets stuck in the loop because jiffies may never get updated.
Implemented counter based wait mechanism for atleast the same
timeout period.
Signed-off-by: Jassi <jassi.brar@samsung.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (257 commits)
[ARM] Update mach-types
ARM: 5636/1: Move vendor enum to AMBA include
ARM: Fix pfn_valid() for sparse memory
[ARM] orion5x: Add LaCie NAS 2Big Network support
[ARM] pxa/sharpsl_pm: zaurus c3000 aka spitz: fix resume
ARM: 5686/1: at91: Correct AC97 reset line in at91sam9263ek board
ARM: 5640/1: This patch modifies the support of AC97 on the at91sam9263 ek board
ARM: 5689/1: Update default config of HP Jornada 700-series machines
ARM: 5691/1: fix cache aliasing issues between kmap() and kmap_atomic() with highmem
ARM: 5688/1: ks8695_serial: disable_irq() lockup
ARM: 5687/1: fix an oops with highmem
ARM: 5684/1: Add nuc960 platform to w90x900
ARM: 5683/1: Add nuc950 platform to w90x900
ARM: 5682/1: Add cpu.c and dev.c and modify some files of w90p910 platform
ARM: 5626/1: add suspend/resume functions to amba-pl011 serial driver
ARM: 5625/1: fix hard coded 4K resource size in amba bus detection
MMC: MMCI: convert realview MMC to use gpiolib
ARM: 5685/1: Make MMCI driver compile without gpiolib
ARM: implement highpte
ARM: Show FIQ in /proc/interrupts on CONFIG_FIQ
...
Fix up trivial conflict in arch/arm/kernel/signal.c.
It was due to the TIF_NOTIFY_RESUME addition in commit d0420c83f ("KEYS:
Extend TIF_NOTIFY_RESUME to (almost) all architectures") and follow-ups.
Error handling code following a kzalloc should free the allocated data.
Error handling code following an ioremap should iounmap the allocated data.
The semantic match that finds the first problem is as follows:
(http://www.emn.fr/x-info/coccinelle/)
// <smpl>
@r exists@
local idexpression x;
statement S;
expression E;
identifier f,f1,l;
position p1,p2;
expression *ptr != NULL;
@@
x@p1 = \(kmalloc\|kzalloc\|kcalloc\)(...);
...
if (x == NULL) S
<... when != x
when != if (...) { <+...x...+> }
(
x->f1 = E
|
(x->f1 == NULL || ...)
|
f(...,x->f1,...)
)
...>
(
return \(0\|<+...x...+>\|ptr\);
|
return@p2 ...;
)
@script:python@
p1 << r.p1;
p2 << r.p2;
@@
print "* file: %s kmalloc %s return %s" % (p1[0].file,p1[0].line,p2[0].line)
// </smpl>
Signed-off-by: Julia Lawall <julia@diku.dk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* topic/asoc: (226 commits)
ASoC: au1x: PSC-AC97 bugfixes
ASoC: Fix WM835x Out4 capture enumeration
ASoC: Remove unuused hw_read_t
ASoC: fix pxa2xx-ac97.c breakage
ASoC: Fully specify DC servo bits to update in wm_hubs
ASoC: Debugged improper setting of PLL fields in WM8580 driver
ASoC: new board driver to connect bfin-5xx with ad1836 codec
ASoC: OMAP: Add functionality to set CLKR and FSR sources in McBSP DAI
ASoC: davinci: i2c device creation moved into board files
ASoC: Don't reconfigure WM8350 FLL if not needed
ASoC: Fix s3c-i2s-v2 build
ASoC: Make platform data optional for TLV320AIC3x
ASoC: Add S3C24xx dependencies for Simtec machines
ASoC: SDP3430: Fix TWL GPIO6 pin mux request
ASoC: S3C platform: Fix s3c2410_dma_started() called at improper time
ARM: OMAP: McBSP: Merge two functions into omap_mcbsp_start/_stop
ASoC: OMAP: Fix setup of XCCR and RCCR registers in McBSP DAI
OMAP: McBSP: Use textual values in DMA operating mode sysfs files
ARM: OMAP: DMA: Add support for DMA channel self linking on OMAP1510
ASoC: Select core DMA when building for S3C64xx
...
This patch fixes the following bugs:
- only reprogram bitdepth if it has changed since last call to hw_params.
- add locking inside ac97_read/write functions:
When reprogramming sample depth, the ac97 unit has to be disabled,
which should not be done in the middle of codec register accesses.
- retry timed-out codec register accesses.
- wait for status bits to set/clear when starting/stopping various
functional blocks; very important after reenabling AC97 unit else
sound may be distorted (e.g. high-pitch noise in 1kHz sine wave).
- clear fifos before/after starting/stopping RX/TX.
- longer timeouts waiting for PSC/AC97 ready after cold reset
with certain codecs this can take ridiculous amounts of time.
Run-tested on various Au1200 platforms with various codecs.
Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
It's the 8th enum of a zero indexed array. This is why I don't let
new drivers use these arrays of enums...
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: stable@kernel.org
Avoids potential issues if we read back unexpected values during
a read/modify/write cycle.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Bug was caught while trying to use WM8580 as I2S master on SMDK.
Symptoms were lesser LRCLK read by CRO(41.02 instead of 44.1 KHz) Solved
by referring to WM8580A manual and setting mask value correctly and
making the code to not touch 'reserved' bits of PLL4 register.
Signed-off-by: Jassi <jassi.brar@samsung.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
As discussed, the patch uses the original TDM order without rewriting.
For the match between TDM slot number and audio channel number, a new
API need be added.
Signed-off-by: Barry Song <21cnbao@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The McBSP1 port in OMAP3 processors (I believe OMAP2 too but I don't have
specifications to check it) have additional CLKR and FSR pins for McBSP1
receiver. Reset default is that receiver is using bit clock and frame
sync signal from those pins but it is possible to configure to use
also CLKX and FSX pins as well. In fact, other McBSP ports are doing that
internally that transmitter and receiver share the CLKX and FSX.
Add functionaly that machine drivers can set the CLKR and FSR sources by
using the snd_soc_dai_set_sysclk.
Thanks to "Aggarwal, Anuj" <anuj.aggarwal@ti.com> for reporting the issue.
Signed-off-by: Jarkko Nikula <jhnikula@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Also, the codec setup data structure has to remain for successful
probe.
Signed-off-by: Chaithrika U S <chaithrika@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
If the requested FLL configuration is the one we're currently running
in it's at best pointless to reconfigure the FLL.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Now that we don't need the I2C address for the device the platform data
is redundant so allow it to be omitted.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Tested-by: Chaithrika U S <chaithrika@ti.com>
No point in building them for S3C64xx, certainly no sense in running
into build issues there.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
- restructure to support multiple channel controllers by using
additional struct resources for each CC
- interface changes visible to EDMA clients
Introduce macros to build IDs from controller and channel number,
and to extract them. Modify the edma_alloc_slot function to take an
extra argument for the controller.
Also update ASoC drivers to use API. ASoC changes
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
- Move queue related mappings to dm<soc>.c
EDMA in DM355 and DM644x has two transfer controllers while DM646x
has four transfer controllers. Moving the queue to tc mapping and
queue priority mapping to dm<soc>.c will be helpful to probe these
mappings from platform device so that the machine_is_* testing will
be avoided.
- add channel mapping logic
Channel mapping logic is introduced in dm646x EDMA. This implies
that there is no fixed association for a channel number to a
parameter entry number. In other words, using the DMA channel
mapping registers (DCHMAPn), a PaRAM entry can be mapped to any
channel. While in the case of dm644x and dm355 there is a fixed
mapping between the EDMA channel and Param entry number.
Signed-off-by: Naresh Medisetty <naresh@ti.com>
Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Reviewed-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Fix the write to PMBR1 register through I2C. Also, the constant which
holds the value to write is now called TWL4030_GPIO6_PWM0_MUTE. This
name is based on TRM to avoid confusion.
Signed-off-by: Jorge Eduardo Candelaria <x0107209@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
s3c24xx dma has the auto reload feature, when the the trnasfer is done,
CURR_TC(DSTAT[19:0], current value of transfer count) reaches 0, and DMA
ACK becomes 1, and then, TC(DCON[19:0]) will be loaded into CURR_TC. So
the transmission is repeated.
IRQ is issued while auto reload occurs. We change the DISRC and
DCON[19:0] in the ISR, but at this time, the auto reload has been
performed already. The first block is being re-transmitted by the DMA.
So we need rewrite the DISRC and DCON[19:0] for the next block
immediatly after the this block has been started to be transported.
The function s3c2410_dma_started() is for this perpose, which is called
in the form of "s3c2410_dma_ctrl(prtd->params->channel,
S3C2410_DMAOP_STARTED);" in s3c24xx_pcm_trigger().
But it is not correct. DMA transmission won't start until DMA REQ signal
arrived, it is the time s3c24xx_snd_txctrl(1) or s3c24xx_snd_rxctrl(1)
is called in s3c24xx_i2s_trigger().
In the current framework, s3c24xx_pcm_trigger() is always called before
s3c24xx_pcm_trigger(). So the s3c2410_dma_started() should be called in
s3c24xx_pcm_trigger() after s3c24xx_snd_txctrl(1) or
s3c24xx_snd_rxctrl(1) is called in this function.
However, s3c2410_dma_started() is dma related, to call this function we
should provide the channel number, which is given by
substream->runtime->private_data->params->channel. The private_data
points to a struct s3c24xx_runtime_data object, which is define in
s3c24xx_pcm.c, so s3c2410_dma_started() can't be called in s3c24xx_i2s.c
Fix this by moving the call to signal the DMA started to the DAI
drivers.
Signed-off-by: Shine Liu <liuxian@redflag-linux.com>
Signed-off-by: Shine Liu <shinel@foxmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Functionality of functions omap_mcbsp_xmit_enable and omap_mcbsp_recv_enable
can be merged into omap_mcbsp_start and omap_mcbsp_stop since API of
those omap_mcbsp_start and omap_mcbsp_stop was changed recently allowing
to start and stop individually the transmitter and receiver.
This cleans up the code in arch/arm/plat-omap/mcbsp.c and in
sound/soc/omap/omap-mcbsp.c which was the only user for those removed
functions.
Signed-off-by: Jarkko Nikula <jhnikula@gmail.com>
Acked-by: Eero Nurkkala <ext-eero.nurkkala@nokia.com>
Cc: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Commit ca6e2ce086 is setting up few XCCR and
RCCR bits for I2S and DPS_A formats. Part of the bits are already set
for all formats and I believe that XDISABLE and RDISABLE bits are
format independent.
As XCCR and RCCR are found only from OMAP2430 and OMAP34xx, I move setup
of XDISABLE and RDISABLE to where those cpu's are tested and remove format
dependent part for simplicity.
Signed-off-by: Jarkko Nikula <jhnikula@gmail.com>
Acked-by: Eero Nurkkala <ext-eero.nurkkala@nokia.com>
Cc: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Free socdev if snd_soc_init_card() fails.
Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Currently when built with DEBUG DAPM will dump information about
the power state decisions it is taking for each widget to dmesg.
This isn't an ideal way of getting the information - it requires
a kernel build to turn it on and off and for large hub CODECs the
volume of information is so large as to be illegible. When the
output goes to the console it can also cause a noticable impact
on performance simply to print it out.
Improve the situation by adding a dapm directory to our debugfs
tree containing a file per widget with the same information in
it. This still requires a decision to build with debugfs support
but is easier to navigate and much less intrusive.
In addition to the previously displayed information active streams
are also shown in these files.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This patch is tested by ms7724se
Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This is very simple driver for ALSA
It supprt headphone output and stereo input only
This patch is tested by ms7724se
Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Add support for the tlv320aic3x CODEC on the Simtec Hermes board.
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Fixup the device changes by modifying the files that we just removed the
explicit device creation from with i2c_register_board_info() until this
can be moved into the relevant board files.
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The tlv320aic3x driver managed its own i2c device, instead of an extant
one created by the board support code. Change the code to make it so that
the driver binds to an extant (in this case i2c) device.
Add explict tlv320aic33 as well as tlv320aic3x to the supported device
table and remove the old driver bindings from the users of this code.
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Add core support for the range of S3C24XX Simtec boards with TLV320AIC23
CODECs on them. Since there are also boards with similar IIS routing the
AMP and the configuration code is placed in a core file for re-use with
other CODEC bindings.
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Configures DMA sync mode depending on McBSP operating mode value.
The value is configurable by McBSP instance. So, depending
on McBSP operating mode, the DMA sync mode is passed from
omap-mcbsp to omap-pcm. Besides that, it also configures
McBSP threshold value depending on which McBSP mode is activated.
Signed-off-by: Eduardo Valentin <eduardo.valentin@nokia.com>
Acked-by: Jarkko Nikula <jhnikula@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This patch changes the way DMA is done in omap-pcm.c
in order to reduce power consumption. There is no need
to have so much SW control in order to have DMA in idle
state during audio streaming. Configuring McBSP threshold value
and DMA to FRAME_SYNC are sufficient.
Signed-off-by: Eduardo Valentin <eduardo.valentin@nokia.com>
Acked-by: Jarkko Nikula <jhnikula@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
All these steps are required for ASoC to behave correctly.
rccr and xccr are format dependent, for example TDM audio
has different values than I2S or DSP_A. Also the
omap_mcbsp_xmit_enable and/or omap_mcbsp_recv_enable must
be called right after the DMA has started.
This provides no longer L and R channels switching at random.
Signed-off-by: Eero Nurkkala <ext-eero.nurkkala@nokia.com>
Acked-by: Jarkko Nikula <jhnikula@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This is, no RFIG or XFIG (Not defined in 34xx), correct
initiliazation of rccr and xccr.
Signed-off-by: Eero Nurkkala <ext-eero.nurkkala@nokia.com>
Acked-by: Jarkko Nikula <jhnikula@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Align DMA address to DMA burst transaction sizes.
Signed-off-by: Eduardo Valentin <eduardo.valentin@nokia.com>
Acked-by: Jarkko Nikula <jhnikula@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Improve DMA transfers by enabling Burst transaction.
Signed-off-by: Eduardo Valentin <eduardo.valentin@nokia.com>
Acked-by: Jarkko Nikula <jhnikula@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This driver is very simple.
It support playback only now.
This patch is tested by ms7724se board.
Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
> Then it's a driver bug. If unaligned period size is allowed, it means
> that the irq is really generated in that period, not at the buffer
> boundary. Otherwise, it must have a proper hw-constraint to align the
> period size to the buffer size.
This patch will fix the bug metioned in the above mail. Force the peroid
size to be aligned with the buffer size.
Based and tested on linux-2.6.31-rc6.
Signed-off-by: Shine Liu <shinel@foxmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
If the CODEC does not provide a set_bias_level() then update the
bias_level variable for it since other parts of the system expect
that to be maintained.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Linus Torvalds
Takashi Iwai
Huang Weiyi
Jassi
Mark Brown
Julia Lawall
Russell King
Manuel Lauss
jassi brar
Barry Song
Jarkko Nikula
Chaithrika U S
Sudhakar Rajashekhara
Candelaria Villareal, Jorge
Shine Liu
Marek Vasut
Roel Kluin
Kuninori Morimoto
Ben Dooks
Eduardo Valentin
Eero Nurkkala