Граф коммитов

505596 Коммитов

Автор SHA1 Сообщение Дата
Guenter Roeck 19334920ea net: dsa: Set valid phy interface type
If the phy interface mode is not found in devicetree, or if devicetree
is not configured, of_get_phy_mode returns -ENODEV. The current code
sets the phy interface mode to the return value from of_get_phy_mode
without checking if it is valid.

This invalid phy interface mode is passed as parameter to of_phy_connect
or to phy_connect_direct. This sets the phy interface mode to the invalid
value, which in turn causes problems for any code using phydev->interface.

Fixes: b31f65fb43 ("net: dsa: slave: Fix autoneg for phys on switch MDIO bus")
Fixes: 0d8bcdd383 ("net: dsa: allow for more complex PHY setups")
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2015-02-17 10:37:39 -08:00
Mike Marciniszyn 041af0bb76 IB/qib: Fix sizeof checkpatch warnings
Reviewed-by: Dennis Dalessandro <dennis.dalessandro@intel.com>
Signed-off-by: Mike Marciniszyn <mike.marciniszyn@intel.com>
Signed-off-by: Roland Dreier <roland@purestorage.com>
2015-02-17 10:26:19 -08:00
Andreea-Cristina Bernat 590c3fec2d IB/qib: Replace rcu_assign_pointer() with RCU_INIT_POINTER() in qib_keys.c
The uses of "rcu_assign_pointer()" are NULLing out the pointers.
According to RCU_INIT_POINTER()'s block comment:
"1.   This use of RCU_INIT_POINTER() is NULLing out the pointer"
it is better to use it instead of rcu_assign_pointer() because it has a
smaller overhead.

The following Coccinelle semantic patch was used:
@@
@@

- rcu_assign_pointer
+ RCU_INIT_POINTER
  (..., NULL)

[Derived from http://marc.info/?l=linux-rdma&m=140836519219236&w=2]

Tested-by: Mike Marciniszyn <mike.marciniszyn@intel.com>
Signed-off-by: Andreea-Cristina Bernat <bernat.ada@gmail.com>
Signed-off-by: Mike Marciniszyn <mike.marciniszyn@intel.com>
Signed-off-by: Roland Dreier <roland@purestorage.com>
2015-02-17 10:26:19 -08:00
Andreea-Cristina Bernat 03c885913f IB/qib: Replace rcu_assign_pointer() with RCU_INIT_POINTER() in qib_qp.c
According to RCU_INIT_POINTER()'s block comment 3.a, it can be used if
"1.   This use of RCU_INIT_POINTER() is NULLing out the pointer"
it is better to use it instead of rcu_assign_pointer() because it has a
smaller overhead.

"3.   The referenced data structure has already been exposed to readers either
at compile time or via rcu_assign_pointer() -and-
 a.   You have not made -any- reader-visible changes to this structure since
then".

These cases fulfill the conditions above because between the
rcu_dereference_protected() call and the rcu_assign_pointer() call
there is no update of that value.  Therefore, this patch makes the
replacement.

The following Coccinelle semantic patch was used:
@@
@@

- rcu_assign_pointer
+ RCU_INIT_POINTER
  (...,
(
 rtnl_dereference(...)
|
 rcu_dereference_protected(...)
) )

[consolidated from http://marc.info/?l=linux-rdma&m=140836578119485&w=2 and
 http://marc.info/?l=linux-rdma&m=140906361403047&w=2]

Tested-by: Mike Marciniszyn <mike.marciniszyn@intel.com>
Signed-off-by: Andreea-Cristina Bernat <bernat.ada@gmail.com>
Signed-off-by: Mike Marciniszyn <mike.marciniszyn@intel.com>
Signed-off-by: Roland Dreier <roland@purestorage.com>
2015-02-17 10:26:19 -08:00
Dan Carpenter f614fc15ae IB/mlx5: Fix error code in get_port_caps()
The current code returns success when kmalloc() fails.  It should
return an error code, -ENOMEM.

Fixes: e126ba97db ("mlx5: Add driver for Mellanox Connect-IB adapters")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Roland Dreier <roland@purestorage.com>
2015-02-17 10:22:59 -08:00
Linus Torvalds cc4f9c2a91 ARM: SoC 64-bit changes and additions
The 64-bit set of updates this release cycle adds support for three new platforms:
 
 - Samsunc Exynos 7
 - Freescale LS2085a
 - Mediatek MT8173
 
 For all these, the changes mostly consititude additions of DT contents,
 but also some Kconfig entries to allow dependency/selection of drivers
 per-platform, etc.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJU4vKcAAoJEIwa5zzehBx358oQAInkGDQLBIl758u0VlXFvKnW
 NaMewMzH6R32hpDD8sr9zk/xdeS9BkN4nQzg49lFBHj6GbxtEYY94cpdYebjwntj
 Mg5tj99Mc1xlN0EwFEkBttf7gBd2JpPPhqKLKAfHaypeHlxyQkcLBWAq5vJbQHS9
 Iar2C6HsCBbpmbSFf3xI/w0Q16HlYmXxrICKIU1ZzqQzSo3IJM/6yFjNKlgbbdWN
 aQr5KVZtAgQLSuU4BCBYy3hvxS794bk3DdDpyYXa7RNAv5/zG/mU127HHYMFtM8K
 Ebk2ksbq2KolulMvKCxO2sLqlKgGRaSY5L54Ab5OXsd3Hys4YqgOyOxdE6AP++Ro
 gUn+bjfFsJ+9xmYoAQwPCWF9nz1YBLdhr72fcV5eR8Jq0b6VgT8ELI6/gYePfccJ
 5efWPev8qFvuBwgHLTf5NKFC2UN14nI3yUf9znez5OwyRs38PaXP2ju/hg1jd8d3
 1zJEj93oUvWggmUya+5PvX9G6X5dgYoobQVLKycRfXNH47gf906ArcQRASJbMPNA
 3HZFFnBzOBkb9MLwx1HbXRabIxGGqjzmhWr0efq6WZzg8cG/VoeAgPZBOGnRmzDV
 aPK+tFhmm/drACdAI6V3Pff7YLsQF0GBfOmGUgO+4NzezvKRzBGFXU9pohvpsxSI
 vyNhKL54OlI2eMfTR/XM
 =FuwP
 -----END PGP SIGNATURE-----

Merge tag '64bit-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC 64-bit changes and additions from Olof Johansson:
 "The 64-bit set of updates this release cycle adds support for three
  new platforms:

   - Samsunc Exynos 7
   - Freescale LS2085a
   - Mediatek MT8173

  For all these, the changes mostly consititude additions of DT
  contents, but also some Kconfig entries to allow dependency/selection
  of drivers per-platform, etc"

* tag '64bit-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  arm64: Kconfig: clean up two no-op Kconfig options from CONFIG_ARCH_TEGRA*
  arm64: Fix sort of platform Kconfig entries
  arm64: Add support for FSL's LS2085A SoC in Kconfig and defconfig
  arm64: Add DTS support for FSL's LS2085A SoC
  arm64: mediatek: Add MT8173 SoC Kconfig and defconfig
  arm64: dts: Add mediatek MT8173 SoC and evaluation board dts and Makefile
  Document: DT: Add bindings for mediatek MT8173 SoC Platform
  arm64: Add Tegra132 support
  arm64: Enable ARMv8 based exynos7 SoC support
  arm64: dts: Add nodes for mmc, i2c, rtc, watchdog, adc on exynos7
  arm64: dts: Add PMU DT node for exynos7 SoC
  arm64: dts: Add initial pinctrl support to exynos7
  arm64: dts: Add initial device tree support for exynos7
2015-02-17 09:47:46 -08:00
Linus Torvalds 03a40e2994 ARM: SoC defconfig changes
Most of these changes are to enable new drivers that have been merged, or
 various additions to make defconfigs more useful. There's also a set of patches
 trimming down omap2plus kernel size a bit since it is quite large.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJU4ukrAAoJEIwa5zzehBx3ApIP/1HEfcdke2RLZknLl5GyIjTV
 gPAvtb1f8bXxCeCQIvwiSg8KozBg0XQoy4EqkBgWi2vKdX2jcrKPh1m4oWgJwbTx
 ZIeHRNPvTl3p01KpOesz02XCeGMTZdb5vip+dTmJ4LFukcBtKxbMSLDMYo+RzRE5
 Ta6WcFqloaOaQRFKGHjL1QWf5W+xbzcVcd9a/v0FU0TXsKdZ4yC+6Zv5q2Al8vb5
 BqC8fWNTO2cGl3SX59czR4xPJMu/bPGfzKG+++bu0KoG7PAnNP/edbwlIDVuF1aN
 Dv2ZA+yiLIV1SCriayg4bj8DOX6eqFjHczgDEcZZ98BHtnwZgf1+j/ioiNq/lTFN
 Xn3uxqi8SSvyg7Xdx9hHFrN6dgmpEqLvMc7gebWTJbOgDgUuY7G+Aecmj49ltKqa
 qldOATT5JPQDAZcQTVv1I/fiSUKQujO3zN7LT8rLWwLHOSZ2g6jLZ1lFJQ5+g2q6
 zkiPO1GFh9CRnq6XEdIakhtOmnnQcwDrEj3SxHdZ2xzxFbJ2t9ARxz5Q40znTu9m
 DozUxAk+6scrq8BR5GtSnVQL8uzpDX9pki38JpZD75eSpB91LNq+Ql+vO8uinjH1
 khej1qQ4tKEHd0zBEE+3aLOq1o4X/faK+5ayrDKLGrX1XAoUs9jZdu+FXBNS2YQV
 vR+/QKE2pUHbX9SpeOSB
 =Ar0W
 -----END PGP SIGNATURE-----

Merge tag 'defconfig-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC defconfig changes from Olof Johansson:
 "Most of these changes are to enable new drivers that have been merged,
  or various additions to make defconfigs more useful.  There's also a
  set of patches trimming down omap2plus kernel size a bit since it is
  quite large"

* tag 'defconfig-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (39 commits)
  ARM: config: add DEVTMPFS option by default to keystone config
  ARM: multi_v7_defconfig: Enable Exynos5420 Multi-Cluster PM support
  ARM: shmobile: Select CONFIG_REGULATOR in defconfig once again
  ARM: exynos_defconfig: Enable CONFIG_FHANDLE
  ARM: exynos_defconfig: Enable PMIC and MUIC drivers for Gears and Trats2
  ARM: exynos_defconfig: Enable CONFIG_LOCKUP_DETECTOR
  ARM: config: enable ARCH_HIP01
  ARM: omap2plus_defconfig: Enable OHCI & EHCI HCD support
  ARM: omap2plus_defconfig: Enable misc options for BeagleBoard-X15 platform
  ARM: imx_v6_v7_defconfig: enable more USB functions
  ARM: imx_v6_v7_defconfig: Select CONFIG_FB_MXS
  ARM: omap2plus_defconfig: Enable pcf857x
  ARM: omap2plus_defconfig: Add NOR flash support
  ARM: omap2plus_defconfig: Enable support for davinci_emac
  ARM: multi_v7_defconfig: Enable MiPHY28lp - ST's Generic (SATA, PCIe & USB3) PHY
  ARM: efm32: update defconfig
  ARM: at91: sama5: enable atmel-isi and ov2640 in defconfig
  ARM: multi_v7_defconfig: Enable Hip01 platform
  ARM: config: multi_v7: Update it for Keystone defconfig
  ARM: shmobile: Enable kzm9g board in multiplatform defconfig
  ...
2015-02-17 09:44:50 -08:00
Linus Torvalds 18656782a8 ARM: SoC driver updates
These are changes for drivers that are intimately tied to some SoC
 and for some reason could not get merged through the respective
 subsystem maintainer tree.
 
 This time around, much of this is for at91, with the bulk of it being syscon
 and udc drivers.
 
 Also, there's:
 - coupled cpuidle support for Samsung Exynos4210
 - Renesas 73A0 common-clk work
 - of/platform changes to tear down DMA mappings on device destruction
 - a few updates to the TI Keystone knav code
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJU4upSAAoJEIwa5zzehBx3HkUP/Rc4B1yZChNIFNfVq4dbei6w
 dT9WdFmxOIj2JLeXEypFBiNf1nSHmsxrZe9/IDACz2fYQOnaZZ6/786utUJP/PtC
 2GDJy9cjL2Xh03We3nQp5z6J33XvpEni1t82cOpCl8wLBOQNnkjEks8UvLgi1LHW
 CNLcMm8JtDQ2aB/gRTjzetp9liZluESY5+Mig+loE2F/rzbMbNQDcWDDgUPyIQIS
 1onL+Bad3BnGFdo/+qnkurGc81pxoKiQJty06VWFftzvIwxXhsNjrqls2+KzstAx
 0lLvW1tqaDhXvUBImRM8GgfbldZslsgoFVmgESS9MpPMBNENYrkAiQNvJUnM7kd9
 qHDQNq+zRNsz/k4fVvp/YUp7xEiAo4rLcFmp/dBr535jS2LNyiZnB94q+kXsin/m
 tiyEMx+RWxEHTEHN9WdKE61Ty1RbzOa5UTLSzOKFAkF+m2nvuQsJvb97n19coAq9
 SSsj/wJgesfqrDEegphCDh1fyVxUzlAjjhTAyvPS155WvPzkbxZxuBbSqRuriRKA
 2aCfVne2ELimHAr3LEPgPW2kFBcONHckOGe6MvrTX4zPHU8bb9WIeg+iGdQChnr3
 nclT9jq+ZnQro5XTgUtPtadq100oEXlJbqpAzhd+cJbvgzSNbcWfcgE6kOWqd9uK
 oeWQWFLCdXLmXf9zCwmk
 =T7R2
 -----END PGP SIGNATURE-----

Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver updates from Olof Johansson:
 "These are changes for drivers that are intimately tied to some SoC and
  for some reason could not get merged through the respective subsystem
  maintainer tree.

  This time around, much of this is for at91, with the bulk of it being
  syscon and udc drivers.

  Also, there's:
   - coupled cpuidle support for Samsung Exynos4210
   - Renesas 73A0 common-clk work
   - of/platform changes to tear down DMA mappings on device destruction
   - a few updates to the TI Keystone knav code"

* tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (26 commits)
  cpuidle: exynos: add coupled cpuidle support for exynos4210
  ARM: EXYNOS: apply S5P_CENTRAL_SEQ_OPTION fix only when necessary
  soc: ti: knav_qmss_queue: change knav_range_setup_acc_irq to static
  soc: ti: knav_qmss_queue: makefile tweak to build as dynamic module
  pcmcia: at91_cf: depend on !ARCH_MULTIPLATFORM
  soc: ti: knav_qmss_queue: export API calls for use by user driver
  of/platform: teardown DMA mappings on device destruction
  usb: gadget: at91_udc: Allocate udc instance
  usb: gadget: at91_udc: Update DT binding documentation
  usb: gadget: at91_udc: Rework for multi-platform kernel support
  usb: gadget: at91_udc: Simplify probe and remove functions
  usb: gadget: at91_udc: Remove non-DT handling code
  usb: gadget: at91_udc: Document DT clocks and clock-names property
  usb: gadget: at91_udc: Drop uclk clock
  usb: gadget: at91_udc: Fix clock names
  mfd: syscon: Add Atmel SMC binding doc
  mfd: syscon: Add atmel-smc registers definition
  mfd: syscon: Add Atmel Matrix bus DT binding documentation
  mfd: syscon: Add atmel-matrix registers definition
  clk: shmobile: fix sparse NULL pointer warning
  ...
2015-02-17 09:38:59 -08:00
Linus Torvalds a233bb742a ARM: SoC DT updates
DT changes continue to be the bulk of our merge window contents.
 
 We continue to have a large set of changes across the board as new platforms
 and drivers are added.
 
 Some of the new platforms are:
 - Alphascale ASM9260
 - Marvell Armada 388
 - CSR Atlas7
 - TI Davinci DM816x
 - Hisilicon HiP01
 - ST STiH418
 
 There have also been some sweeping changes, including relicensing of DTS
 contents from GPL to GPLv2+/X11 so that the same files can be reused in
 other non-GPL projects more easily. There's also been changes to the
 DT Makefile to make it a little less conflict-ridden and churny down
 the road.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJU4u0bAAoJEIwa5zzehBx3XFQP+wbVDp39ay3SRanFWeXqhfTe
 6jRsYrOcq6BN/b1NugjD+yKIYp2MQhwlXbMmj/1vnmJ3XSY25ZMLlgs0/vsNk7W2
 5e0xySwdhd1DjsajhZyN+5gUgqcTgOof/V+CbEUkijDDJ9v/WJbGZrpCHDz+UVTh
 dG9p1vrKoxDELAVbnp9muKZPlaQkAM60zJcHNJw9bJB5M0RCx4XFwPZc1cDLIsIZ
 lK/uYpKsgvgrGw5QuCtEK1/NkqLkBqgBfVg6xq0VB6OCYetqpxqs7kSZjnncIhQc
 PvxShsIJzb/dgfk7xBVb1+4Jfe5L/4poFwS69QuBlr/wiwc7wrhv37edgkyDlclS
 aj5xfOIhQdDaTkknFVs4QEkGAFg/lnTZnmiNiQdlsmDHqbWdTEELKShdVeMO7Zsg
 6bPdDipA2jsQ86UWNwucis8QulzVTuyNuU+Mlrxp73b76+hKXLkbYcZ51FJ/xMD8
 wLpCGqtc9Quirdb7Wy7XiVfesv3lKfDmzZB/6ZJ6zfadDvsqJPxAjNTA8VYZ9YeT
 EyW4K6CMOa5v+sLmIQUsAjKCYaul3PVDCi4voQjpS1ZtPLw+WN3zqX5XZZDT9Ll2
 D1ycmInp/40KsQgjV36u1NlIKMM+oaUJaSzaSPGdgj3Zcw0YZi8O+h0m6iHrlzUB
 uGFufsLKmcOFY/sLwprt
 =XEw1
 -----END PGP SIGNATURE-----

Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC DT updates from Olof Johansson:
 "DT changes continue to be the bulk of our merge window contents.

  We continue to have a large set of changes across the board as new
  platforms and drivers are added.

  Some of the new platforms are:
   - Alphascale ASM9260
   - Marvell Armada 388
   - CSR Atlas7
   - TI Davinci DM816x
   - Hisilicon HiP01
   - ST STiH418

  There have also been some sweeping changes, including relicensing of
  DTS contents from GPL to GPLv2+/X11 so that the same files can be
  reused in other non-GPL projects more easily.  There's also been
  changes to the DT Makefile to make it a little less conflict-ridden
  and churny down the road"

* tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (330 commits)
  ARM: dts: Add PPMU node for exynos4412-trats2
  ARM: dts: Add PPMU node for exynos3250-monk and exynos3250-rinato
  ARM: dts: Add PPMU dt node for exynos4 and exynos4210
  ARM: dts: Add PPMU dt node for exynos3250
  ARM: dts: add mipi dsi device node for exynos4415
  ARM: dts: add fimd device node for exynos4415
  ARM: dts: Add syscon phandle to the video-phy node for Exynos4
  ARM: dts: Add sound nodes for exynos4412-trats2
  ARM: dts: Fix CLK_MOUT_CAMn parent clocks assignment for exynos4412-trats2
  ARM: dts: Fix CLK_UART_ISP_SCLK clock assignment in exynos4x12.dtsi
  ARM: dts: Add max77693 charger node for exynos4412-trats2
  ARM: dts: Switch max77686 regulators to GPIO control for exynos4412-trats2
  ARM: dts: Add suspend configuration for max77686 regulators for exynos4412-trats2
  ARM: dts: Add Maxim 77693 fuel gauge node for exynos4412-trats2
  ARM: dts: am57xx-beagle-x15: Fix USB2 mode
  ARM: dts: am57xx-beagle-x15: Add extcon nodes for USB
  ARM: dts: dra72-evm: Add extcon nodes for USB
  ARM: dts: dra7-evm: Add extcon nodes for USB
  ARM: dts: rockchip: move the hdmi ddc-i2c-bus property to the actual boards
  ARM: dts: rockchip: enable vops and hdmi output on rk3288-firefly and -evb
  ...
2015-02-17 09:36:52 -08:00
Jarkko Nikula f8f87c0362 Revert "ACPI / LPSS: Remove non-existing clock control from Intel Lynxpoint I2C"
Revert commit b893e80e31 ("ACPI / LPSS: Remove non-existing clock control
from Intel Lynxpoint I2C") because it causes touchpad to not load on Dell
XPS13.

Regression is a clear indication that not only some early prototype version
of Lynxpoint I2C but also newer versions can be doing clock gating even
documentation does not state it.

Therefore it is best to revert since this clock gating haven't caused known
issues on those Lynxpoint version which don't do clock gating.

Reported-by-and-tested-by: Chris Rorvick <chris@rorvick.com>
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2015-02-17 18:30:48 +01:00
Scot Doyle 92e4b1bcd6 ACPI / EC: Remove non-standard log emphasis
Remove unusual pr_info() visual emphasis introduced in ad479e7f47
"ACPI / EC: Introduce STARTED/STOPPED flags to replace BLOCKED flag".

Signed-off-by: Scot Doyle <lkml14@scotdoyle.com>
[ rjw: Change pr_info() to pr_debug() too in those places. ]
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2015-02-17 18:27:59 +01:00
Linus Torvalds 878ba61aa9 ARM: SoC platform changes
New and updated SoC support. Also included are some cleanups where the
 platform maintainers hadn't separated cleanups from new developent in
 separate branches.
 
 Some of the larger things worth pointing out:
 
 - A large set of changes from Alexandre Belloni and Nicolas Ferre
   preparing at91 platforms for multiplatform and cleaning up quite a
   bit in the process.
 - Removal of CSR's "Marco" SoC platform that never made it out to the
   market. We love seeing these since it means the vendor published
   support before product was out, which is exactly what we want!
 
 New platforms this release are:
 
 - Conexant Digicolor (CX92755 SoC)
 - Hisilicon HiP01 SoC
 - CSR/sirf Atlas7 SoC
 - ST STiH418 SoC
 - Common code changes for Nvidia Tegra132 (64-bit SoC)
 
 We're seeing more and more platforms having a harder time labelling
 changes as cleanups vs new development -- which is a good sign that
 we've come quite far on the cleanup effort. So over time we might start
 combining the cleanup and new-development branches more.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJU4uiiAAoJEIwa5zzehBx3LtoQAIP4eInJAumhB67MexzWGIBx
 eOsloBRMEBrjBQdSYsdsypN6T61WjDu1aieCxEGzIqitcMa59AIyyzglmlXy3UmV
 XQuSnIBag2fsOqrvqd+c6ewzAMxm2/Nbi3+zjzApkf27NDlBLhEjxuK6pAAf4Yw9
 gyWqB9g0d4V06XdqRInRvyyVfMu6fdApHLnadtjcMdiorQGd1bcOE1sQYygy6N6e
 d6vGvyKSv4ygyDG9//njzm6C5OnmHliimMToeuDC2Scel69RM97EnMXys988CqUH
 0Ru7XANEujtHXSOBYOyCv1kk4V5NguGzlfepe23oidOew8MjUdyRvKrwUiMt3AnT
 SVqcZ9UU5wjJC6j+iADh+E7zww2H0rA6vFRzXy297dDuLg2C2ONFljBj/tIKGc71
 ++gLc6LRn7UmSyK98JMzkxDhmnnPn8w2O0M5GdabAqzZSfHlL1juW9ljp9Al5P6y
 apLRzqMGjEoyC4huXvB3XVfrxGfepe5pco6wVlwmF3ilwf7iHnfuHONC1aw2mPRO
 aOKiS+0gHWL3rNZtZQtyW7Ws0I2HJFip2CWIloBK1/2ntEoh51PH7jGw8iu/6jTk
 //DCXqPBNXcLqonB9CHJZ/EWt0wup0BcHyLjlWX7iEjsdP/QJXrDgnrV3qdHibbh
 AJASjs0YVDcdvRsRStlg
 =szd9
 -----END PGP SIGNATURE-----

Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform changes from Olof Johansson:
 "New and updated SoC support.  Also included are some cleanups where
  the platform maintainers hadn't separated cleanups from new developent
  in separate branches.

  Some of the larger things worth pointing out:

   - A large set of changes from Alexandre Belloni and Nicolas Ferre
     preparing at91 platforms for multiplatform and cleaning up quite a
     bit in the process.

   - Removal of CSR's "Marco" SoC platform that never made it out to the
     market.  We love seeing these since it means the vendor published
     support before product was out, which is exactly what we want!

  New platforms this release are:

   - Conexant Digicolor (CX92755 SoC)
   - Hisilicon HiP01 SoC
   - CSR/sirf Atlas7 SoC
   - ST STiH418 SoC
   - Common code changes for Nvidia Tegra132 (64-bit SoC)

  We're seeing more and more platforms having a harder time labelling
  changes as cleanups vs new development -- which is a good sign that
  we've come quite far on the cleanup effort.  So over time we might
  start combining the cleanup and new-development branches more"

* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (124 commits)
  ARM: at91/trivial: unify functions and machine names
  ARM: at91: remove at91_dt_initialize and machine init_early()
  ARM: at91: change board files into SoC files
  ARM: at91: remove at91_boot_soc
  ARM: at91: move alternative initial mapping to board-dt-sama5.c
  ARM: at91: merge all SOC_AT91SAM9xxx
  ARM: at91: at91rm9200: set idle and restart from rm9200_dt_device_init()
  ARM: digicolor: select syscon and timer
  ARM: zynq: Simplify SLCR initialization
  ARM: zynq: PM: Fixed simple typo.
  ARM: zynq: Setup default gpio number for Xilinx Zynq
  ARM: digicolor: add low level debug support
  ARM: initial support for Conexant Digicolor CX92755 SoC
  ARM: OMAP2+: Add dm816x hwmod support
  ARM: OMAP2+: Add clock domain support for dm816x
  ARM: OMAP2+: Add board-generic.c entry for ti81xx
  ARM: at91: pm: remove warning to remove SOC_AT91SAM9263 usage
  ARM: at91: remove unused mach/system_rev.h
  ARM: at91: stop using HAVE_AT91_DBGUx
  ARM: at91: fix ordering of SRAM and PM initialization
  ...
2015-02-17 09:27:54 -08:00
David Howells e59b4e9187 debugfs: Provide a file creation function that also takes an initial size
Provide a file creation function that also takes an initial size so that the
caller doesn't have to set i_size, thus meaning that we don't have to call
deal with ->d_inode in the callers.

Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2015-02-17 12:21:51 -05:00
Linus Torvalds ea7531ac4a ARM: SoC cleanups
This is a good healthy set of various code removals. Total net delta is 8100
 lines removed.
 
 Among the larger cleanups are:
 
 - Removal of old Samsung S3C DMA infrastructure by Arnd
 - Removal of the non-DT version of the 'lager' board by Magnus Damm
 - General stale code removal on OMAP and Davinci by Rickard Strandqvist
 - Removal of non-DT support on am3517 platforms by Tony Lindgren
 
 ... plus several other cleanups of various platforms across the board.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJU4uYeAAoJEIwa5zzehBx3v58P/RGKt5e4CgCdHKjVhbPmADSE
 FVECT4qrIkf4dFgU5qPCBDCtQn/B3ljxZnq6Hqi8VxYD+pRcXt94R50ZyhGUZ6QF
 GLXU8jDSlY906uJwW+CHZFVLmDjTM4ONLn1ZMRtcdOrU3yGC5rZq9+Kla6ZIE6jb
 mUAFMj6e+NBPYDonq93G7968EdyLJOtK4B2ylPW0+wgSRGIEPibCiNi9yyN4hBFr
 LiaOyY/execKUo2K2BFWkfAZWt7GrwBu/qAkz/9YDRDiikLwFG2UBWbaik5Fj8tf
 v8wvpL6Af6iLpRx1wI/HoCgjFS/g/n4O3svMe7aHGyfrkEAxNtoCKlFscO8w/aLc
 eABNAb5j65it8IHvQMR5RhgqWoQe4XMlDcwsxotTe64GfxpTahdhDmhk7RKAY9Xq
 MyITvtZPTPHTSZHNEDE3HtgHn62ndSinYFhdTaBi2FQxLNCUFl2TKZxpb0r65JI/
 2yOf6hcgWGTgV1VOruAc5SHcSkQOY3SptM4n4F1B0VcDrCphBDYhRTdokELFJIIq
 I47Week8o0f+a4ot/sf0QhU68wVZENgUJO3/Q5Buta+UGSZa4NYH7Ymc159e7hGS
 k+7mCeTJC85F0H/EBWvCcZzbpwiq7jBRAY2PhqYF1EQkefdR/+28o1sX090fVaXD
 n0gXv3/ZDvJB2ryv8lR/
 =tsjK
 -----END PGP SIGNATURE-----

Merge tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC cleanups from Olof Johansson:
 "This is a good healthy set of various code removals.  Total net delta
  is 8100 lines removed.

  Among the larger cleanups are:

   - Removal of old Samsung S3C DMA infrastructure by Arnd
   - Removal of the non-DT version of the 'lager' board by Magnus Damm
   - General stale code removal on OMAP and Davinci by Rickard Strandqvist
   - Removal of non-DT support on am3517 platforms by Tony Lindgren

  ... plus several other cleanups of various platforms across the board"

* tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (47 commits)
  ARM: sirf: drop redundant function and marco declaration
  arm: omap: specify PMUs are for ARMv7 CPUs
  arm: shmobile: specify PMUs are for ARMv7 CPUs
  arm: iop: specify PMUs are for XScale CPUs
  arm: pxa: specify PMUs are for XScale CPUs
  arm: realview: specify PMU types
  ARM: SAMSUNG: remove unused DMA infrastructure
  ARM: OMAP3: Add back Kconfig option MACH_OMAP3517EVM for ASoC
  ARM: davinci: Remove CDCE949 driver
  ARM: at91: remove useless at91rm9200_set_type()
  ARM: at91: remove useless at91rm9200_dt_initialize()
  ARM: at91: move debug-macro.S into the common space
  ARM: at91: remove useless at91_sysirq_mask_rtx
  ARM: at91: remove useless config MACH_AT91SAM9_DT
  ARM: at91: remove useless config MACH_AT91RM9200_DT
  ARM: at91: remove unused mach/memory.h
  ARM: at91: remove useless header file includes
  ARM: at91: remove unneeded header file
  rtc: at91/Kconfig: remove useless options
  ARM: at91/Documentation: add a README for Atmel SoCs
  ...
2015-02-17 09:17:33 -08:00
Linus Torvalds 4025fa97ff ARM: SoC non-critical fixes
Here's a small collection of fixes accrued during the last release that weren't
 considered severe enough to merge during the -rc series.
 
 A few of these are around resurrecting TI81xx support that's been broken for
 quite a while, the rest are smaller fixes -- most for PXA but a few across
 the board.
 
 There are also some updates to MAINTAINERS here, in particular for Broadcom
 platforms.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJU4uShAAoJEIwa5zzehBx3SW0P/1T19Tnx2D18/c2rFvyNl3N3
 09emcSZZ2xPKlmt0y6kpbyvV5X8zM/0JjH61DVJGYHeMMHTuhk8evy9ptfXTXkGp
 GskrIla2jozSaei45lsx7uy9Cz/FtxQSQ9SqBTfOBlvL8yekEJ9/ZPsL7tqRvTQa
 OllOR7RztcjkO/A9FjrSqlEwY6Ckduv6lKjfuXaGmx88sMMQt7hmgM+x5sgzJnss
 5BHYOhXXYODh6KHJRQqG0fi5j2vOrWSw18dro6HwZPN3TlsmeFYkkOV9bOgJiBQz
 TYXoFTnIwYLaBaVVzIrQO1fmyVmxlFjSRvs3BY++a142VPjxkXmh7KNWYwLKEtXH
 cVET4jtKHVQVOEo9pbx3E5Fjlcj/VKJDPqdnTvCXV9OjpCDLP9bT0EfXRmjmWiab
 oUQDW3o+VEY4INBnsRJ6yL3iXelU26U/XMTZxWuZRo3m1ArF4yTUdzMUjQGYyRW6
 rGnLYZU6wO8cc61IG3It8bq58MZx1DDtP3knjf3lDfcFv62AA2dNcN75vkdeKar3
 ndFqtKwr3OZ+NuSgGASxfMOGEi2uMZborI+hzaXy/aTefSN0gUSFR1Kpy05Q4aKA
 D0mZ+JF8gArZMqXfAqGbYD/mgT293UWKS2kIlyfAviJS9oMxT5oFE/TpTIpCT1gv
 pi5ydJMFmD7X5A0w6wik
 =YCX1
 -----END PGP SIGNATURE-----

Merge tag 'fixes-non-critical-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC non-critical fixes from Olof Johansson:
 "Here's a small collection of fixes accrued during the last release
  that weren't considered severe enough to merge during the -rc series.

  A few of these are around resurrecting TI81xx support that's been
  broken for quite a while, the rest are smaller fixes -- most for PXA
  but a few across the board.

  There are also some updates to MAINTAINERS here, in particular for
  Broadcom platforms"

* tag 'fixes-non-critical-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (23 commits)
  MAINTAINERS: fix git repositories for Broadcom SoCs
  ARM: pxa: fix broken isa interrupts for zeus and viper
  ARM: DRA7: hwmod: Fix boot crash with DEBUG_LL enabled on UART3
  ARM: OMAP: DRA7: hwmod: Make gpmc software supervised as the smart idle is broken
  ARM: AM43xx: hwmod: set DSS submodule parent hwmods
  ARM: OMAP2+: hwmod: print error if wait_target_ready() failed
  MAINTAINERS: add maintainer for OMAP hwmod data
  ARM: OMAP2+: Disable omap3 PM init for ti81xx
  ARM: OMAP2+: Fix reboot for 81xx
  ARM: OMAP2+: Fix dm814 and dm816 for clocks and timer init
  ARM: OMAP2+: Fix ti81xx class type
  ARM: OMAP2+: Fix ti81xx devtype
  ARM: OMAP2+: Fix error handling for omap2_clk_enable_init_clocks
  MAINTAINERS: add a git entry for BMIPS-based BCM7xxx SoCs
  MAINTAINERS: add a git entry for BCM7xxx ARM-based SoCs
  MAINTAINERS: update Broadcom Cygnus SoC git tree
  MAINTAINERS: move BCM63xx ARM-based SoCs git tree
  hx4700: regulator: declare full constraints
  ARM: pxa: add regulator_has_full_constraints to spitz board file
  ARM: pxa: add regulator_has_full_constraints to poodle board file
  ...
2015-02-17 09:15:46 -08:00
Linus Torvalds c397f8fa43 Merge branch 'akpm' (patches from Andrew)
Merge fifth set of updates from Andrew Morton:

 - A few things which were awaiting merges from linux-next:
     - rtc
     - ocfs2
     - misc others

 - Willy's "dax" feature: direct fs access to memory (mainly NV-DIMMs)
   which isn't backed by pageframes.

* emailed patches from Andrew Morton <akpm@linux-foundation.org>: (37 commits)
  rtc: add driver for DS1685 family of real time clocks
  MAINTAINERS: add entry for Maxim PMICs on Samsung boards
  lib/Kconfig: use bool instead of boolean
  powerpc: drop _PAGE_FILE and pte_file()-related helpers
  ocfs2: set append dio as a ro compat feature
  ocfs2: wait for orphan recovery first once append O_DIRECT write crash
  ocfs2: complete the rest request through buffer io
  ocfs2: do not fallback to buffer I/O write if appending
  ocfs2: allocate blocks in ocfs2_direct_IO_get_blocks
  ocfs2: implement ocfs2_direct_IO_write
  ocfs2: add orphan recovery types in ocfs2_recover_orphans
  ocfs2: add functions to add and remove inode in orphan dir
  ocfs2: prepare some interfaces used in append direct io
  MAINTAINERS: fix spelling mistake & remove trailing WS
  dax: does not work correctly with virtual aliasing caches
  brd: rename XIP to DAX
  ext4: add DAX functionality
  dax: add dax_zero_page_range
  ext2: get rid of most mentions of XIP in ext2
  ext2: remove ext2_aops_xip
  ...
2015-02-17 08:38:30 -08:00
Ray Jui e6e5dd3566 i2c: iproc: Add Broadcom iProc I2C Driver
Add initial support to the Broadcom iProc I2C controller found in the
iProc family of SoCs.

The iProc I2C controller has separate internal TX and RX FIFOs, each has
a size of 64 bytes. The iProc I2C controller supports two bus speeds
including standard mode (100kHz) and fast mode (400kHz)

Signed-off-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Reviewed-by: Kevin Cernekee <cernekee@chromium.org>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-02-17 16:44:13 +01:00
Andy Shevchenko a93ac5786d i2c: designware-pci: update Intel copyright line
While here, fix few indentations issues across the code. There is no functional
change.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-02-17 16:42:43 +01:00
Markos Chandras f296e7c48d MIPS: Add Malta QEMU 32R6 defconfig
Add a Malta defconfig for the 32-bit MIPS R6 core as emulated
by QEMU.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:39 +00:00
Markos Chandras 575509b647 MIPS: Malta: Add support for building MIPS R6 kernel
The Malta platform supports MIPS R6 (via QEMU or real bitstreams)
so add support for it.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:39 +00:00
Markos Chandras 46490b5725 MIPS: kernel: elf: Improve the overall ABI and FPU mode checks
The previous implementation did not cover all possible FPU combinations
and it silently allowed ABI incompatible objects to be loaded with the
wrong ABI. For example, the previous logic would set the FP_64 ABI as
the matching ABI for an FP_XX object combined with an FP_64A object.
This was wrong, and the matching ABI should have been FP_64A.
The previous logic is now replaced with a new one which determines
the appropriate FPU mode to be used rather than the FP ABI. This has
the advantage that the entire logic is much simpler since it is the FPU
mode we are interested in rather than the FP ABI resulting to code
simplifications. This also removes the now obsolete FP32XX_HYBRID_FPRS
option.

Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:39 +00:00
Markos Chandras 6134d94923 MIPS: asm: fpu: Allow 64-bit FPU on MIPS32 R6
MIPS32 R6 has a 64-bit FPU so add the necessary MIPS R6
definition.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:38 +00:00
Markos Chandras 13e45f0957 MIPS: kernel: process: Do not allow FR=0 on MIPS R6
A prctl() call to set FR=0 for MIPS R6 should not be allowed
since FR=1 is the only option for R6 cores.

Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Matthew Fortune <matthew.fortune@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:38 +00:00
Markos Chandras e0d32f33e6 MIPS: Handle MIPS IV, V and R2 FPU instructions on MIPS R6 as well
MIPS R2 FPU instructions are also present in MIPS R6 so amend the
preprocessor definitions to take MIPS R6 into consideration.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:37 +00:00
Markos Chandras 7c151d3d5d MIPS: Make use of the ERETNC instruction on MIPS R6
The ERETNC instruction, introduced in MIPS R5, is similar to the ERET
one, except it does not clear the LLB bit in the LLADDR register.
This feature is necessary to safely emulate R2 LL/SC instructions.
However, on context switches, we need to clear the LLAddr/LLB bit
in order to make sure that an SC instruction from the new thread
will never succeed if it happens to interrupt an LL operation on the
same address from the previous thread.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:37 +00:00
Leonid Yegoshin b0a668fb20 MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6
MIPS R6 removed quite a few R2 instructions. However, there
is plenty of <R6 userland code so we add an in-kernel emulator
so we can still be able to execute all R2 userland out there.

The emulator comes with a handy debugfs under /mips/ directory
(r2-emul-stats) to provide some basic statistics of the
instructions that are being emulated.

Below are some statistics from booting a minimal buildroot image:

Instruction     Total   BDslot
------------------------------
movs            236969  0
hilo            56686   0
muls            55279   0
divs            10941   0
dsps            0       0
bops            1       0
traps           0       0
fpus            0       0
loads           214981  17
stores          103364  0
llsc            56898   0
dsemul          150418  0
jr              370158
bltzl           43
bgezl           1594
bltzll          0
bgezll          0
bltzal          39
bgezal          39
beql            14503
bnel            138741
blezl           0
bgtzl           3988

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:37 +00:00
Markos Chandras b55b9e2715 MIPS: asm: mipsregs: Add support for the LLADDR register
If Config5/LLB is set in the core, then software can write the LLB
bit in the LLADDR register.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:36 +00:00
Markos Chandras 5aed9da128 MIPS: Add LLB bit and related feature for the Config 5 CP0 register
The LLBIT (bit 4) in the Config5 CP0 register indicates the software
availability of the Load-Linked bit. This bit is only set by hardware
and it has the following meaning:

0: LLB functionality is not supported
1: LLB functionality is supported. The following feature are also
supported:

- ERETNC instruction. Similar to ERET but it does not clear the LLB
bit in the LLAddr register.
- CP0 LLAddr/LLB bit must be set
- LLbit is software accessible through the LLAddr[0]

This will be used later on to emulate R2 LL/SC instructions.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:36 +00:00
Markos Chandras 28d6f93d20 MIPS: Emulate the new MIPS R6 BNEZC and JIALC instructions
MIPS R6 uses the <R6 sdc2 opcode for the new BNEZC and JIALC instructions

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:35 +00:00
Markos Chandras 69b9a2fd05 MIPS: Emulate the new MIPS R6 BEQZC and JIC instructions
MIPS R6 uses the <R6 ldc2 opcode for the new BEQZC and JIC instructions

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:35 +00:00
Markos Chandras 84fef63012 MIPS: Emulate the new MIPS R6 BALC instruction
MIPS R6 uses the <R6 swc2 opcode for the new BALC instructions.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:35 +00:00
Markos Chandras 10d962d534 MIPS: Emulate the new MIPS R6 BNVC, BNEC and BNEZLAC instructions
MIPS R6 uses the <R6 DADDI opcode for the new BNVC, BNEC and
BNEZLAC instructions.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:34 +00:00
Markos Chandras c893ce38b2 MIPS: Emulate the new MIPS R6 BOVC, BEQC and BEQZALC instructions
MIPS R6 uses the <R6 ADDI opcode for the new BOVC, BEQC and
BEQZALC instructions.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:34 +00:00
Markos Chandras 8467ca0122 MIPS: Emulate the new MIPS R6 branch compact (BC) instruction
MIPS R6 uses the <R6 LWC2 opcode for the new BC instruction.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:34 +00:00
Markos Chandras f1b44067c1 MIPS: Emulate the new MIPS R6 B{L,G}T{Z,}{AL,}C instructions
MIPS R6 added the following four instructions which share the
BGTZ and BGTZL opcode:

BLTZALC: Compact branch-and-link if GPR rt is < to zero
BGTZALC: Compact branch-and-link if GPR rt is > to zero
BLTZL  : Compact branch if GPR rt is < to zero
BGTZL  : Compact branch if GPR rt is > to zero
BLTC   : Compact branch if GPR rs is less than GPR rt
BLTUC  : Similar to BLTC but unsigned

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:33 +00:00
Markos Chandras a8ff66f52d MIPS: Emulate the new MIPS R6 B{L,G}Ε{Z,}{AL,}C instructions
MIPS R6 added the following four instructions which share the
BLEZ and BLEZL opcodes:

BLEZALC: Compact branch-and-link if GPR rt is <= to zero
BGEZALC: Compact branch-and-link if GPR rt is >= to zero
BLEZC  : Compact branch if GPR rt is <= to zero
BGEZC  : Compact branch if GPR rt is >= to zero
BGEC   : Compact branch if GPR rs is less than or equal to GPR rt
BGEUC  : Similar to BGEC but unsigned.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:33 +00:00
Markos Chandras c8a34581ec MIPS: Emulate the BC1{EQ,NE}Z FPU instructions
MIPS R6 introduced the following two branch instructions for COP1:

BC1EQZ: Branch if Cop1 (FPR) Register Bit 0 is Equal to Zero
BC1NEZ: Branch if Cop1 (FPR) Register Bit 0 is Not Equal to Zero

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:32 +00:00
Markos Chandras 319824eabc MIPS: kernel: branch: Do not emulate the branch likelies on MIPS R6
MIPS R6 removed the BLTZL, BGEZL, BLTZAL, BGEZAL, BEQL, BNEL, BLEZL,
BGTZL branch likely instructions so we must not try to emulate them on
MIPS R6 if the R2-to-R6 emulator is not present.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:32 +00:00
Markos Chandras 5f9f41c474 MIPS: kernel: Prepare the JR instruction for emulation on MIPS R6
The MIPS R6 JR instruction is an alias to the JALR one, so it may
need emulation for non-R6 userlands.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:31 +00:00
Markos Chandras b5ad2c2193 MIPS: mm: scache: Add secondary cache support for MIPS R6 cores
The secondary cache initialization and configuration code is processor
specific so we need to handle MIPS R6 cores as well.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:31 +00:00
Markos Chandras 4ee486274e MIPS: mm: c-r4k: Set the correct ISA level
The local_r4k_flush_cache_sigtramp function uses the 'cache'
instruction inside an asm block. However, MIPS R6 changed the
opcode for the cache instruction and as a result of which we
need to set the correct ISA level.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:31 +00:00
Leonid Yegoshin 77f3ee59ee MIPS: mm: tlbex: Use cpu_has_mips_r2_exec_hazard for the EHB instruction
MIPS uses the cpu_has_mips_r2_exec_hazard macro to determine whether the
EHB instruction is available or not. This is necessary for MIPS R6
which also supports the EHB instruction.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:30 +00:00
Markos Chandras d2e6d30ad1 MIPS: mm: page: Add MIPS R6 support
The MIPS R6 pref instruction only has 9 bits for the immediate
field so skip the micro-assembler PREF instruction if the offset
does not fit in 9 bits. Moreover, bit 30 (Pref_PrepareForStore) is
no longer valid in MIPS R6, so we change the default for all MIPS R6
processors to bit 5 (Pref_StoreStreamed).

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:30 +00:00
Leonid Yegoshin 8c56208aff MIPS: lib: memset: Add MIPS R6 support
MIPS R6 dropped the unaligned load and store instructions so
we need to re-write this part of the code for R6 to store
one byte at a time.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:30 +00:00
Leonid Yegoshin b0ce4bd535 MIPS: lib: memcpy: Add MIPS R6 support
MIPS R6 does not support the unaligned load and store instructions
so we add a special MIPS R6 case to copy one byte at a time if we
need to read/write to unaligned memory addresses.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:29 +00:00
Markos Chandras fee313d4b8 MIPS: kernel: syscall: Set the appropriate ISA level for MIPS R6
MIPS R6 changed the opcodes for LL/SC instructions so we need to set
the appropriate ISA level.

Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:29 +00:00
Leonid Yegoshin 0593a44c64 MIPS: kernel: unaligned: Add support for the MIPS R6
The load/store unaligned instructions have been removed in MIPS R6
so we need to re-implement the related macros using the regular
load/store instructions. Moreover, the load/store from coprocessor 2
instructions have been reallocated in Release 6 so we will handle them
in the emulator instead.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:28 +00:00
Markos Chandras acac4108df MIPS: kernel: cps-vec: Replace "addi" with "addiu"
The "addi" instruction will trap on overflows which is not something
we need in this code, so we replace that with "addiu".

Link: http://www.linux-mips.org/archives/linux-mips/2015-01/msg00430.html
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: <stable@vger.kernel.org> # v3.15+
Cc: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:28 +00:00
Markos Chandras 938c12824b MIPS: kernel: genex: Set correct ISA level
The jr instruction opcode has changed in R6 so make sure
the correct ISA level is set prior using that instruction.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:28 +00:00
Leonid Yegoshin 8d5b9b771e MIPS: kernel: r4k_fpu: Add support for MIPS R6
Add the MIPS R6 related preprocessor definitions for FPU signal
related functions. MIPS R6 only has FR=1 so avoid checking that
bit on the C0/Status register.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2015-02-17 15:37:27 +00:00