Граф коммитов

6 Коммитов

Автор SHA1 Сообщение Дата
Max Filippov 2eabc1800d xtensa: nommu: set up cache and atomctl in initialize_mmu
initialize_mmu sets up atomctl SR which is needed for s32c1i to function
correctly even in noMMU configurations. It's also a good place to set up
caching attributes of physical memory.

Allow enabling INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX in noMMU
configurations for setting up atomctl and cache attributes.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-10-21 13:28:56 +04:00
Max Filippov 53490121e9 xtensa: move vecbase SR initialization to _startup
Instead of initializing vecbase in initialize_mmu macro, which may be
expanded either in Image.elf reset vector hadler or in the kernel
head.S, both times only when CONFIG_MMU is enabled, do this
initialization once in _startup function.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-10-21 13:28:55 +04:00
Baruch Siach 6cb971114f xtensa: remap io area defined in device tree
Use the simple-bus node to discover the io area, and remap the cached and
bypass io ranges. The parent-bus-address value of the first triplet in the
"ranges" property is used. This value is rounded down to the nearest 256MB
boundary. The length of the io area is fixed at 256MB; the "ranges" property
length value is ignored.

Other limitations: (1) only the first simple-bus node is considered, and (2)
only the first triplet of the "ranges" property is considered.

See ePAPR 1.1 §6.5 for the simple-bus node description, and §2.3.8 for the
"ranges" property description.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-01-15 00:25:14 +04:00
Baruch Siach 4809bb468f xtensa: avoid duplicate of IO range definitions
Define IO addresses in a single place, to make it easier to change for
non-standard memory maps.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-01-15 00:21:24 +04:00
Max Filippov e85e335f8f xtensa: add MMU v3 support
MMUv3 comes out of reset with identity vaddr -> paddr mapping in the TLB
way 6:

Way 6 (512 MB)
        Vaddr       Paddr       ASID  Attr RWX Cache
        ----------  ----------  ----  ---- --- -------
        0x00000000  0x00000000  0x01  0x03 RWX Bypass
        0x20000000  0x20000000  0x01  0x03 RWX Bypass
        0x40000000  0x40000000  0x01  0x03 RWX Bypass
        0x60000000  0x60000000  0x01  0x03 RWX Bypass
        0x80000000  0x80000000  0x01  0x03 RWX Bypass
        0xa0000000  0xa0000000  0x01  0x03 RWX Bypass
        0xc0000000  0xc0000000  0x01  0x03 RWX Bypass
        0xe0000000  0xe0000000  0x01  0x03 RWX Bypass

This patch adds remapping code at the reset vector or at the kernel
_start (depending on CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX) that
reconfigures MMUv3 as MMUv2:

Way 5 (128 MB)
        Vaddr       Paddr       ASID  Attr RWX Cache
        ----------  ----------  ----  ---- --- -------
        0xd0000000  0x00000000  0x01  0x07 RWX WB
        0xd8000000  0x00000000  0x01  0x03 RWX Bypass
Way 6 (256 MB)
        Vaddr       Paddr       ASID  Attr RWX Cache
        ----------  ----------  ----  ---- --- -------
        0xe0000000  0xf0000000  0x01  0x07 RWX WB
        0xf0000000  0xf0000000  0x01  0x03 RWX Bypass

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:09 -07:00
Max Filippov c622b29d1f xtensa: initialize atomctl SR
In order to use S32C1I instruction on cores with ATOMCTL SR the register
must be properly initialized.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2012-12-18 21:10:22 -08:00