Граф коммитов

19 Коммитов

Автор SHA1 Сообщение Дата
Greg Kroah-Hartman 5471a81235 phy-for-5.14 version 2
- Updates:
         - Yaml conversion for renesas,rcar-gen3 pcie phy and
           rockchip-usb-phy bindings
         - Support for devm_phy_get() taking NULL phy name
 
   - New support:
         - PCIe phy for Qualcomm IPQ60xx
         - PCIe phy for Qualcomm SDX55
         - USB phy for RK3308
         - CAN transceivers phy for TI TCAN104x
         - Innosilicon-based CSI dphy for rockchip
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEE+vs47OPLdNbVcHzyfBQHDyUjg0cFAmDS5/MACgkQfBQHDyUj
 g0cMZhAAjtAeYe7R8r2M8NACd2HRnBMBcHFJtz6Os7ZZa4dRMLyq6TkStZ8k1Mat
 2dEUb3Wb8G18WqECXUlcJp/CYlK1ea1GDwgTLd09tGo7PAn6p3RBG7ujf+aCWoil
 TLhsE9Sb7d3pr8qVsy6DQc/TIWxfCTeqZrIRzt2UQXxK6P/3CtdN1g/TEdq1r/h9
 A/xkDnyT2QQOJTgFMUh9RF85vXfptm9+gVxNdgyHGVvdaEhSURUytEfubrQYjd1P
 sM5BhsNPEKHqL/kYlgMAgnENtQBrXBwfEzP02M32zyhTLvaZMcV87Z8LXxmrPDn/
 jtYLlSYTQTDKA9tHBw1W8NogaLS9INeTjDhqt0hBsT/lh1vL5KMk0IGsSxUaJ27h
 6on3NmjsxI/HKosdrQzRizURS0xixOWDnZN7UPFaHFJbA8GMIlQlDidZOJTl87cc
 inIuSdB29YA0FNGbXOq/HR3y1qChlwAewxFYCzFtKfuHmZWJNy7osUvQNHodEAGl
 BGjerYgJUNNiWlxmoggUcLtAdbqYVH8fvvz3WUyClUePVqioX8gS6UDRx8LrgGV2
 FvLSKgetbqH3iQtRO+2RtwMJEMmC3eW7esjUv/fEgKym+2JvORpE0p2n5sWTgRMc
 VWFDVqOp5JJXmarRkly2MMppO5x25d3wE9DLR0/Re7hNPGUsz4M=
 =Col+
 -----END PGP SIGNATURE-----

Merge tag 'phy-for-5.14_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into char-misc-next

Vinod writes:

phy-for-5.14 version 2

  - Updates:
        - Yaml conversion for renesas,rcar-gen3 pcie phy and
          rockchip-usb-phy bindings
        - Support for devm_phy_get() taking NULL phy name

  - New support:
        - PCIe phy for Qualcomm IPQ60xx
        - PCIe phy for Qualcomm SDX55
        - USB phy for RK3308
        - CAN transceivers phy for TI TCAN104x
        - Innosilicon-based CSI dphy for rockchip

* tag 'phy-for-5.14_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (36 commits)
  phy: Revert "phy: ralink: Kconfig: convert mt7621-pci-phy into 'bool'"
  phy: ti: dm816x: Fix the error handling path in 'dm816x_usb_phy_probe()
  phy: uniphier-pcie: Fix updating phy parameters
  phy/rockchip: add Innosilicon-based CSI dphy
  dt-bindings: phy: add yaml binding for rockchip-inno-csi-dphy
  phy: rockchip: remove redundant initialization of pointer cfg
  phy: phy-can-transceiver: Add support for generic CAN transceiver driver
  dt-bindings: phy: Add binding for TI TCAN104x CAN transceivers
  phy: core: Reword the comment specifying the units of max_link_rate to be Mbps
  phy: phy-mtk-hdmi: Remove redundant dev_err call in mtk_hdmi_phy_probe()
  phy: phy-mtk-mipi-dsi: Remove redundant dev_err call in mtk_mipi_tx_probe()
  phy: phy-mmp3-hsic: Remove redundant dev_err call in mmp3_hsic_phy_probe()
  phy: bcm-ns-usb3: Remove redundant dev_err call in bcm_ns_usb3_mdio_probe()
  MAINTAINERS: update marvell,armada-3700-utmi-phy.yaml reference
  phy: phy-twl4030-usb: use DEVICE_ATTR_RO macro
  dt-bindings: phy: convert rockchip-usb-phy.txt to YAML
  phy: phy-rockchip-inno-usb2: add support for RK3308 USB phy
  dt-bindings: phy: rockchip-inno-usb2: add compatible for rk3308 USB phy
  phy: stm32: manage optional vbus regulator on phy_power_on/off
  dt-bindings: phy: add vbus-supply optional property to phy-stm32-usbphyc
  ...
2021-06-23 10:33:34 +02:00
Vinod Koul 15692a80d9 phy: Revert "phy: ralink: Kconfig: convert mt7621-pci-phy into 'bool'"
This reverts commit 6eded551ce ("phy: ralink: Kconfig: convert
mt7621-pci-phy into 'bool'") as we don't want drivers to be built in and
should be a module instead

Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-06-23 12:59:46 +05:30
Sergio Paracuellos d6e9e8e5dd phy: ralink: phy-mt7621-pci: drop 'of_match_ptr' to fix -Wunused-const-variable
The of_device_id is included unconditionally by of.h header and used
in the driver as well. Remove of_match_ptr to fix W=1 compile test
warning with !CONFIG_OF:

drivers/phy/ralink/phy-mt7621-pci.c:341:34: warning: unused variable 'mt7621_pci_phy_ids' [-Wunused-const-variable]

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210603043219.32646-1-sergio.paracuellos@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-06-03 11:18:14 +05:30
Sergio Paracuellos 652a6a2e38 phy: ralink: phy-mt7621-pci: properly print pointer address
The way of printing the pointer address for the 'port_base'
address got into compile warnings on some architectures
[-Wpointer-to-int-cast]. Instead of use '%08x' and cast
to an 'unsigned int' just make use of '%px' and avoid the
cast. To avoid not really needed driver verbosity on normal
behaviour change also from 'dev_info' to 'dev_dbg'.

Fixes: d87da32372 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210508070930.5290-7-sergio.paracuellos@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-05-14 16:16:29 +05:30
Sergio Paracuellos 6eded551ce phy: ralink: Kconfig: convert mt7621-pci-phy into 'bool'
Make dependent on PCI_MT7621 configuration option and mark
this pci phy configuration as bool which has more sense.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210508070930.5290-6-sergio.paracuellos@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-05-14 16:16:29 +05:30
Sergio Paracuellos 28dcfba1a0 phy: ralink: Kconfig: enable COMPILE_TEST on mt7621-pci-phy driver
After use the clock apis and avoid custom architecture
code this driver can properly be enabled for COMPILE_TEST.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210508070930.5290-5-sergio.paracuellos@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-05-14 16:16:29 +05:30
Sergio Paracuellos 60ece833cc phy: ralink: phy-mt7621-pci: use kernel clock APIS
MT7621 SoC clock driver has already mainlined in
'commit 48df7a26f4 ("clk: ralink: add clock driver for mt7621 SoC")'
This allow us to properly use kernel clock apis to get
the clock frequency needed for the phy configuration
instead of use custom architecture code to do the same.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210508070930.5290-4-sergio.paracuellos@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-05-14 16:16:28 +05:30
Wei Yongjun b976c98751 phy: ralink: phy-mt7621-pci: fix return value check in mt7621_pci_phy_probe()
Fix the return value check which testing the wrong variable
in mt7621_pci_phy_probe().

Fixes: d87da32372 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210305034931.3237558-1-weiyongjun1@huawei.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30 23:35:17 +05:30
Sergio Paracuellos 982313c38f phy: ralink: phy-mt7621-pci: fix XTAL bitmask
When this was rewriten to get mainlined and start to
use 'linux/bitfield.h' headers, XTAL_MASK was wrong.
It must mask three bits but only two were used. Hence
properly fix it to make things work.

Fixes: d87da32372 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY")
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210302105412.16221-1-sergio.paracuellos@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30 23:35:17 +05:30
Sergio Paracuellos 8145dcb07d phy: ralink: phy-mt7621-pci: set correct name in MODULE_DEVICE_TABLE macro
Correct name passed into 'MODULE_DEVICE_TABLE' which was wrong and
was showing a warning when the driver is enabled for 'COMPILE_TEST'.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20201201112051.17463-3-sergio.paracuellos@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-12-01 17:14:41 +05:30
Sergio Paracuellos 0e055d179e phy: ralink: phy-mt7621-pci: drop 'COMPILE_TEST' from Kconfig
This driver includes the following two files directly:
- mt7621.h
- ralink_regs.h

Compilation for its related platform properly works because
its real path is included in 'arch/mips/ralink/Platform' as
cflags.

This driver depends on RALINK but also is enabled for COMPILE_TEST
where nothing about its platform is known and this directly
included files are not found at all breaking compilation.

If we want 'COMPILE_TEST' we have to change cflags also inside
'phy/ralink' subdirectory Makefile which seems that does not
like to linux-phy maintainers. Hence remove COMPILE_TEST from
Kconfig to avoid the problem.

Fixes: d87da32372 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY")
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20201201112051.17463-2-sergio.paracuellos@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-12-01 17:14:41 +05:30
Sergio Paracuellos d87da32372 phy: ralink: Add PHY driver for MT7621 PCIe PHY
This patch adds a driver for the PCIe PHY of MT7621 SoC.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20201121155037.21354-3-sergio.paracuellos@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-30 16:18:24 +05:30
Chunfeng Yun fc5662127a phy: phy-ralink-usb: convert to devm_platform_ioremap_resource
Use devm_platform_ioremap_resource to simplify code

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Link: https://lore.kernel.org/r/1604642930-29019-11-git-send-email-chunfeng.yun@mediatek.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16 12:47:47 +05:30
Rikard Falkeborn d6541a86ec phy: ralink-usb: Constify ralink_usb_phy_ops
The only usage is to pass its address to devm_phy_create() which takes a
const pointer. Make it const to allow the compiler to put it in
read-only memory.

Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Link: https://lore.kernel.org/r/20200823220025.17588-7-rikard.falkeborn@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-08-31 14:36:37 +05:30
Thomas Gleixner c942fddf87 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157
Based on 3 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation either version 2 of the license or at
  your option any later version this program is distributed in the
  hope that it will be useful but without any warranty without even
  the implied warranty of merchantability or fitness for a particular
  purpose see the gnu general public license for more details

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation either version 2 of the license or at
  your option any later version [author] [kishon] [vijay] [abraham]
  [i] [kishon]@[ti] [com] this program is distributed in the hope that
  it will be useful but without any warranty without even the implied
  warranty of merchantability or fitness for a particular purpose see
  the gnu general public license for more details

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation either version 2 of the license or at
  your option any later version [author] [graeme] [gregory]
  [gg]@[slimlogic] [co] [uk] [author] [kishon] [vijay] [abraham] [i]
  [kishon]@[ti] [com] [based] [on] [twl6030]_[usb] [c] [author] [hema]
  [hk] [hemahk]@[ti] [com] this program is distributed in the hope
  that it will be useful but without any warranty without even the
  implied warranty of merchantability or fitness for a particular
  purpose see the gnu general public license for more details

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-or-later

has been chosen to replace the boilerplate/reference in 1105 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Richard Fontana <rfontana@redhat.com>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070033.202006027@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-30 11:26:37 -07:00
Thomas Gleixner ec8f24b7fa treewide: Add SPDX license identifier - Makefile/Kconfig
Add SPDX license identifiers to all Make/Kconfig files which:

 - Have no license information of any form

These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:

  GPL-2.0-only

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-21 10:50:46 +02:00
Masahiro Yamada bb0e500bed phy: add 'depends on HAS_IOMEM' to fix unmet dependency
These configs select MFD_SYSCON, but do not depend on HAS_IOMEM.

Compile testing on architecture without HAS_IOMEM causes "unmet
direct dependencies" in Kconfig phase.

Detected by "make ARCH=score allyesconfig".

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-03-16 13:40:45 +05:30
Arnd Bergmann e593beaf60 phy: ralink: fix 64-bit build warning
Casting between an 'int' and a pointer causes a warning on
64-bit architectures in compile-testing this driver:

drivers/phy/ralink/phy-ralink-usb.c: In function 'ralink_usb_phy_probe':
drivers/phy/ralink/phy-ralink-usb.c:195:13: error: cast from pointer to
integer of different size [-Werror=pointer-to-int-cast]

This changes the code to cast to uintptr_t instead. This is
guaranteed to do what we want on all architectures and avoids
the warning.

Fixes: 2411a736ff ("phy: ralink-usb: add driver for Mediatek/Ralink")
Acked-by: John Crispin <john@phrozen.org>
Tested-by Harvey Hunt <harvey.hunt@imgtec.com>
Reviewed-by Harvey Hunt <harvey.hunt@imgtec.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-08-24 17:26:50 -07:00
John Crispin 2411a736ff phy: ralink-usb: add driver for Mediatek/Ralink
Add a driver to setup the USB phy on Mediatek/Ralink SoCs.
The driver sets up power and host mode, but also needs to
configure PHY registers for the MT7628 and MT7688.

Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Harvey Hunt <harvey.hunt@imgtec.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-08-20 14:02:23 +05:30