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Benoit Cousson f7bb0d9ab2 I2C: i2c-omap: Change device name: i2c_omap -> omap_i2c
The convention for omap device naming is omap_XXX.

Rename the device and driver name in order to stick
to this naming convention.

Change device name in clock nodes as well.

Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Ben Dooks <ben-i2c@fluff.org>
Acked-by: Paul Walmsley <paul@pwsan.com>
Acked-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-12-20 17:53:04 -08:00
Paul Walmsley 4814ced511 OMAP: control: move plat-omap/control.h to mach-omap2/control.h
Only OMAP2+ platforms have the System Control Module (SCM) IP block.
In the past, we've kept the SCM header file in plat-omap.  This has
led to abuse - device drivers including it; includes being added that
create implicit dependencies on OMAP2+ builds; etc.

In response, move the SCM headers into mach-omap2/.

As part of this, remove the direct SCM access from the OMAP UDC
driver.  It was clearly broken.  The UDC code needs an indepth review for
use on OMAP2+ chips.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Cory Maccarrone <darkstar6262@gmail.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
2010-10-08 11:40:20 -06:00
Benoit Cousson 0edc9e8582 OMAP4: clocks: Fix ES2 clock issues
Fix a few OMAP4430 clock tree problems after the recent manual merge of the
various ES2 clock patches:

- usim optional clock and its parent had the same name, rename the parent
usim_fclk -> usim_ck

- OPTFCLKEN_CLK32K is not handled anymore by the USBPHYOCP2SCP module in ES2
Create a new clock that belongs to CM_ALWON_USBPHY_CLKCTRL register

This patch depends on some of the PRCM macro updates from Rajendra.

Signed-off-by: Benoit Cousson <b-cousson@ti.com>
[paul@pwsan.com: tweaked patch description]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
2010-09-27 14:02:56 -06:00
Benoit Cousson 1c03f42f01 OMAP4: clock: Add optional clock nodes
OMAP4 IP optional clocks require explicit enable in module CTRLCLK
register. In order to allow that we have to create artificial clock
nodes that represent this clock inputs in the IP.

Notes:
- Temporary use OMAP3 names for GPIO optional clocks until the GPIO hwmod
convertion is done. It will enforce the usage of OMAP4 names as the reference.
- Temporary use OMAP3 names for TIMER main clock (gptX_fck) until TIMER hwmod
convertion is done. During that convertion, the new name will have to be used.

Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Rajendra Nayak <rnayak@ti.com>
2010-09-27 14:02:55 -06:00
Benoit Cousson 0e43327191 OMAP4: clock: Fix clock names and align with hwmod names
The OMAP4 hwmod data introduced the new naming convention for TI
IPs (See patch OMAP4: hwmod: Add partial hwmod support for OMAP4430 ES1.0)

The leaf clock names are using the same IP name and thus must be
modified to match the clock populated in the hwmod data.

- Fix some leaf clocks nodes that were using a _iclk instead of the _fclk
prefix.
- Fix some wrong interface clock name for master IPs connected to
interconnect.

Please not that due to the fact that nodes are sorted by name, the name
change will introduce a quite ugly diff a little bit hard to follow.

Timers clock con_id is still using the old gptX_fck name until the
gptimer driver is updated to omap_device framework.
Timers entries in hwmods DB are still disabled until the migration
if timer to platform_driver + omap_hwmod.

Signed-off-by: Benoit Cousson <b-cousson@ti.com>
[paul@pwsan.com: manually resolved conflicts with Rajendra's clock patch]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
2010-09-27 14:02:54 -06:00
Rajendra Nayak 76cf52951a OMAP4: clocks: Update clock tree for ES2
This patch updates the clock tree with all the
changes in OMAP4430 ES2.

clock nodes added
-1- tie_low_clock_ck
-2- abe_dpll_bypass_clk_mux_ck

clock nodes deleted
-1- dpll_sys_ref_clk
-2- per_sgx_fclk
-3- usbphyocp2scp_ick

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Benoît Cousson <b-cousson@ti.com>
[paul@pwsan.com: added comment re ES1 clocks to top of file]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
2010-09-27 14:02:54 -06:00
Santosh Shilimkar 090830b4c7 OMAP4: clock: Fix multi-omap boot with reset un-used clocks
This patch uses "ENABLE_ON_INIT" flag on the emif clock nodes
to avoid the emif clk getting cut as part of reset un-used clock
routine which prevents boot.

Since "omap4xxx_clk_init()" calls "clk_enable_init_clocks()"
which increases the usecount on all ENABLE_ON_INIT clocks, it
prevents "omap2_clk_disable_unused()" from disabling the clock.

The real fix is to have driver for EMIF and do clock get/enable
as part of it. The EMIF driver is planned to be done HWMOD way
so till that available to keep omap3_defconfig booting on OMAP4430,
this patch is necessary.
(Will updated the auto-gen script for 44xx accordingly)

The fix was suggested by Paul Walmsley

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-06-16 19:01:33 +03:00
kishore kadiyala 2c9d103e1e omap4: Adds Dummy Interface clock's for MMC controllers
This patch adds dummy Interface clocks for MMC controllers

Signed-off-by: Kishore Kadiyala <kishore.kadiyala@ti.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-05-20 11:21:21 -07:00
Abraham Arce c8334810db OMAP4: Clocks: Change SPI Instance Names
Change the name for the spi instances on omap44xx_clks to match
the names omap2 spi driver gives:

omap-mcspi.1 -> omap2_mcspi.1
omap-mcspi.2 -> omap2_mcspi.2
omap-mcspi.3 -> omap2_mcspi.3
omap-mcspi.4 -> omap2_mcspi.4

Signed-off-by: Abraham Arce <x0066660@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-04-23 15:35:11 -07:00
Santosh Shilimkar 7c43d54728 OMAP4: clock: Add dummy clock nodes for interface clocks
On OMAP4 platform the iclk control is completly under hardware control
and no software control is available.

This difference w.r.t previous OMAP's needs all the common driver
accross OMAP's , cpu_is_xxxx() checks. To avoid poulluting the
drivers dummy clock nodes are created (The autogeneration
script has been updated accordingly).

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
[paul@pwsan.com: made OMAP1 dummy_ck common and edited patch to reuse that]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24 17:45:17 -07:00
Rajendra Nayak 5477605026 OMAP4: clock: Rename leaf clock nodes to end with a _ick or _fck
All leaf clock nodes are renamed for OMAP4 to have a clk name which
end with a _ick or a _fck. This is done so that the naming convention
is same as that followed on older OMAPs.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24 17:45:16 -07:00
Paul Walmsley 53c92d8f20 OMAP4 clock: drop the ALWAYS_ENABLED clock flag
Get rid of the ALWAYS_ENABLED clock flag - it doesn't actually do anything.
(The OMAP4 clock autogeneration scripts have been updated accordingly.)

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Benoît Cousson <b-cousson@ti.com>
2010-02-24 12:29:43 -07:00
Paul Walmsley 657ebfadc1 OMAP3/4 clock: split into per-chip family files
clock34xx_data.c now contains data for the OMAP34xx family, the
OMAP36xx family, and the OMAP3517 family, so rename it to
clock3xxx_data.c.  Rename clock34xx.c to clock3xxx.c, and move the
chip family-specific clock functions to clock34xx.c, clock36xx.c, or
clock3517.c, as appropriate.  So now "clock3xxx.*" refers to the OMAP3
superset.

The main goal here is to prepare to compile chip family-specific clock
functions only for kernel builds that target that chip family.  To get to
that point, we also need to add CONFIG_SOC_* options for those other
chip families; that will be done in future patches, planned for 2.6.35.

OMAP4 is also affected by this.  It duplicated the OMAP3 non-CORE DPLL
clkops structure.  The OMAP4 variant of this clkops structure has been
removed, and since there was nothing else currently in clock44xx.c, it
too has been removed -- it can always be added back later when there
is some content for it.  (The OMAP4 clock autogeneration scripts have been
updated accordingly.)

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Ranjith Lohithakshan <ranjithl@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
2010-02-24 12:16:15 -07:00
Paul Walmsley c78a05e8e4 OMAP4 clock: drop the CLOCK_IN_OMAP4430 clock flag
The CLOCK_IN_OMAP4430 clock flag is not currently needed in the OMAP4
ES1 clock tree, and platform discrimination via clock flags is
deprecated in favor of the clkdev mechanism, so, drop it.  (The OMAP4
clock tree autogeneration script has been updated accordingly.)

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
2010-02-24 12:15:04 -07:00
Paul Walmsley 93340a2294 OMAP2/3/4 clock: fix DPLL multiplier value errors; also copyrights, includes, documentation
The maximum DPLL multiplier (M) values for OMAP2xxx and OMAP3xxx are
one increment higher than they should be.  See for example the
OMAP242x TRM Rev X Section 5.10.6 "Clock Generator Registers" and the
OMAP36xx TRM Rev C Table 3-202 "CM_CLKSEL1_PLL".  Programming a 0 into
the DPLL's M register bitfield is valid for OMAP2/3 and indicates that
the DPLL should enter MN-bypass mode.  Also, increase the minimum
multiplier (M) value for the DPLL rate rounding code from 1 to 2, to
ensure that it does not inadvertently put the DPLL into bypass.

Note that the register documentation in the OMAP2xxx and OMAP3xxx TRMs
does not make clear that the actual DPLL divider value (the "N") is
the content of the appropriate register bitfield for the N value,
_plus one_.  (In other words, an N register bitfield of 0 indicates a
DPLL divider value of 1.)  This is only clearly documented in the
OMAP4430 TRM, in, for example, OMAP4430 TRM Rev A Table 3-1167
"CM_CLKSEL_DPLL_USB".

While here, update copyrights, add kerneldoc for struct dpll_data,
drop the unused struct dpll_data.max_tolerance field, remove some
unnecessary #includes in DPLL-related code, and replace the #include
of <linux/module.h> with <linux/list.h>, which is what was really
needed.  The OMAP4 clock autogenerator script has been updated
accordingly.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
2010-02-24 12:15:03 -07:00
Richard Woodruff 358965d7ba OMAP3 clock: introduce DPLL4 Jtype
DPLL4 for 3630 introduces a changed block called j type dpll, requiring
special divisor bits and additional reg fields. To allow for silicons to
use this, this is introduced as a flag and is enabled for 3630 silicon.
OMAP4 also has j type dpll for usb.

Tested with 3630 ZOOM3 and OMAP3430 ZOOM2

Signed-off-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vishwanath BS <Vishwanath.bs@ti.com>
[paul@pwsan.com: added some comments; updated copyrights and credits; fixed
 some style issues]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24 12:15:02 -07:00
Tony Lindgren 4751227df9 omap3/4: Fix compile for multi-omap for clkops_noncore_dpll_ops
Rename clkops_noncore_dpll_ops for omap3 and omap4.

Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-02-15 09:27:25 -08:00
Paul Walmsley e80a9729b1 OMAP2/3/4 clock: rename and clean the omap2_clk_init() functions
Rename the omap2_clk_init() in the OMAP2, 3, and 4 clock code to be
omap2xxx_clk_init(), omap3xxx_clk_init(), etc.  Remove all traces of
the (commented) old virt_prcm_set code from omap3xxx_clk_init() and
omap4xxx_clk_init(), since this will be handled with the OPP code that
is cooking in the PM branch.

After this patch, there should be very little else in the clock code
that blocks a multi-OMAP 2+3 kernel.  (OMAP2420+OMAP2430 still has some
outstanding issues that need to be resolved; this is pending on some
additions to the hwmod data.)

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-01-29 10:14:22 -07:00
Abhijit Pagare bf98540106 ARM: OMAP4 clock framework: Remove the checks preventing OMAP4 clockdomain validation
The clockdomain related code being in place, it is not necessary to have
some part of the clock code commented out. This would help the validation of
the clockdomain functions using the clock level interfaces.

Signed-off-by: Abhijit Pagare <abhijitpagare@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-01-26 20:12:58 -07:00
Rajendra Nayak ecbb065947 OMAP4: clocks: Fix the clksel_rate struct DPLL divs
For all DPLL's the valid dividers are same as the values
to be programmed in the register. 0 is an invalid value.
The changes are generated by updating the script which autogenerates
the file modifed in the patch.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-01-20 13:35:28 -07:00
Rajendra Nayak 911bd7395c ARM: OMAP4: PM: Add init api for DPLL nodes
An api at init for all dpll nodes seem to be
needed to reparent the dpll clk node to its
bypass clk in case the dpll is in bypass.
If not done this causes sequencing issues at init
during propogate_rate.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoit Cousson <b-cousson@ti.com>
2009-12-11 17:00:47 -07:00
Rajendra Nayak 972c542746 ARM: OMAP4: PM: OMAP4 clock tree and clkdev registration
This patch defines all the clock nodes in OMAP4430
platform. All the clock node structs and the clkdev table is
autogenerated using a python script (gen_clock_tree.py)
developed by Paul Walmsley, Benoit Cousson and Rajendra Nayak.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoit Cousson <b-cousson@ti.com>
2009-12-11 17:00:45 -07:00