/************************************************************************ * s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC * Copyright(c) 2002-2007 Neterion Inc. * This software may be used and distributed according to the terms of * the GNU General Public License (GPL), incorporated herein by reference. * Drivers based on or derived from this code fall under the GPL and must * retain the authorship, copyright and license notice. This file is not * a complete program and may only be used when the entire operating * system is licensed under the GPL. * See the file COPYING in this distribution for more information. ************************************************************************/ #ifndef _S2IO_H #define _S2IO_H #define TBD 0 #define BIT(loc) (0x8000000000000000ULL >> (loc)) #define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz)) #define INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff) #ifndef BOOL #define BOOL int #endif #ifndef TRUE #define TRUE 1 #define FALSE 0 #endif #undef SUCCESS #define SUCCESS 0 #define FAILURE -1 #define S2IO_MINUS_ONE 0xFFFFFFFFFFFFFFFFULL #define S2IO_MAX_PCI_CONFIG_SPACE_REINIT 100 #define S2IO_BIT_RESET 1 #define S2IO_BIT_SET 2 #define CHECKBIT(value, nbit) (value & (1 << nbit)) /* Maximum time to flicker LED when asked to identify NIC using ethtool */ #define MAX_FLICKER_TIME 60000 /* 60 Secs */ /* Maximum outstanding splits to be configured into xena. */ enum { XENA_ONE_SPLIT_TRANSACTION = 0, XENA_TWO_SPLIT_TRANSACTION = 1, XENA_THREE_SPLIT_TRANSACTION = 2, XENA_FOUR_SPLIT_TRANSACTION = 3, XENA_EIGHT_SPLIT_TRANSACTION = 4, XENA_TWELVE_SPLIT_TRANSACTION = 5, XENA_SIXTEEN_SPLIT_TRANSACTION = 6, XENA_THIRTYTWO_SPLIT_TRANSACTION = 7 }; #define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4) /* OS concerned variables and constants */ #define WATCH_DOG_TIMEOUT 15*HZ #define EFILL 0x1234 #define ALIGN_SIZE 127 #define PCIX_COMMAND_REGISTER 0x62 /* * Debug related variables. */ /* different debug levels. */ #define ERR_DBG 0 #define INIT_DBG 1 #define INFO_DBG 2 #define TX_DBG 3 #define INTR_DBG 4 /* Global variable that defines the present debug level of the driver. */ static int debug_level = ERR_DBG; /* DEBUG message print. */ #define DBG_PRINT(dbg_level, args...) if(!(debug_level> 16) & 0xFFFF) #define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF) u64 Control_2; #define THE_RXD_MARK 0x3 #define SET_RXD_MARKER vBIT(THE_RXD_MARK, 0, 2) #define GET_RXD_MARKER(ctrl) ((ctrl & SET_RXD_MARKER) >> 62) #define MASK_VLAN_TAG vBIT(0xFFFF,48,16) #define SET_VLAN_TAG(val) vBIT(val,48,16) #define SET_NUM_TAG(val) vBIT(val,16,32) }; /* Rx descriptor structure for 1 buffer mode */ struct RxD1 { struct RxD_t h; #define MASK_BUFFER0_SIZE_1 vBIT(0x3FFF,2,14) #define SET_BUFFER0_SIZE_1(val) vBIT(val,2,14) #define RXD_GET_BUFFER0_SIZE_1(_Control_2) \ (u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48) u64 Buffer0_ptr; }; /* Rx descriptor structure for 3 or 2 buffer mode */ struct RxD3 { struct RxD_t h; #define MASK_BUFFER0_SIZE_3 vBIT(0xFF,2,14) #define MASK_BUFFER1_SIZE_3 vBIT(0xFFFF,16,16) #define MASK_BUFFER2_SIZE_3 vBIT(0xFFFF,32,16) #define SET_BUFFER0_SIZE_3(val) vBIT(val,8,8) #define SET_BUFFER1_SIZE_3(val) vBIT(val,16,16) #define SET_BUFFER2_SIZE_3(val) vBIT(val,32,16) #define RXD_GET_BUFFER0_SIZE_3(Control_2) \ (u8)((Control_2 & MASK_BUFFER0_SIZE_3) >> 48) #define RXD_GET_BUFFER1_SIZE_3(Control_2) \ (u16)((Control_2 & MASK_BUFFER1_SIZE_3) >> 32) #define RXD_GET_BUFFER2_SIZE_3(Control_2) \ (u16)((Control_2 & MASK_BUFFER2_SIZE_3) >> 16) #define BUF0_LEN 40 #define BUF1_LEN 1 u64 Buffer0_ptr; u64 Buffer1_ptr; u64 Buffer2_ptr; }; /* Structure that represents the Rx descriptor block which contains * 128 Rx descriptors. */ struct RxD_block { #define MAX_RXDS_PER_BLOCK_1 127 struct RxD1 rxd[MAX_RXDS_PER_BLOCK_1]; u64 reserved_0; #define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last * Rxd in this blk */ u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */ u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch * the upper 32 bits should * be 0 */ }; #define SIZE_OF_BLOCK 4096 #define RXD_MODE_1 0 /* One Buffer mode */ #define RXD_MODE_3B 1 /* Two Buffer mode */ /* Structure to hold virtual addresses of Buf0 and Buf1 in * 2buf mode. */ struct buffAdd { void *ba_0_org; void *ba_1_org; void *ba_0; void *ba_1; }; /* Structure which stores all the MAC control parameters */ /* This structure stores the offset of the RxD in the ring * from which the Rx Interrupt processor can start picking * up the RxDs for processing. */ struct rx_curr_get_info { u32 block_index; u32 offset; u32 ring_len; }; struct rx_curr_put_info { u32 block_index; u32 offset; u32 ring_len; }; /* This structure stores the offset of the TxDl in the FIFO * from which the Tx Interrupt processor can start picking * up the TxDLs for send complete interrupt processing. */ struct tx_curr_get_info { u32 offset; u32 fifo_len; }; struct tx_curr_put_info { u32 offset; u32 fifo_len; }; struct rxd_info { void *virt_addr; dma_addr_t dma_addr; }; /* Structure that holds the Phy and virt addresses of the Blocks */ struct rx_block_info { void *block_virt_addr; dma_addr_t block_dma_addr; struct rxd_info *rxds; }; /* Ring specific structure */ struct ring_info { /* The ring number */ int ring_no; /* * Place holders for the virtual and physical addresses of * all the Rx Blocks */ struct rx_block_info rx_blocks[MAX_RX_BLOCKS_PER_RING]; int block_count; int pkt_cnt; /* * Put pointer info which indictes which RxD has to be replenished * with a new buffer. */ struct rx_curr_put_info rx_curr_put_info; /* * Get pointer info which indictes which is the last RxD that was * processed by the driver. */ struct rx_curr_get_info rx_curr_get_info; /* Index to the absolute position of the put pointer of Rx ring */ int put_pos; /* Buffer Address store. */ struct buffAdd **ba; struct s2io_nic *nic; }; /* Fifo specific structure */ struct fifo_info { /* FIFO number */ int fifo_no; /* Maximum TxDs per TxDL */ int max_txds; /* Place holder of all the TX List's Phy and Virt addresses. */ struct list_info_hold *list_info; /* * Current offset within the tx FIFO where driver would write * new Tx frame */ struct tx_curr_put_info tx_curr_put_info; /* * Current offset within tx FIFO from where the driver would start freeing * the buffers */ struct tx_curr_get_info tx_curr_get_info; struct s2io_nic *nic; }; /* Information related to the Tx and Rx FIFOs and Rings of Xena * is maintained in this structure. */ struct mac_info { /* tx side stuff */ /* logical pointer of start of each Tx FIFO */ struct TxFIFO_element __iomem *tx_FIFO_start[MAX_TX_FIFOS]; /* Fifo specific structure */ struct fifo_info fifos[MAX_TX_FIFOS]; /* Save virtual address of TxD page with zero DMA addr(if any) */ void *zerodma_virt_addr; /* rx side stuff */ /* Ring specific structure */ struct ring_info rings[MAX_RX_RINGS]; u16 rmac_pause_time; u16 mc_pause_threshold_q0q3; u16 mc_pause_threshold_q4q7; void *stats_mem; /* orignal pointer to allocated mem */ dma_addr_t stats_mem_phy; /* Physical address of the stat block */ u32 stats_mem_sz; struct stat_block *stats_info; /* Logical address of the stat block */ }; /* structure representing the user defined MAC addresses */ struct usr_addr { char addr[ETH_ALEN]; int usage_cnt; }; /* Default Tunable parameters of the NIC. */ #define DEFAULT_FIFO_0_LEN 4096 #define DEFAULT_FIFO_1_7_LEN 512 #define SMALL_BLK_CNT 30 #define LARGE_BLK_CNT 100 /* * Structure to keep track of the MSI-X vectors and the corresponding * argument registered against each vector */ #define MAX_REQUESTED_MSI_X 17 struct s2io_msix_entry { u16 vector; u16 entry; void *arg; u8 type; #define MSIX_FIFO_TYPE 1 #define MSIX_RING_TYPE 2 u8 in_use; #define MSIX_REGISTERED_SUCCESS 0xAA }; struct msix_info_st { u64 addr; u64 data; }; /* Data structure to represent a LRO session */ struct lro { struct sk_buff *parent; struct sk_buff *last_frag; u8 *l2h; struct iphdr *iph; struct tcphdr *tcph; u32 tcp_next_seq; __be32 tcp_ack; int total_len; int frags_len; int sg_num; int in_use; __be16 window; u32 cur_tsval; u32 cur_tsecr; u8 saw_ts; }; /* Structure representing one instance of the NIC */ struct s2io_nic { int rxd_mode; /* * Count of packets to be processed in a given iteration, it will be indicated * by the quota field of the device structure when NAPI is enabled. */ int pkts_to_process; struct net_device *dev; struct napi_struct napi; struct mac_info mac_control; struct config_param config; struct pci_dev *pdev; void __iomem *bar0; void __iomem *bar1; #define MAX_MAC_SUPPORTED 16 #define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED struct mac_addr def_mac_addr[MAX_MAC_SUPPORTED]; struct net_device_stats stats; int high_dma_flag; int device_enabled_once; char name[60]; struct tasklet_struct task; volatile unsigned long tasklet_status; /* Timer that handles I/O errors/exceptions */ struct timer_list alarm_timer; /* Space to back up the PCI config space */ u32 config_space[256 / sizeof(u32)]; atomic_t rx_bufs_left[MAX_RX_RINGS]; spinlock_t tx_lock; spinlock_t put_lock; #define PROMISC 1 #define ALL_MULTI 2 #define MAX_ADDRS_SUPPORTED 64 u16 usr_addr_count; u16 mc_addr_count; struct usr_addr usr_addrs[MAX_ADDRS_SUPPORTED]; u16 m_cast_flg; u16 all_multi_pos; u16 promisc_flg; /* Id timer, used to blink NIC to physically identify NIC. */ struct timer_list id_timer; /* Restart timer, used to restart NIC if the device is stuck and * a schedule task that will set the correct Link state once the * NIC's PHY has stabilized after a state change. */ struct work_struct rst_timer_task; struct work_struct set_link_task; /* Flag that can be used to turn on or turn off the Rx checksum * offload feature. */ int rx_csum; /* after blink, the adapter must be restored with original * values. */ u64 adapt_ctrl_org; /* Last known link state. */ u16 last_link_state; #define LINK_DOWN 1 #define LINK_UP 2 int task_flag; unsigned long long start_time; #define CARD_DOWN 1 #define CARD_UP 2 atomic_t card_state; volatile unsigned long link_state; struct vlan_group *vlgrp; #define MSIX_FLG 0xA5 struct msix_entry *entries; int msi_detected; wait_queue_head_t msi_wait; struct s2io_msix_entry *s2io_entries; char desc[MAX_REQUESTED_MSI_X][25]; int avail_msix_vectors; /* No. of MSI-X vectors granted by system */ struct msix_info_st msix_info[0x3f]; #define XFRAME_I_DEVICE 1 #define XFRAME_II_DEVICE 2 u8 device_type; #define MAX_LRO_SESSIONS 32 struct lro lro0_n[MAX_LRO_SESSIONS]; unsigned long clubbed_frms_cnt; unsigned long sending_both; u8 lro; u16 lro_max_aggr_per_sess; #define INTA 0 #define MSI_X 2 u8 intr_type; spinlock_t rx_lock; atomic_t isr_cnt; u64 general_int_mask; u64 *ufo_in_band_v; #define VPD_STRING_LEN 80 u8 product_name[VPD_STRING_LEN]; u8 serial_num[VPD_STRING_LEN]; }; #define RESET_ERROR 1; #define CMD_ERROR 2; /* OS related system calls */ #ifndef readq static inline u64 readq(void __iomem *addr) { u64 ret = 0; ret = readl(addr + 4); ret <<= 32; ret |= readl(addr); return ret; } #endif #ifndef writeq static inline void writeq(u64 val, void __iomem *addr) { writel((u32) (val), addr); writel((u32) (val >> 32), (addr + 4)); } #endif /* * Some registers have to be written in a particular order to * expect correct hardware operation. The macro SPECIAL_REG_WRITE * is used to perform such ordered writes. Defines UF (Upper First) * and LF (Lower First) will be used to specify the required write order. */ #define UF 1 #define LF 2 static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order) { u32 ret; if (order == LF) { writel((u32) (val), addr); ret = readl(addr); writel((u32) (val >> 32), (addr + 4)); ret = readl(addr + 4); } else { writel((u32) (val >> 32), (addr + 4)); ret = readl(addr + 4); writel((u32) (val), addr); ret = readl(addr); } } /* Interrupt related values of Xena */ #define ENABLE_INTRS 1 #define DISABLE_INTRS 2 /* Highest level interrupt blocks */ #define TX_PIC_INTR (0x0001<<0) #define TX_DMA_INTR (0x0001<<1) #define TX_MAC_INTR (0x0001<<2) #define TX_XGXS_INTR (0x0001<<3) #define TX_TRAFFIC_INTR (0x0001<<4) #define RX_PIC_INTR (0x0001<<5) #define RX_DMA_INTR (0x0001<<6) #define RX_MAC_INTR (0x0001<<7) #define RX_XGXS_INTR (0x0001<<8) #define RX_TRAFFIC_INTR (0x0001<<9) #define MC_INTR (0x0001<<10) #define ENA_ALL_INTRS ( TX_PIC_INTR | \ TX_DMA_INTR | \ TX_MAC_INTR | \ TX_XGXS_INTR | \ TX_TRAFFIC_INTR | \ RX_PIC_INTR | \ RX_DMA_INTR | \ RX_MAC_INTR | \ RX_XGXS_INTR | \ RX_TRAFFIC_INTR | \ MC_INTR ) /* Interrupt masks for the general interrupt mask register */ #define DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL #define TXPIC_INT_M BIT(0) #define TXDMA_INT_M BIT(1) #define TXMAC_INT_M BIT(2) #define TXXGXS_INT_M BIT(3) #define TXTRAFFIC_INT_M BIT(8) #define PIC_RX_INT_M BIT(32) #define RXDMA_INT_M BIT(33) #define RXMAC_INT_M BIT(34) #define MC_INT_M BIT(35) #define RXXGXS_INT_M BIT(36) #define RXTRAFFIC_INT_M BIT(40) /* PIC level Interrupts TODO*/ /* DMA level Inressupts */ #define TXDMA_PFC_INT_M BIT(0) #define TXDMA_PCC_INT_M BIT(2) /* PFC block interrupts */ #define PFC_MISC_ERR_1 BIT(0) /* Interrupt to indicate FIFO full */ /* PCC block interrupts. */ #define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate PCC_FB_ECC Error. */ #define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG) /* * Prototype declaration. */ static int __devinit s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre); static void __devexit s2io_rem_nic(struct pci_dev *pdev); static int init_shared_mem(struct s2io_nic *sp); static void free_shared_mem(struct s2io_nic *sp); static int init_nic(struct s2io_nic *nic); static void rx_intr_handler(struct ring_info *ring_data); static void tx_intr_handler(struct fifo_info *fifo_data); static void alarm_intr_handler(struct s2io_nic *sp); static int s2io_starter(void); static void s2io_closer(void); static void s2io_tx_watchdog(struct net_device *dev); static void s2io_tasklet(unsigned long dev_addr); static void s2io_set_multicast(struct net_device *dev); static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp); static void s2io_link(struct s2io_nic * sp, int link); static void s2io_reset(struct s2io_nic * sp); static int s2io_poll(struct napi_struct *napi, int budget); static void s2io_init_pci(struct s2io_nic * sp); static int s2io_set_mac_addr(struct net_device *dev, u8 * addr); static void s2io_alarm_handle(unsigned long data); static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id); static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id); static irqreturn_t s2io_isr(int irq, void *dev_id); static int verify_xena_quiescence(struct s2io_nic *sp); static const struct ethtool_ops netdev_ethtool_ops; static void s2io_set_link(struct work_struct *work); static int s2io_set_swapper(struct s2io_nic * sp); static void s2io_card_down(struct s2io_nic *nic); static int s2io_card_up(struct s2io_nic *nic); static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit, int bit_state); static int s2io_add_isr(struct s2io_nic * sp); static void s2io_rem_isr(struct s2io_nic * sp); static void restore_xmsi_data(struct s2io_nic *nic); static int s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro, struct RxD_t *rxdp, struct s2io_nic *sp); static void clear_lro_session(struct lro *lro); static void queue_rx_frame(struct sk_buff *skb); static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro); static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro, struct sk_buff *skb, u32 tcp_len); static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring); static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state); static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev); static void s2io_io_resume(struct pci_dev *pdev); #define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size #define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size #define s2io_offload_type(skb) skb_shinfo(skb)->gso_type #define S2IO_PARM_INT(X, def_val) \ static unsigned int X = def_val;\ module_param(X , uint, 0); #endif /* _S2IO_H */