Serge Semin e338131e98 clk: baikal-t1: Add SATA internal ref clock buffer ... [ Upstream commit 081a9b7c74 ] It turns out the internal SATA reference clock signal will stay unavailable for the SATA interface consumer until the buffer on it's way is ungated. So aside with having the actual clock divider enabled we need to ungate a buffer placed on the signal way to the SATA controller (most likely some rudiment from the initial SoC release). Seeing the switch flag is placed in the same register as the SATA-ref clock divider at a non-standard ffset, let's implement it as a separate clock controller with the set-rate propagation to the parental clock divider wrapper. As such we'll be able to disable/enable and still change the original clock source rate. Fixes: 353afa3a8d ("clk: Add Baikal-T1 CCU Dividers driver") Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Link: https://lore.kernel.org/r/20220929225402.9696-5-Sergey.Semin@baikalelectronics.ru Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>		2022-10-26 12:35:20 +02:00
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Kconfig	clk: Add Baikal-T1 CCU Dividers driver	2020-05-30 11:10:23 -07:00
Makefile	clk: Add Baikal-T1 CCU Dividers driver	2020-05-30 11:10:23 -07:00
ccu-div.c	clk: baikal-t1: Add SATA internal ref clock buffer	2022-10-26 12:35:20 +02:00
ccu-div.h	clk: baikal-t1: Add SATA internal ref clock buffer	2022-10-26 12:35:20 +02:00
ccu-pll.c	…
ccu-pll.h	…
clk-ccu-div.c	clk: baikal-t1: Add SATA internal ref clock buffer	2022-10-26 12:35:20 +02:00
clk-ccu-pll.c	clk: baikal-t1: Mark Ethernet PLL as critical	2020-10-13 19:48:34 -07:00