WSL2-Linux-Kernel/drivers/clk/socfpga
Gustavo A. R. Silva 18640a1818 clk: socfpga: Fix undefined behavior bug in struct stratix10_clock_data
commit d761bb01c85b22d5b44abe283eb89019693f6595 upstream.

`struct clk_hw_onecell_data` is a flexible structure, which means that
it contains flexible-array member at the bottom, in this case array
`hws`:

include/linux/clk-provider.h:
1380 struct clk_hw_onecell_data {
1381         unsigned int num;
1382         struct clk_hw *hws[] __counted_by(num);
1383 };

This could potentially lead to an overwrite of the objects following
`clk_data` in `struct stratix10_clock_data`, in this case
`void __iomem *base;` at run-time:

drivers/clk/socfpga/stratix10-clk.h:
  9 struct stratix10_clock_data {
 10         struct clk_hw_onecell_data      clk_data;
 11         void __iomem            *base;
 12 };

There are currently three different places where memory is allocated for
`struct stratix10_clock_data`, including the flex-array `hws` in
`struct clk_hw_onecell_data`:

drivers/clk/socfpga/clk-agilex.c:
469         clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
470                                 num_clks), GFP_KERNEL);

drivers/clk/socfpga/clk-agilex.c:
509         clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
510                                 num_clks), GFP_KERNEL);

drivers/clk/socfpga/clk-s10.c:
400         clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
401                                                  num_clks), GFP_KERNEL);

I'll use just one of them to describe the issue. See below.

Notice that a total of 440 bytes are allocated for flexible-array member
`hws` at line 469:

include/dt-bindings/clock/agilex-clock.h:
 70 #define AGILEX_NUM_CLKS	55

drivers/clk/socfpga/clk-agilex.c:
459         struct stratix10_clock_data *clk_data;
460         void __iomem *base;
...
466
467         num_clks = AGILEX_NUM_CLKS;
468
469         clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
470                                 num_clks), GFP_KERNEL);

`struct_size(clk_data, clk_data.hws, num_clks)`	above translates to
sizeof(struct stratix10_clock_data) + sizeof(struct clk_hw *) * 55 ==
16 + 8 * 55 == 16 + 440
		    ^^^
		     |
	allocated bytes for flex-array `hws`

474         for (i = 0; i < num_clks; i++)
475                 clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);
476
477         clk_data->base = base;

and then some data is written into both `hws` and `base` objects.

Fix this by placing the declaration of object `clk_data` at the end of
`struct stratix10_clock_data`. Also, add a comment to make it clear
that this object must always be last in the structure.

-Wflex-array-member-not-at-end is coming in GCC-14, and we are getting
ready to enable it globally.

Fixes: ba7e258425 ("clk: socfpga: Convert to s10/agilex/n5x to use clk_hw")
Cc: stable@vger.kernel.org
Reviewed-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Link: https://lore.kernel.org/r/1da736106d8e0806aeafa6e471a13ced490eae22.1698117815.git.gustavoars@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-11-28 16:56:28 +00:00
..
Kconfig clk: socfpga: use ARCH_INTEL_SOCFPGA also for 32-bit ARM SoCs (and compile test) 2021-03-23 11:03:36 -05:00
Makefile clk: socfpga: use ARCH_INTEL_SOCFPGA also for 32-bit ARM SoCs (and compile test) 2021-03-23 11:03:36 -05:00
clk-agilex.c clk: socfpga: agilex: fix duplicate s2f_user0_clk 2021-09-24 16:03:08 -07:00
clk-gate-a10.c clk: socfpga: arria10: Fix memory leak of socfpga_clk on error return 2021-04-07 16:29:31 -07:00
clk-gate-s10.c clk: agilex/stratix10: add support for the 2nd bypass 2021-06-27 16:39:59 -07:00
clk-gate.c clk: socfpga: Fix memory leak in socfpga_gate_init() 2022-12-31 13:14:18 +01:00
clk-periph-a10.c clk: socfpga: arria10: convert to use clk_hw 2021-03-30 19:26:26 -07:00
clk-periph-s10.c clk: agilex/stratix10/n5x: fix how the bypass_reg is handled 2021-06-27 16:39:59 -07:00
clk-periph.c clk: socfpga: use clk_hw_register for a5/c5 2021-03-30 19:26:26 -07:00
clk-pll-a10.c clk: socfpga: arria10: convert to use clk_hw 2021-03-30 19:26:26 -07:00
clk-pll-s10.c clk: socfpga: remove redundant initialization of variable div 2021-04-07 16:30:23 -07:00
clk-pll.c clk: socfpga: clk-pll: Remove unused variable 'rc' 2021-06-27 17:33:21 -07:00
clk-s10.c clk: agilex/stratix10: fix bypass representation 2021-06-27 16:39:59 -07:00
clk.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13 2019-05-21 11:28:45 +02:00
clk.h treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288 2019-06-05 17:36:37 +02:00
stratix10-clk.h clk: socfpga: Fix undefined behavior bug in struct stratix10_clock_data 2023-11-28 16:56:28 +00:00