WSL2-Linux-Kernel/drivers/clk/zynqmp
Jay Buddhabhatti 9117fc44fd drivers: clk: zynqmp: update divider round rate logic
[ Upstream commit 1fe15be1fb613534ecbac5f8c3f8744f757d237d ]

Currently zynqmp divider round rate is considering single parent and
calculating rate and parent rate accordingly. But if divider clock flag
is set to SET_RATE_PARENT then its not trying to traverse through all
parent rate and not selecting best parent rate from that. So use common
divider_round_rate() which is traversing through all clock parents and
its rate and calculating proper parent rate.

Fixes: 3fde0e16d0 ("drivers: clk: Add ZynqMP clock driver")
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Link: https://lore.kernel.org/r/20231129112916.23125-3-jay.buddhabhatti@amd.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2024-01-25 14:52:44 -08:00
..
Kconfig clk: zynqmp: Drop dependency on ARCH_ZYNQMP 2021-04-07 17:26:09 -07:00
Makefile
clk-gate-zynqmp.c clk: zynqmp: Fix kernel-doc format 2021-08-28 23:43:17 -07:00
clk-mux-zynqmp.c drivers: clk: zynqmp: calculate closest mux rate 2024-01-25 14:52:44 -08:00
clk-zynqmp.h clk: zynqmp: fix kernel doc 2021-08-28 21:19:02 -07:00
clkc.c clk: zynqmp: Fix stack-out-of-bounds in strncpy` 2022-10-26 12:35:45 +02:00
divider.c drivers: clk: zynqmp: update divider round rate logic 2024-01-25 14:52:44 -08:00
pll.c clk: zynqmp: pll: rectify rate rounding in zynqmp_pll_round_rate 2022-10-26 12:35:46 +02:00