748 строки
19 KiB
C
748 строки
19 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
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#include <linux/acpi.h>
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#include <linux/clk.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/qcom-geni-se.h>
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#include <linux/spinlock.h>
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#define SE_I2C_TX_TRANS_LEN 0x26c
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#define SE_I2C_RX_TRANS_LEN 0x270
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#define SE_I2C_SCL_COUNTERS 0x278
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#define SE_I2C_ERR (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\
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M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN)
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#define SE_I2C_ABORT BIT(1)
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/* M_CMD OP codes for I2C */
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#define I2C_WRITE 0x1
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#define I2C_READ 0x2
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#define I2C_WRITE_READ 0x3
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#define I2C_ADDR_ONLY 0x4
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#define I2C_BUS_CLEAR 0x6
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#define I2C_STOP_ON_BUS 0x7
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/* M_CMD params for I2C */
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#define PRE_CMD_DELAY BIT(0)
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#define TIMESTAMP_BEFORE BIT(1)
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#define STOP_STRETCH BIT(2)
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#define TIMESTAMP_AFTER BIT(3)
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#define POST_COMMAND_DELAY BIT(4)
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#define IGNORE_ADD_NACK BIT(6)
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#define READ_FINISHED_WITH_ACK BIT(7)
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#define BYPASS_ADDR_PHASE BIT(8)
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#define SLV_ADDR_MSK GENMASK(15, 9)
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#define SLV_ADDR_SHFT 9
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/* I2C SCL COUNTER fields */
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#define HIGH_COUNTER_MSK GENMASK(29, 20)
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#define HIGH_COUNTER_SHFT 20
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#define LOW_COUNTER_MSK GENMASK(19, 10)
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#define LOW_COUNTER_SHFT 10
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#define CYCLE_COUNTER_MSK GENMASK(9, 0)
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enum geni_i2c_err_code {
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GP_IRQ0,
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NACK,
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GP_IRQ2,
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BUS_PROTO,
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ARB_LOST,
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GP_IRQ5,
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GENI_OVERRUN,
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GENI_ILLEGAL_CMD,
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GENI_ABORT_DONE,
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GENI_TIMEOUT,
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};
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#define DM_I2C_CB_ERR ((BIT(NACK) | BIT(BUS_PROTO) | BIT(ARB_LOST)) \
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<< 5)
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#define I2C_AUTO_SUSPEND_DELAY 250
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#define KHZ(freq) (1000 * freq)
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#define PACKING_BYTES_PW 4
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#define ABORT_TIMEOUT HZ
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#define XFER_TIMEOUT HZ
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#define RST_TIMEOUT HZ
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struct geni_i2c_dev {
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struct geni_se se;
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u32 tx_wm;
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int irq;
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int err;
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struct i2c_adapter adap;
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struct completion done;
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struct i2c_msg *cur;
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int cur_wr;
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int cur_rd;
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spinlock_t lock;
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u32 clk_freq_out;
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const struct geni_i2c_clk_fld *clk_fld;
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int suspended;
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void *dma_buf;
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size_t xfer_len;
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dma_addr_t dma_addr;
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};
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struct geni_i2c_err_log {
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int err;
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const char *msg;
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};
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static const struct geni_i2c_err_log gi2c_log[] = {
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[GP_IRQ0] = {-EIO, "Unknown I2C err GP_IRQ0"},
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[NACK] = {-ENXIO, "NACK: slv unresponsive, check its power/reset-ln"},
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[GP_IRQ2] = {-EIO, "Unknown I2C err GP IRQ2"},
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[BUS_PROTO] = {-EPROTO, "Bus proto err, noisy/unexpected start/stop"},
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[ARB_LOST] = {-EAGAIN, "Bus arbitration lost, clock line undriveable"},
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[GP_IRQ5] = {-EIO, "Unknown I2C err GP IRQ5"},
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[GENI_OVERRUN] = {-EIO, "Cmd overrun, check GENI cmd-state machine"},
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[GENI_ILLEGAL_CMD] = {-EIO, "Illegal cmd, check GENI cmd-state machine"},
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[GENI_ABORT_DONE] = {-ETIMEDOUT, "Abort after timeout successful"},
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[GENI_TIMEOUT] = {-ETIMEDOUT, "I2C TXN timed out"},
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};
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struct geni_i2c_clk_fld {
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u32 clk_freq_out;
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u8 clk_div;
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u8 t_high_cnt;
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u8 t_low_cnt;
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u8 t_cycle_cnt;
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};
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/*
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* Hardware uses the underlying formula to calculate time periods of
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* SCL clock cycle. Firmware uses some additional cycles excluded from the
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* below formula and it is confirmed that the time periods are within
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* specification limits.
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*
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* time of high period of SCL: t_high = (t_high_cnt * clk_div) / source_clock
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* time of low period of SCL: t_low = (t_low_cnt * clk_div) / source_clock
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* time of full period of SCL: t_cycle = (t_cycle_cnt * clk_div) / source_clock
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* clk_freq_out = t / t_cycle
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* source_clock = 19.2 MHz
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*/
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static const struct geni_i2c_clk_fld geni_i2c_clk_map[] = {
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{KHZ(100), 7, 10, 11, 26},
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{KHZ(400), 2, 5, 12, 24},
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{KHZ(1000), 1, 3, 9, 18},
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};
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static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c)
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{
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int i;
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const struct geni_i2c_clk_fld *itr = geni_i2c_clk_map;
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for (i = 0; i < ARRAY_SIZE(geni_i2c_clk_map); i++, itr++) {
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if (itr->clk_freq_out == gi2c->clk_freq_out) {
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gi2c->clk_fld = itr;
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return 0;
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}
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}
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return -EINVAL;
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}
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static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c)
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{
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const struct geni_i2c_clk_fld *itr = gi2c->clk_fld;
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u32 val;
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writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL);
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val = (itr->clk_div << CLK_DIV_SHFT) | SER_CLK_EN;
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writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG);
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val = itr->t_high_cnt << HIGH_COUNTER_SHFT;
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val |= itr->t_low_cnt << LOW_COUNTER_SHFT;
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val |= itr->t_cycle_cnt;
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writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS);
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}
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static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c)
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{
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u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0);
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u32 m_stat = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS);
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u32 geni_s = readl_relaxed(gi2c->se.base + SE_GENI_STATUS);
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u32 geni_ios = readl_relaxed(gi2c->se.base + SE_GENI_IOS);
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u32 dma = readl_relaxed(gi2c->se.base + SE_GENI_DMA_MODE_EN);
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u32 rx_st, tx_st;
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if (dma) {
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rx_st = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT);
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tx_st = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT);
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} else {
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rx_st = readl_relaxed(gi2c->se.base + SE_GENI_RX_FIFO_STATUS);
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tx_st = readl_relaxed(gi2c->se.base + SE_GENI_TX_FIFO_STATUS);
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}
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dev_dbg(gi2c->se.dev, "DMA:%d tx_stat:0x%x, rx_stat:0x%x, irq-stat:0x%x\n",
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dma, tx_st, rx_st, m_stat);
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dev_dbg(gi2c->se.dev, "m_cmd:0x%x, geni_status:0x%x, geni_ios:0x%x\n",
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m_cmd, geni_s, geni_ios);
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}
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static void geni_i2c_err(struct geni_i2c_dev *gi2c, int err)
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{
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if (!gi2c->err)
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gi2c->err = gi2c_log[err].err;
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if (gi2c->cur)
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dev_dbg(gi2c->se.dev, "len:%d, slv-addr:0x%x, RD/WR:%d\n",
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gi2c->cur->len, gi2c->cur->addr, gi2c->cur->flags);
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if (err != NACK && err != GENI_ABORT_DONE) {
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dev_err(gi2c->se.dev, "%s\n", gi2c_log[err].msg);
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geni_i2c_err_misc(gi2c);
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}
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}
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static irqreturn_t geni_i2c_irq(int irq, void *dev)
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{
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struct geni_i2c_dev *gi2c = dev;
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void __iomem *base = gi2c->se.base;
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int j, p;
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u32 m_stat;
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u32 rx_st;
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u32 dm_tx_st;
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u32 dm_rx_st;
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u32 dma;
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u32 val;
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struct i2c_msg *cur;
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spin_lock(&gi2c->lock);
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m_stat = readl_relaxed(base + SE_GENI_M_IRQ_STATUS);
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rx_st = readl_relaxed(base + SE_GENI_RX_FIFO_STATUS);
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dm_tx_st = readl_relaxed(base + SE_DMA_TX_IRQ_STAT);
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dm_rx_st = readl_relaxed(base + SE_DMA_RX_IRQ_STAT);
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dma = readl_relaxed(base + SE_GENI_DMA_MODE_EN);
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cur = gi2c->cur;
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if (!cur ||
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m_stat & (M_CMD_FAILURE_EN | M_CMD_ABORT_EN) ||
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dm_rx_st & (DM_I2C_CB_ERR)) {
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if (m_stat & M_GP_IRQ_1_EN)
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geni_i2c_err(gi2c, NACK);
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if (m_stat & M_GP_IRQ_3_EN)
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geni_i2c_err(gi2c, BUS_PROTO);
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if (m_stat & M_GP_IRQ_4_EN)
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geni_i2c_err(gi2c, ARB_LOST);
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if (m_stat & M_CMD_OVERRUN_EN)
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geni_i2c_err(gi2c, GENI_OVERRUN);
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if (m_stat & M_ILLEGAL_CMD_EN)
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geni_i2c_err(gi2c, GENI_ILLEGAL_CMD);
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if (m_stat & M_CMD_ABORT_EN)
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geni_i2c_err(gi2c, GENI_ABORT_DONE);
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if (m_stat & M_GP_IRQ_0_EN)
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geni_i2c_err(gi2c, GP_IRQ0);
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/* Disable the TX Watermark interrupt to stop TX */
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if (!dma)
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writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG);
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} else if (dma) {
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dev_dbg(gi2c->se.dev, "i2c dma tx:0x%x, dma rx:0x%x\n",
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dm_tx_st, dm_rx_st);
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} else if (cur->flags & I2C_M_RD &&
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m_stat & (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)) {
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u32 rxcnt = rx_st & RX_FIFO_WC_MSK;
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for (j = 0; j < rxcnt; j++) {
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p = 0;
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val = readl_relaxed(base + SE_GENI_RX_FIFOn);
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while (gi2c->cur_rd < cur->len && p < sizeof(val)) {
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cur->buf[gi2c->cur_rd++] = val & 0xff;
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val >>= 8;
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p++;
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}
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if (gi2c->cur_rd == cur->len)
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break;
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}
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} else if (!(cur->flags & I2C_M_RD) &&
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m_stat & M_TX_FIFO_WATERMARK_EN) {
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for (j = 0; j < gi2c->tx_wm; j++) {
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u32 temp;
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val = 0;
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p = 0;
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while (gi2c->cur_wr < cur->len && p < sizeof(val)) {
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temp = cur->buf[gi2c->cur_wr++];
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val |= temp << (p * 8);
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p++;
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}
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writel_relaxed(val, base + SE_GENI_TX_FIFOn);
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/* TX Complete, Disable the TX Watermark interrupt */
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if (gi2c->cur_wr == cur->len) {
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writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG);
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break;
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}
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}
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}
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if (m_stat)
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writel_relaxed(m_stat, base + SE_GENI_M_IRQ_CLEAR);
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if (dma && dm_tx_st)
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writel_relaxed(dm_tx_st, base + SE_DMA_TX_IRQ_CLR);
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if (dma && dm_rx_st)
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writel_relaxed(dm_rx_st, base + SE_DMA_RX_IRQ_CLR);
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/* if this is err with done-bit not set, handle that through timeout. */
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if (m_stat & M_CMD_DONE_EN || m_stat & M_CMD_ABORT_EN ||
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dm_tx_st & TX_DMA_DONE || dm_tx_st & TX_RESET_DONE ||
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dm_rx_st & RX_DMA_DONE || dm_rx_st & RX_RESET_DONE)
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complete(&gi2c->done);
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spin_unlock(&gi2c->lock);
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return IRQ_HANDLED;
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}
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static void geni_i2c_abort_xfer(struct geni_i2c_dev *gi2c)
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{
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u32 val;
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unsigned long time_left = ABORT_TIMEOUT;
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unsigned long flags;
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spin_lock_irqsave(&gi2c->lock, flags);
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geni_i2c_err(gi2c, GENI_TIMEOUT);
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gi2c->cur = NULL;
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geni_se_abort_m_cmd(&gi2c->se);
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spin_unlock_irqrestore(&gi2c->lock, flags);
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do {
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time_left = wait_for_completion_timeout(&gi2c->done, time_left);
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val = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS);
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} while (!(val & M_CMD_ABORT_EN) && time_left);
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if (!(val & M_CMD_ABORT_EN))
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dev_err(gi2c->se.dev, "Timeout abort_m_cmd\n");
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}
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static void geni_i2c_rx_fsm_rst(struct geni_i2c_dev *gi2c)
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{
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u32 val;
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unsigned long time_left = RST_TIMEOUT;
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writel_relaxed(1, gi2c->se.base + SE_DMA_RX_FSM_RST);
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do {
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time_left = wait_for_completion_timeout(&gi2c->done, time_left);
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val = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT);
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} while (!(val & RX_RESET_DONE) && time_left);
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if (!(val & RX_RESET_DONE))
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dev_err(gi2c->se.dev, "Timeout resetting RX_FSM\n");
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}
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static void geni_i2c_tx_fsm_rst(struct geni_i2c_dev *gi2c)
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{
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u32 val;
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unsigned long time_left = RST_TIMEOUT;
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writel_relaxed(1, gi2c->se.base + SE_DMA_TX_FSM_RST);
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do {
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time_left = wait_for_completion_timeout(&gi2c->done, time_left);
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val = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT);
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} while (!(val & TX_RESET_DONE) && time_left);
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if (!(val & TX_RESET_DONE))
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dev_err(gi2c->se.dev, "Timeout resetting TX_FSM\n");
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}
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static void geni_i2c_rx_msg_cleanup(struct geni_i2c_dev *gi2c,
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struct i2c_msg *cur)
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{
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gi2c->cur_rd = 0;
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if (gi2c->dma_buf) {
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if (gi2c->err)
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geni_i2c_rx_fsm_rst(gi2c);
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geni_se_rx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len);
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i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err);
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}
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}
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static void geni_i2c_tx_msg_cleanup(struct geni_i2c_dev *gi2c,
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struct i2c_msg *cur)
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{
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gi2c->cur_wr = 0;
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if (gi2c->dma_buf) {
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if (gi2c->err)
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geni_i2c_tx_fsm_rst(gi2c);
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geni_se_tx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len);
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i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err);
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}
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}
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static int geni_i2c_rx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
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u32 m_param)
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{
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dma_addr_t rx_dma = 0;
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unsigned long time_left;
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void *dma_buf;
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struct geni_se *se = &gi2c->se;
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size_t len = msg->len;
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struct i2c_msg *cur;
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dma_buf = i2c_get_dma_safe_msg_buf(msg, 32);
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if (dma_buf)
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geni_se_select_mode(se, GENI_SE_DMA);
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else
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geni_se_select_mode(se, GENI_SE_FIFO);
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writel_relaxed(len, se->base + SE_I2C_RX_TRANS_LEN);
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geni_se_setup_m_cmd(se, I2C_READ, m_param);
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if (dma_buf && geni_se_rx_dma_prep(se, dma_buf, len, &rx_dma)) {
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geni_se_select_mode(se, GENI_SE_FIFO);
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i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
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dma_buf = NULL;
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} else {
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gi2c->xfer_len = len;
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gi2c->dma_addr = rx_dma;
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gi2c->dma_buf = dma_buf;
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}
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cur = gi2c->cur;
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time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
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if (!time_left)
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geni_i2c_abort_xfer(gi2c);
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geni_i2c_rx_msg_cleanup(gi2c, cur);
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return gi2c->err;
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|
}
|
|
|
|
static int geni_i2c_tx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
|
|
u32 m_param)
|
|
{
|
|
dma_addr_t tx_dma = 0;
|
|
unsigned long time_left;
|
|
void *dma_buf;
|
|
struct geni_se *se = &gi2c->se;
|
|
size_t len = msg->len;
|
|
struct i2c_msg *cur;
|
|
|
|
dma_buf = i2c_get_dma_safe_msg_buf(msg, 32);
|
|
if (dma_buf)
|
|
geni_se_select_mode(se, GENI_SE_DMA);
|
|
else
|
|
geni_se_select_mode(se, GENI_SE_FIFO);
|
|
|
|
writel_relaxed(len, se->base + SE_I2C_TX_TRANS_LEN);
|
|
geni_se_setup_m_cmd(se, I2C_WRITE, m_param);
|
|
|
|
if (dma_buf && geni_se_tx_dma_prep(se, dma_buf, len, &tx_dma)) {
|
|
geni_se_select_mode(se, GENI_SE_FIFO);
|
|
i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
|
|
dma_buf = NULL;
|
|
} else {
|
|
gi2c->xfer_len = len;
|
|
gi2c->dma_addr = tx_dma;
|
|
gi2c->dma_buf = dma_buf;
|
|
}
|
|
|
|
if (!dma_buf) /* Get FIFO IRQ */
|
|
writel_relaxed(1, se->base + SE_GENI_TX_WATERMARK_REG);
|
|
|
|
cur = gi2c->cur;
|
|
time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
|
|
if (!time_left)
|
|
geni_i2c_abort_xfer(gi2c);
|
|
|
|
geni_i2c_tx_msg_cleanup(gi2c, cur);
|
|
|
|
return gi2c->err;
|
|
}
|
|
|
|
static int geni_i2c_xfer(struct i2c_adapter *adap,
|
|
struct i2c_msg msgs[],
|
|
int num)
|
|
{
|
|
struct geni_i2c_dev *gi2c = i2c_get_adapdata(adap);
|
|
int i, ret;
|
|
|
|
gi2c->err = 0;
|
|
reinit_completion(&gi2c->done);
|
|
ret = pm_runtime_get_sync(gi2c->se.dev);
|
|
if (ret < 0) {
|
|
dev_err(gi2c->se.dev, "error turning SE resources:%d\n", ret);
|
|
pm_runtime_put_noidle(gi2c->se.dev);
|
|
/* Set device in suspended since resume failed */
|
|
pm_runtime_set_suspended(gi2c->se.dev);
|
|
return ret;
|
|
}
|
|
|
|
qcom_geni_i2c_conf(gi2c);
|
|
for (i = 0; i < num; i++) {
|
|
u32 m_param = i < (num - 1) ? STOP_STRETCH : 0;
|
|
|
|
m_param |= ((msgs[i].addr << SLV_ADDR_SHFT) & SLV_ADDR_MSK);
|
|
|
|
gi2c->cur = &msgs[i];
|
|
if (msgs[i].flags & I2C_M_RD)
|
|
ret = geni_i2c_rx_one_msg(gi2c, &msgs[i], m_param);
|
|
else
|
|
ret = geni_i2c_tx_one_msg(gi2c, &msgs[i], m_param);
|
|
|
|
if (ret)
|
|
break;
|
|
}
|
|
if (ret == 0)
|
|
ret = num;
|
|
|
|
pm_runtime_mark_last_busy(gi2c->se.dev);
|
|
pm_runtime_put_autosuspend(gi2c->se.dev);
|
|
gi2c->cur = NULL;
|
|
gi2c->err = 0;
|
|
return ret;
|
|
}
|
|
|
|
static u32 geni_i2c_func(struct i2c_adapter *adap)
|
|
{
|
|
return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
|
|
}
|
|
|
|
static const struct i2c_algorithm geni_i2c_algo = {
|
|
.master_xfer = geni_i2c_xfer,
|
|
.functionality = geni_i2c_func,
|
|
};
|
|
|
|
#ifdef CONFIG_ACPI
|
|
static const struct acpi_device_id geni_i2c_acpi_match[] = {
|
|
{ "QCOM0220"},
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(acpi, geni_i2c_acpi_match);
|
|
#endif
|
|
|
|
static int geni_i2c_probe(struct platform_device *pdev)
|
|
{
|
|
struct geni_i2c_dev *gi2c;
|
|
struct resource *res;
|
|
u32 proto, tx_depth;
|
|
int ret;
|
|
struct device *dev = &pdev->dev;
|
|
|
|
gi2c = devm_kzalloc(dev, sizeof(*gi2c), GFP_KERNEL);
|
|
if (!gi2c)
|
|
return -ENOMEM;
|
|
|
|
gi2c->se.dev = dev;
|
|
gi2c->se.wrapper = dev_get_drvdata(dev->parent);
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
gi2c->se.base = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(gi2c->se.base))
|
|
return PTR_ERR(gi2c->se.base);
|
|
|
|
gi2c->se.clk = devm_clk_get(dev, "se");
|
|
if (IS_ERR(gi2c->se.clk) && !has_acpi_companion(dev))
|
|
return PTR_ERR(gi2c->se.clk);
|
|
|
|
ret = device_property_read_u32(dev, "clock-frequency",
|
|
&gi2c->clk_freq_out);
|
|
if (ret) {
|
|
dev_info(dev, "Bus frequency not specified, default to 100kHz.\n");
|
|
gi2c->clk_freq_out = KHZ(100);
|
|
}
|
|
|
|
if (has_acpi_companion(dev))
|
|
ACPI_COMPANION_SET(&gi2c->adap.dev, ACPI_COMPANION(dev));
|
|
|
|
gi2c->irq = platform_get_irq(pdev, 0);
|
|
if (gi2c->irq < 0)
|
|
return gi2c->irq;
|
|
|
|
ret = geni_i2c_clk_map_idx(gi2c);
|
|
if (ret) {
|
|
dev_err(dev, "Invalid clk frequency %d Hz: %d\n",
|
|
gi2c->clk_freq_out, ret);
|
|
return ret;
|
|
}
|
|
|
|
gi2c->adap.algo = &geni_i2c_algo;
|
|
init_completion(&gi2c->done);
|
|
spin_lock_init(&gi2c->lock);
|
|
platform_set_drvdata(pdev, gi2c);
|
|
ret = devm_request_irq(dev, gi2c->irq, geni_i2c_irq, 0,
|
|
dev_name(dev), gi2c);
|
|
if (ret) {
|
|
dev_err(dev, "Request_irq failed:%d: err:%d\n",
|
|
gi2c->irq, ret);
|
|
return ret;
|
|
}
|
|
/* Disable the interrupt so that the system can enter low-power mode */
|
|
disable_irq(gi2c->irq);
|
|
i2c_set_adapdata(&gi2c->adap, gi2c);
|
|
gi2c->adap.dev.parent = dev;
|
|
gi2c->adap.dev.of_node = dev->of_node;
|
|
strlcpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name));
|
|
|
|
ret = geni_icc_get(&gi2c->se, "qup-memory");
|
|
if (ret)
|
|
return ret;
|
|
/*
|
|
* Set the bus quota for core and cpu to a reasonable value for
|
|
* register access.
|
|
* Set quota for DDR based on bus speed.
|
|
*/
|
|
gi2c->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
|
|
gi2c->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
|
|
gi2c->se.icc_paths[GENI_TO_DDR].avg_bw = Bps_to_icc(gi2c->clk_freq_out);
|
|
|
|
ret = geni_icc_set_bw(&gi2c->se);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = geni_se_resources_on(&gi2c->se);
|
|
if (ret) {
|
|
dev_err(dev, "Error turning on resources %d\n", ret);
|
|
return ret;
|
|
}
|
|
proto = geni_se_read_proto(&gi2c->se);
|
|
tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se);
|
|
if (proto != GENI_SE_I2C) {
|
|
dev_err(dev, "Invalid proto %d\n", proto);
|
|
geni_se_resources_off(&gi2c->se);
|
|
return -ENXIO;
|
|
}
|
|
gi2c->tx_wm = tx_depth - 1;
|
|
geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth);
|
|
geni_se_config_packing(&gi2c->se, BITS_PER_BYTE, PACKING_BYTES_PW,
|
|
true, true, true);
|
|
ret = geni_se_resources_off(&gi2c->se);
|
|
if (ret) {
|
|
dev_err(dev, "Error turning off resources %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = geni_icc_disable(&gi2c->se);
|
|
if (ret)
|
|
return ret;
|
|
|
|
dev_dbg(dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth);
|
|
|
|
gi2c->suspended = 1;
|
|
pm_runtime_set_suspended(gi2c->se.dev);
|
|
pm_runtime_set_autosuspend_delay(gi2c->se.dev, I2C_AUTO_SUSPEND_DELAY);
|
|
pm_runtime_use_autosuspend(gi2c->se.dev);
|
|
pm_runtime_enable(gi2c->se.dev);
|
|
|
|
ret = i2c_add_adapter(&gi2c->adap);
|
|
if (ret) {
|
|
dev_err(dev, "Error adding i2c adapter %d\n", ret);
|
|
pm_runtime_disable(gi2c->se.dev);
|
|
return ret;
|
|
}
|
|
|
|
dev_dbg(dev, "Geni-I2C adaptor successfully added\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int geni_i2c_remove(struct platform_device *pdev)
|
|
{
|
|
struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev);
|
|
|
|
i2c_del_adapter(&gi2c->adap);
|
|
pm_runtime_disable(gi2c->se.dev);
|
|
return 0;
|
|
}
|
|
|
|
static void geni_i2c_shutdown(struct platform_device *pdev)
|
|
{
|
|
struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev);
|
|
|
|
/* Make client i2c transfers start failing */
|
|
i2c_mark_adapter_suspended(&gi2c->adap);
|
|
}
|
|
|
|
static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev)
|
|
{
|
|
int ret;
|
|
struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
|
|
|
|
disable_irq(gi2c->irq);
|
|
ret = geni_se_resources_off(&gi2c->se);
|
|
if (ret) {
|
|
enable_irq(gi2c->irq);
|
|
return ret;
|
|
|
|
} else {
|
|
gi2c->suspended = 1;
|
|
}
|
|
|
|
return geni_icc_disable(&gi2c->se);
|
|
}
|
|
|
|
static int __maybe_unused geni_i2c_runtime_resume(struct device *dev)
|
|
{
|
|
int ret;
|
|
struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
|
|
|
|
ret = geni_icc_enable(&gi2c->se);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = geni_se_resources_on(&gi2c->se);
|
|
if (ret)
|
|
return ret;
|
|
|
|
enable_irq(gi2c->irq);
|
|
gi2c->suspended = 0;
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused geni_i2c_suspend_noirq(struct device *dev)
|
|
{
|
|
struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
|
|
|
|
i2c_mark_adapter_suspended(&gi2c->adap);
|
|
|
|
if (!gi2c->suspended) {
|
|
geni_i2c_runtime_suspend(dev);
|
|
pm_runtime_disable(dev);
|
|
pm_runtime_set_suspended(dev);
|
|
pm_runtime_enable(dev);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused geni_i2c_resume_noirq(struct device *dev)
|
|
{
|
|
struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
|
|
|
|
i2c_mark_adapter_resumed(&gi2c->adap);
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops geni_i2c_pm_ops = {
|
|
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(geni_i2c_suspend_noirq, geni_i2c_resume_noirq)
|
|
SET_RUNTIME_PM_OPS(geni_i2c_runtime_suspend, geni_i2c_runtime_resume,
|
|
NULL)
|
|
};
|
|
|
|
static const struct of_device_id geni_i2c_dt_match[] = {
|
|
{ .compatible = "qcom,geni-i2c" },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, geni_i2c_dt_match);
|
|
|
|
static struct platform_driver geni_i2c_driver = {
|
|
.probe = geni_i2c_probe,
|
|
.remove = geni_i2c_remove,
|
|
.shutdown = geni_i2c_shutdown,
|
|
.driver = {
|
|
.name = "geni_i2c",
|
|
.pm = &geni_i2c_pm_ops,
|
|
.of_match_table = geni_i2c_dt_match,
|
|
.acpi_match_table = ACPI_PTR(geni_i2c_acpi_match),
|
|
},
|
|
};
|
|
|
|
module_platform_driver(geni_i2c_driver);
|
|
|
|
MODULE_DESCRIPTION("I2C Controller Driver for GENI based QUP cores");
|
|
MODULE_LICENSE("GPL v2");
|