429 строки
10 KiB
C
429 строки
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Analog Devices Generic AXI ADC IP core
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* Link: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip
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*
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* Copyright 2012-2020 Analog Devices Inc.
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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#include <linux/iio/buffer.h>
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#include <linux/iio/buffer-dmaengine.h>
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#include <linux/fpga/adi-axi-common.h>
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#include <linux/iio/adc/adi-axi-adc.h>
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/*
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* Register definitions:
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* https://wiki.analog.com/resources/fpga/docs/axi_adc_ip#register_map
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*/
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/* ADC controls */
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#define ADI_AXI_REG_RSTN 0x0040
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#define ADI_AXI_REG_RSTN_CE_N BIT(2)
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#define ADI_AXI_REG_RSTN_MMCM_RSTN BIT(1)
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#define ADI_AXI_REG_RSTN_RSTN BIT(0)
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/* ADC Channel controls */
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#define ADI_AXI_REG_CHAN_CTRL(c) (0x0400 + (c) * 0x40)
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#define ADI_AXI_REG_CHAN_CTRL_LB_OWR BIT(11)
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#define ADI_AXI_REG_CHAN_CTRL_PN_SEL_OWR BIT(10)
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#define ADI_AXI_REG_CHAN_CTRL_IQCOR_EN BIT(9)
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#define ADI_AXI_REG_CHAN_CTRL_DCFILT_EN BIT(8)
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#define ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT BIT(6)
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#define ADI_AXI_REG_CHAN_CTRL_FMT_TYPE BIT(5)
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#define ADI_AXI_REG_CHAN_CTRL_FMT_EN BIT(4)
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#define ADI_AXI_REG_CHAN_CTRL_PN_TYPE_OWR BIT(1)
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#define ADI_AXI_REG_CHAN_CTRL_ENABLE BIT(0)
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#define ADI_AXI_REG_CHAN_CTRL_DEFAULTS \
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(ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT | \
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ADI_AXI_REG_CHAN_CTRL_FMT_EN | \
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ADI_AXI_REG_CHAN_CTRL_ENABLE)
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struct adi_axi_adc_core_info {
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unsigned int version;
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};
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struct adi_axi_adc_state {
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struct mutex lock;
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struct adi_axi_adc_client *client;
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void __iomem *regs;
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};
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struct adi_axi_adc_client {
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struct list_head entry;
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struct adi_axi_adc_conv conv;
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struct adi_axi_adc_state *state;
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struct device *dev;
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const struct adi_axi_adc_core_info *info;
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};
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static LIST_HEAD(registered_clients);
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static DEFINE_MUTEX(registered_clients_lock);
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static struct adi_axi_adc_client *conv_to_client(struct adi_axi_adc_conv *conv)
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{
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return container_of(conv, struct adi_axi_adc_client, conv);
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}
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void *adi_axi_adc_conv_priv(struct adi_axi_adc_conv *conv)
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{
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struct adi_axi_adc_client *cl = conv_to_client(conv);
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return (char *)cl + ALIGN(sizeof(struct adi_axi_adc_client), IIO_ALIGN);
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}
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EXPORT_SYMBOL_GPL(adi_axi_adc_conv_priv);
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static void adi_axi_adc_write(struct adi_axi_adc_state *st,
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unsigned int reg,
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unsigned int val)
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{
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iowrite32(val, st->regs + reg);
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}
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static unsigned int adi_axi_adc_read(struct adi_axi_adc_state *st,
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unsigned int reg)
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{
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return ioread32(st->regs + reg);
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}
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static int adi_axi_adc_config_dma_buffer(struct device *dev,
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struct iio_dev *indio_dev)
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{
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const char *dma_name;
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if (!device_property_present(dev, "dmas"))
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return 0;
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if (device_property_read_string(dev, "dma-names", &dma_name))
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dma_name = "rx";
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return devm_iio_dmaengine_buffer_setup(indio_dev->dev.parent,
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indio_dev, dma_name);
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}
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static int adi_axi_adc_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long mask)
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{
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struct adi_axi_adc_state *st = iio_priv(indio_dev);
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struct adi_axi_adc_conv *conv = &st->client->conv;
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if (!conv->read_raw)
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return -EOPNOTSUPP;
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return conv->read_raw(conv, chan, val, val2, mask);
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}
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static int adi_axi_adc_write_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int val, int val2, long mask)
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{
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struct adi_axi_adc_state *st = iio_priv(indio_dev);
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struct adi_axi_adc_conv *conv = &st->client->conv;
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if (!conv->write_raw)
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return -EOPNOTSUPP;
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return conv->write_raw(conv, chan, val, val2, mask);
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}
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static int adi_axi_adc_read_avail(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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const int **vals, int *type, int *length,
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long mask)
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{
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struct adi_axi_adc_state *st = iio_priv(indio_dev);
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struct adi_axi_adc_conv *conv = &st->client->conv;
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if (!conv->read_avail)
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return -EOPNOTSUPP;
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return conv->read_avail(conv, chan, vals, type, length, mask);
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}
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static int adi_axi_adc_update_scan_mode(struct iio_dev *indio_dev,
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const unsigned long *scan_mask)
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{
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struct adi_axi_adc_state *st = iio_priv(indio_dev);
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struct adi_axi_adc_conv *conv = &st->client->conv;
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unsigned int i, ctrl;
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for (i = 0; i < conv->chip_info->num_channels; i++) {
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ctrl = adi_axi_adc_read(st, ADI_AXI_REG_CHAN_CTRL(i));
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if (test_bit(i, scan_mask))
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ctrl |= ADI_AXI_REG_CHAN_CTRL_ENABLE;
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else
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ctrl &= ~ADI_AXI_REG_CHAN_CTRL_ENABLE;
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adi_axi_adc_write(st, ADI_AXI_REG_CHAN_CTRL(i), ctrl);
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}
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return 0;
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}
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static struct adi_axi_adc_conv *adi_axi_adc_conv_register(struct device *dev,
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size_t sizeof_priv)
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{
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struct adi_axi_adc_client *cl;
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size_t alloc_size;
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alloc_size = ALIGN(sizeof(struct adi_axi_adc_client), IIO_ALIGN);
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if (sizeof_priv)
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alloc_size += ALIGN(sizeof_priv, IIO_ALIGN);
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cl = kzalloc(alloc_size, GFP_KERNEL);
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if (!cl)
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return ERR_PTR(-ENOMEM);
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mutex_lock(®istered_clients_lock);
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cl->dev = get_device(dev);
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list_add_tail(&cl->entry, ®istered_clients);
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mutex_unlock(®istered_clients_lock);
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return &cl->conv;
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}
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static void adi_axi_adc_conv_unregister(struct adi_axi_adc_conv *conv)
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{
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struct adi_axi_adc_client *cl = conv_to_client(conv);
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mutex_lock(®istered_clients_lock);
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list_del(&cl->entry);
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put_device(cl->dev);
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mutex_unlock(®istered_clients_lock);
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kfree(cl);
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}
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static void devm_adi_axi_adc_conv_release(void *conv)
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{
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adi_axi_adc_conv_unregister(conv);
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}
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struct adi_axi_adc_conv *devm_adi_axi_adc_conv_register(struct device *dev,
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size_t sizeof_priv)
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{
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struct adi_axi_adc_conv *conv;
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int ret;
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conv = adi_axi_adc_conv_register(dev, sizeof_priv);
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if (IS_ERR(conv))
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return conv;
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ret = devm_add_action_or_reset(dev, devm_adi_axi_adc_conv_release,
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conv);
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if (ret)
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return ERR_PTR(ret);
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return conv;
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}
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EXPORT_SYMBOL_GPL(devm_adi_axi_adc_conv_register);
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static const struct iio_info adi_axi_adc_info = {
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.read_raw = &adi_axi_adc_read_raw,
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.write_raw = &adi_axi_adc_write_raw,
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.update_scan_mode = &adi_axi_adc_update_scan_mode,
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.read_avail = &adi_axi_adc_read_avail,
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};
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static const struct adi_axi_adc_core_info adi_axi_adc_10_0_a_info = {
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.version = ADI_AXI_PCORE_VER(10, 0, 'a'),
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};
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static struct adi_axi_adc_client *adi_axi_adc_attach_client(struct device *dev)
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{
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const struct adi_axi_adc_core_info *info;
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struct adi_axi_adc_client *cl;
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struct device_node *cln;
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info = of_device_get_match_data(dev);
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if (!info)
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return ERR_PTR(-ENODEV);
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cln = of_parse_phandle(dev->of_node, "adi,adc-dev", 0);
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if (!cln) {
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dev_err(dev, "No 'adi,adc-dev' node defined\n");
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return ERR_PTR(-ENODEV);
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}
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mutex_lock(®istered_clients_lock);
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list_for_each_entry(cl, ®istered_clients, entry) {
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if (!cl->dev)
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continue;
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if (cl->dev->of_node != cln)
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continue;
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if (!try_module_get(cl->dev->driver->owner)) {
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mutex_unlock(®istered_clients_lock);
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of_node_put(cln);
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return ERR_PTR(-ENODEV);
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}
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get_device(cl->dev);
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cl->info = info;
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mutex_unlock(®istered_clients_lock);
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of_node_put(cln);
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return cl;
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}
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mutex_unlock(®istered_clients_lock);
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of_node_put(cln);
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return ERR_PTR(-EPROBE_DEFER);
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}
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static int adi_axi_adc_setup_channels(struct device *dev,
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struct adi_axi_adc_state *st)
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{
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struct adi_axi_adc_conv *conv = &st->client->conv;
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int i, ret;
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if (conv->preenable_setup) {
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ret = conv->preenable_setup(conv);
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if (ret)
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return ret;
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}
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for (i = 0; i < conv->chip_info->num_channels; i++) {
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adi_axi_adc_write(st, ADI_AXI_REG_CHAN_CTRL(i),
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ADI_AXI_REG_CHAN_CTRL_DEFAULTS);
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}
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return 0;
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}
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static void axi_adc_reset(struct adi_axi_adc_state *st)
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{
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adi_axi_adc_write(st, ADI_AXI_REG_RSTN, 0);
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mdelay(10);
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adi_axi_adc_write(st, ADI_AXI_REG_RSTN, ADI_AXI_REG_RSTN_MMCM_RSTN);
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mdelay(10);
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adi_axi_adc_write(st, ADI_AXI_REG_RSTN,
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ADI_AXI_REG_RSTN_RSTN | ADI_AXI_REG_RSTN_MMCM_RSTN);
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}
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static void adi_axi_adc_cleanup(void *data)
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{
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struct adi_axi_adc_client *cl = data;
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put_device(cl->dev);
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module_put(cl->dev->driver->owner);
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}
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static int adi_axi_adc_probe(struct platform_device *pdev)
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{
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struct adi_axi_adc_conv *conv;
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struct iio_dev *indio_dev;
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struct adi_axi_adc_client *cl;
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struct adi_axi_adc_state *st;
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unsigned int ver;
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int ret;
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cl = adi_axi_adc_attach_client(&pdev->dev);
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if (IS_ERR(cl))
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return PTR_ERR(cl);
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ret = devm_add_action_or_reset(&pdev->dev, adi_axi_adc_cleanup, cl);
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if (ret)
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return ret;
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indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
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if (indio_dev == NULL)
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return -ENOMEM;
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st = iio_priv(indio_dev);
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st->client = cl;
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cl->state = st;
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mutex_init(&st->lock);
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st->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(st->regs))
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return PTR_ERR(st->regs);
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conv = &st->client->conv;
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axi_adc_reset(st);
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ver = adi_axi_adc_read(st, ADI_AXI_REG_VERSION);
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if (cl->info->version > ver) {
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dev_err(&pdev->dev,
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"IP core version is too old. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n",
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ADI_AXI_PCORE_VER_MAJOR(cl->info->version),
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ADI_AXI_PCORE_VER_MINOR(cl->info->version),
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ADI_AXI_PCORE_VER_PATCH(cl->info->version),
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ADI_AXI_PCORE_VER_MAJOR(ver),
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ADI_AXI_PCORE_VER_MINOR(ver),
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ADI_AXI_PCORE_VER_PATCH(ver));
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return -ENODEV;
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}
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indio_dev->info = &adi_axi_adc_info;
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indio_dev->name = "adi-axi-adc";
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indio_dev->modes = INDIO_DIRECT_MODE;
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indio_dev->num_channels = conv->chip_info->num_channels;
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indio_dev->channels = conv->chip_info->channels;
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ret = adi_axi_adc_config_dma_buffer(&pdev->dev, indio_dev);
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if (ret)
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return ret;
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ret = adi_axi_adc_setup_channels(&pdev->dev, st);
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if (ret)
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return ret;
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ret = devm_iio_device_register(&pdev->dev, indio_dev);
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if (ret)
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return ret;
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dev_info(&pdev->dev, "AXI ADC IP core (%d.%.2d.%c) probed\n",
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ADI_AXI_PCORE_VER_MAJOR(ver),
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ADI_AXI_PCORE_VER_MINOR(ver),
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ADI_AXI_PCORE_VER_PATCH(ver));
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return 0;
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}
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/* Match table for of_platform binding */
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static const struct of_device_id adi_axi_adc_of_match[] = {
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{ .compatible = "adi,axi-adc-10.0.a", .data = &adi_axi_adc_10_0_a_info },
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{ /* end of list */ }
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};
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MODULE_DEVICE_TABLE(of, adi_axi_adc_of_match);
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static struct platform_driver adi_axi_adc_driver = {
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.driver = {
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.name = KBUILD_MODNAME,
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.of_match_table = adi_axi_adc_of_match,
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},
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.probe = adi_axi_adc_probe,
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};
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module_platform_driver(adi_axi_adc_driver);
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MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
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MODULE_DESCRIPTION("Analog Devices Generic AXI ADC IP core driver");
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MODULE_LICENSE("GPL v2");
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