887 строки
23 KiB
C
887 строки
23 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/* Broadcom BCM54140 Quad SGMII/QSGMII Copper/Fiber Gigabit PHY
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*
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* Copyright (c) 2020 Michael Walle <michael@walle.cc>
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*/
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#include <linux/bitfield.h>
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#include <linux/brcmphy.h>
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#include <linux/hwmon.h>
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#include <linux/module.h>
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#include <linux/phy.h>
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#include "bcm-phy-lib.h"
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/* RDB per-port registers
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*/
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#define BCM54140_RDB_ISR 0x00a /* interrupt status */
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#define BCM54140_RDB_IMR 0x00b /* interrupt mask */
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#define BCM54140_RDB_INT_LINK BIT(1) /* link status changed */
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#define BCM54140_RDB_INT_SPEED BIT(2) /* link speed change */
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#define BCM54140_RDB_INT_DUPLEX BIT(3) /* duplex mode changed */
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#define BCM54140_RDB_SPARE1 0x012 /* spare control 1 */
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#define BCM54140_RDB_SPARE1_LSLM BIT(2) /* link speed LED mode */
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#define BCM54140_RDB_SPARE2 0x014 /* spare control 2 */
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#define BCM54140_RDB_SPARE2_WS_RTRY_DIS BIT(8) /* wirespeed retry disable */
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#define BCM54140_RDB_SPARE2_WS_RTRY_LIMIT GENMASK(4, 2) /* retry limit */
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#define BCM54140_RDB_SPARE3 0x015 /* spare control 3 */
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#define BCM54140_RDB_SPARE3_BIT0 BIT(0)
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#define BCM54140_RDB_LED_CTRL 0x019 /* LED control */
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#define BCM54140_RDB_LED_CTRL_ACTLINK0 BIT(4)
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#define BCM54140_RDB_LED_CTRL_ACTLINK1 BIT(8)
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#define BCM54140_RDB_C_APWR 0x01a /* auto power down control */
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#define BCM54140_RDB_C_APWR_SINGLE_PULSE BIT(8) /* single pulse */
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#define BCM54140_RDB_C_APWR_APD_MODE_DIS 0 /* ADP disable */
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#define BCM54140_RDB_C_APWR_APD_MODE_EN 1 /* ADP enable */
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#define BCM54140_RDB_C_APWR_APD_MODE_DIS2 2 /* ADP disable */
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#define BCM54140_RDB_C_APWR_APD_MODE_EN_ANEG 3 /* ADP enable w/ aneg */
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#define BCM54140_RDB_C_APWR_APD_MODE_MASK GENMASK(6, 5)
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#define BCM54140_RDB_C_APWR_SLP_TIM_MASK BIT(4)/* sleep timer */
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#define BCM54140_RDB_C_APWR_SLP_TIM_2_7 0 /* 2.7s */
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#define BCM54140_RDB_C_APWR_SLP_TIM_5_4 1 /* 5.4s */
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#define BCM54140_RDB_C_PWR 0x02a /* copper power control */
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#define BCM54140_RDB_C_PWR_ISOLATE BIT(5) /* super isolate mode */
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#define BCM54140_RDB_C_MISC_CTRL 0x02f /* misc copper control */
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#define BCM54140_RDB_C_MISC_CTRL_WS_EN BIT(4) /* wirespeed enable */
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/* RDB global registers
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*/
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#define BCM54140_RDB_TOP_IMR 0x82d /* interrupt mask */
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#define BCM54140_RDB_TOP_IMR_PORT0 BIT(4)
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#define BCM54140_RDB_TOP_IMR_PORT1 BIT(5)
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#define BCM54140_RDB_TOP_IMR_PORT2 BIT(6)
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#define BCM54140_RDB_TOP_IMR_PORT3 BIT(7)
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#define BCM54140_RDB_MON_CTRL 0x831 /* monitor control */
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#define BCM54140_RDB_MON_CTRL_V_MODE BIT(3) /* voltage mode */
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#define BCM54140_RDB_MON_CTRL_SEL_MASK GENMASK(2, 1)
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#define BCM54140_RDB_MON_CTRL_SEL_TEMP 0 /* meassure temperature */
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#define BCM54140_RDB_MON_CTRL_SEL_1V0 1 /* meassure AVDDL 1.0V */
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#define BCM54140_RDB_MON_CTRL_SEL_3V3 2 /* meassure AVDDH 3.3V */
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#define BCM54140_RDB_MON_CTRL_SEL_RR 3 /* meassure all round-robin */
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#define BCM54140_RDB_MON_CTRL_PWR_DOWN BIT(0) /* power-down monitor */
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#define BCM54140_RDB_MON_TEMP_VAL 0x832 /* temperature value */
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#define BCM54140_RDB_MON_TEMP_MAX 0x833 /* temperature high thresh */
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#define BCM54140_RDB_MON_TEMP_MIN 0x834 /* temperature low thresh */
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#define BCM54140_RDB_MON_TEMP_DATA_MASK GENMASK(9, 0)
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#define BCM54140_RDB_MON_1V0_VAL 0x835 /* AVDDL 1.0V value */
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#define BCM54140_RDB_MON_1V0_MAX 0x836 /* AVDDL 1.0V high thresh */
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#define BCM54140_RDB_MON_1V0_MIN 0x837 /* AVDDL 1.0V low thresh */
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#define BCM54140_RDB_MON_1V0_DATA_MASK GENMASK(10, 0)
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#define BCM54140_RDB_MON_3V3_VAL 0x838 /* AVDDH 3.3V value */
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#define BCM54140_RDB_MON_3V3_MAX 0x839 /* AVDDH 3.3V high thresh */
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#define BCM54140_RDB_MON_3V3_MIN 0x83a /* AVDDH 3.3V low thresh */
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#define BCM54140_RDB_MON_3V3_DATA_MASK GENMASK(11, 0)
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#define BCM54140_RDB_MON_ISR 0x83b /* interrupt status */
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#define BCM54140_RDB_MON_ISR_3V3 BIT(2) /* AVDDH 3.3V alarm */
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#define BCM54140_RDB_MON_ISR_1V0 BIT(1) /* AVDDL 1.0V alarm */
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#define BCM54140_RDB_MON_ISR_TEMP BIT(0) /* temperature alarm */
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/* According to the datasheet the formula is:
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* T = 413.35 - (0.49055 * bits[9:0])
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*/
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#define BCM54140_HWMON_TO_TEMP(v) (413350L - (v) * 491)
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#define BCM54140_HWMON_FROM_TEMP(v) DIV_ROUND_CLOSEST_ULL(413350L - (v), 491)
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/* According to the datasheet the formula is:
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* U = bits[11:0] / 1024 * 220 / 0.2
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*
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* Normalized:
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* U = bits[11:0] / 4096 * 2514
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*/
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#define BCM54140_HWMON_TO_IN_1V0(v) ((v) * 2514 >> 11)
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#define BCM54140_HWMON_FROM_IN_1V0(v) DIV_ROUND_CLOSEST_ULL(((v) << 11), 2514)
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/* According to the datasheet the formula is:
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* U = bits[10:0] / 1024 * 880 / 0.7
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*
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* Normalized:
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* U = bits[10:0] / 2048 * 4400
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*/
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#define BCM54140_HWMON_TO_IN_3V3(v) ((v) * 4400 >> 12)
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#define BCM54140_HWMON_FROM_IN_3V3(v) DIV_ROUND_CLOSEST_ULL(((v) << 12), 4400)
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#define BCM54140_HWMON_TO_IN(ch, v) ((ch) ? BCM54140_HWMON_TO_IN_3V3(v) \
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: BCM54140_HWMON_TO_IN_1V0(v))
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#define BCM54140_HWMON_FROM_IN(ch, v) ((ch) ? BCM54140_HWMON_FROM_IN_3V3(v) \
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: BCM54140_HWMON_FROM_IN_1V0(v))
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#define BCM54140_HWMON_IN_MASK(ch) ((ch) ? BCM54140_RDB_MON_3V3_DATA_MASK \
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: BCM54140_RDB_MON_1V0_DATA_MASK)
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#define BCM54140_HWMON_IN_VAL_REG(ch) ((ch) ? BCM54140_RDB_MON_3V3_VAL \
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: BCM54140_RDB_MON_1V0_VAL)
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#define BCM54140_HWMON_IN_MIN_REG(ch) ((ch) ? BCM54140_RDB_MON_3V3_MIN \
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: BCM54140_RDB_MON_1V0_MIN)
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#define BCM54140_HWMON_IN_MAX_REG(ch) ((ch) ? BCM54140_RDB_MON_3V3_MAX \
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: BCM54140_RDB_MON_1V0_MAX)
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#define BCM54140_HWMON_IN_ALARM_BIT(ch) ((ch) ? BCM54140_RDB_MON_ISR_3V3 \
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: BCM54140_RDB_MON_ISR_1V0)
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/* This PHY has two different PHY IDs depening on its MODE_SEL pin. This
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* pin choses between 4x SGMII and QSGMII mode:
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* AE02_5009 4x SGMII
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* AE02_5019 QSGMII
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*/
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#define BCM54140_PHY_ID_MASK 0xffffffe8
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#define BCM54140_PHY_ID_REV(phy_id) ((phy_id) & 0x7)
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#define BCM54140_REV_B0 1
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#define BCM54140_DEFAULT_DOWNSHIFT 5
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#define BCM54140_MAX_DOWNSHIFT 9
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struct bcm54140_priv {
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int port;
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int base_addr;
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#if IS_ENABLED(CONFIG_HWMON)
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/* protect the alarm bits */
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struct mutex alarm_lock;
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u16 alarm;
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#endif
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};
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#if IS_ENABLED(CONFIG_HWMON)
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static umode_t bcm54140_hwmon_is_visible(const void *data,
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enum hwmon_sensor_types type,
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u32 attr, int channel)
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{
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switch (type) {
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case hwmon_in:
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switch (attr) {
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case hwmon_in_min:
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case hwmon_in_max:
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return 0644;
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case hwmon_in_label:
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case hwmon_in_input:
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case hwmon_in_alarm:
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return 0444;
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default:
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return 0;
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}
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case hwmon_temp:
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switch (attr) {
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case hwmon_temp_min:
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case hwmon_temp_max:
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return 0644;
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case hwmon_temp_input:
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case hwmon_temp_alarm:
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return 0444;
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default:
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return 0;
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}
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default:
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return 0;
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}
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}
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static int bcm54140_hwmon_read_alarm(struct device *dev, unsigned int bit,
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long *val)
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{
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struct phy_device *phydev = dev_get_drvdata(dev);
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struct bcm54140_priv *priv = phydev->priv;
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int tmp, ret = 0;
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mutex_lock(&priv->alarm_lock);
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/* latch any alarm bits */
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tmp = bcm_phy_read_rdb(phydev, BCM54140_RDB_MON_ISR);
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if (tmp < 0) {
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ret = tmp;
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goto out;
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}
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priv->alarm |= tmp;
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*val = !!(priv->alarm & bit);
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priv->alarm &= ~bit;
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out:
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mutex_unlock(&priv->alarm_lock);
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return ret;
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}
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static int bcm54140_hwmon_read_temp(struct device *dev, u32 attr, long *val)
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{
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struct phy_device *phydev = dev_get_drvdata(dev);
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u16 reg;
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int tmp;
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switch (attr) {
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case hwmon_temp_input:
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reg = BCM54140_RDB_MON_TEMP_VAL;
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break;
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case hwmon_temp_min:
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reg = BCM54140_RDB_MON_TEMP_MIN;
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break;
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case hwmon_temp_max:
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reg = BCM54140_RDB_MON_TEMP_MAX;
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break;
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case hwmon_temp_alarm:
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return bcm54140_hwmon_read_alarm(dev,
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BCM54140_RDB_MON_ISR_TEMP,
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val);
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default:
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return -EOPNOTSUPP;
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}
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tmp = bcm_phy_read_rdb(phydev, reg);
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if (tmp < 0)
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return tmp;
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*val = BCM54140_HWMON_TO_TEMP(tmp & BCM54140_RDB_MON_TEMP_DATA_MASK);
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return 0;
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}
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static int bcm54140_hwmon_read_in(struct device *dev, u32 attr,
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int channel, long *val)
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{
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struct phy_device *phydev = dev_get_drvdata(dev);
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u16 bit, reg;
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int tmp;
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switch (attr) {
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case hwmon_in_input:
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reg = BCM54140_HWMON_IN_VAL_REG(channel);
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break;
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case hwmon_in_min:
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reg = BCM54140_HWMON_IN_MIN_REG(channel);
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break;
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case hwmon_in_max:
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reg = BCM54140_HWMON_IN_MAX_REG(channel);
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break;
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case hwmon_in_alarm:
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bit = BCM54140_HWMON_IN_ALARM_BIT(channel);
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return bcm54140_hwmon_read_alarm(dev, bit, val);
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default:
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return -EOPNOTSUPP;
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}
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tmp = bcm_phy_read_rdb(phydev, reg);
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if (tmp < 0)
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return tmp;
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tmp &= BCM54140_HWMON_IN_MASK(channel);
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*val = BCM54140_HWMON_TO_IN(channel, tmp);
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return 0;
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}
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static int bcm54140_hwmon_read(struct device *dev,
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enum hwmon_sensor_types type, u32 attr,
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int channel, long *val)
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{
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switch (type) {
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case hwmon_temp:
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return bcm54140_hwmon_read_temp(dev, attr, val);
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case hwmon_in:
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return bcm54140_hwmon_read_in(dev, attr, channel, val);
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default:
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return -EOPNOTSUPP;
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}
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}
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static const char *const bcm54140_hwmon_in_labels[] = {
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"AVDDL",
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"AVDDH",
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};
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static int bcm54140_hwmon_read_string(struct device *dev,
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enum hwmon_sensor_types type, u32 attr,
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int channel, const char **str)
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{
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switch (type) {
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case hwmon_in:
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switch (attr) {
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case hwmon_in_label:
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*str = bcm54140_hwmon_in_labels[channel];
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return 0;
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default:
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return -EOPNOTSUPP;
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}
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default:
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return -EOPNOTSUPP;
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}
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}
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static int bcm54140_hwmon_write_temp(struct device *dev, u32 attr,
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int channel, long val)
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{
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struct phy_device *phydev = dev_get_drvdata(dev);
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u16 mask = BCM54140_RDB_MON_TEMP_DATA_MASK;
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u16 reg;
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val = clamp_val(val, BCM54140_HWMON_TO_TEMP(mask),
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BCM54140_HWMON_TO_TEMP(0));
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switch (attr) {
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case hwmon_temp_min:
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reg = BCM54140_RDB_MON_TEMP_MIN;
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break;
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case hwmon_temp_max:
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reg = BCM54140_RDB_MON_TEMP_MAX;
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break;
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default:
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return -EOPNOTSUPP;
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}
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return bcm_phy_modify_rdb(phydev, reg, mask,
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BCM54140_HWMON_FROM_TEMP(val));
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}
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static int bcm54140_hwmon_write_in(struct device *dev, u32 attr,
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int channel, long val)
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{
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struct phy_device *phydev = dev_get_drvdata(dev);
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u16 mask = BCM54140_HWMON_IN_MASK(channel);
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u16 reg;
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val = clamp_val(val, 0, BCM54140_HWMON_TO_IN(channel, mask));
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switch (attr) {
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case hwmon_in_min:
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reg = BCM54140_HWMON_IN_MIN_REG(channel);
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break;
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case hwmon_in_max:
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reg = BCM54140_HWMON_IN_MAX_REG(channel);
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break;
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default:
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return -EOPNOTSUPP;
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}
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return bcm_phy_modify_rdb(phydev, reg, mask,
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BCM54140_HWMON_FROM_IN(channel, val));
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}
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static int bcm54140_hwmon_write(struct device *dev,
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enum hwmon_sensor_types type, u32 attr,
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int channel, long val)
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{
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switch (type) {
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case hwmon_temp:
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return bcm54140_hwmon_write_temp(dev, attr, channel, val);
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case hwmon_in:
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return bcm54140_hwmon_write_in(dev, attr, channel, val);
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default:
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return -EOPNOTSUPP;
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}
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}
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static const struct hwmon_channel_info *bcm54140_hwmon_info[] = {
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HWMON_CHANNEL_INFO(temp,
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HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
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HWMON_T_ALARM),
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HWMON_CHANNEL_INFO(in,
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HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
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HWMON_I_ALARM | HWMON_I_LABEL,
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HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
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HWMON_I_ALARM | HWMON_I_LABEL),
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NULL
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};
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static const struct hwmon_ops bcm54140_hwmon_ops = {
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.is_visible = bcm54140_hwmon_is_visible,
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.read = bcm54140_hwmon_read,
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.read_string = bcm54140_hwmon_read_string,
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.write = bcm54140_hwmon_write,
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};
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static const struct hwmon_chip_info bcm54140_chip_info = {
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.ops = &bcm54140_hwmon_ops,
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.info = bcm54140_hwmon_info,
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};
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static int bcm54140_enable_monitoring(struct phy_device *phydev)
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{
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u16 mask, set;
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/* 3.3V voltage mode */
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set = BCM54140_RDB_MON_CTRL_V_MODE;
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/* select round-robin */
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mask = BCM54140_RDB_MON_CTRL_SEL_MASK;
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set |= FIELD_PREP(BCM54140_RDB_MON_CTRL_SEL_MASK,
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BCM54140_RDB_MON_CTRL_SEL_RR);
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/* remove power-down bit */
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mask |= BCM54140_RDB_MON_CTRL_PWR_DOWN;
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return bcm_phy_modify_rdb(phydev, BCM54140_RDB_MON_CTRL, mask, set);
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}
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static int bcm54140_probe_once(struct phy_device *phydev)
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{
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struct device *hwmon;
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int ret;
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/* enable hardware monitoring */
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ret = bcm54140_enable_monitoring(phydev);
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if (ret)
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return ret;
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hwmon = devm_hwmon_device_register_with_info(&phydev->mdio.dev,
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"BCM54140", phydev,
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&bcm54140_chip_info,
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NULL);
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return PTR_ERR_OR_ZERO(hwmon);
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}
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#endif
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static int bcm54140_base_read_rdb(struct phy_device *phydev, u16 rdb)
|
|
{
|
|
int ret;
|
|
|
|
phy_lock_mdio_bus(phydev);
|
|
ret = __phy_package_write(phydev, MII_BCM54XX_RDB_ADDR, rdb);
|
|
if (ret < 0)
|
|
goto out;
|
|
|
|
ret = __phy_package_read(phydev, MII_BCM54XX_RDB_DATA);
|
|
|
|
out:
|
|
phy_unlock_mdio_bus(phydev);
|
|
return ret;
|
|
}
|
|
|
|
static int bcm54140_base_write_rdb(struct phy_device *phydev,
|
|
u16 rdb, u16 val)
|
|
{
|
|
int ret;
|
|
|
|
phy_lock_mdio_bus(phydev);
|
|
ret = __phy_package_write(phydev, MII_BCM54XX_RDB_ADDR, rdb);
|
|
if (ret < 0)
|
|
goto out;
|
|
|
|
ret = __phy_package_write(phydev, MII_BCM54XX_RDB_DATA, val);
|
|
|
|
out:
|
|
phy_unlock_mdio_bus(phydev);
|
|
return ret;
|
|
}
|
|
|
|
/* Under some circumstances a core PLL may not lock, this will then prevent
|
|
* a successful link establishment. Restart the PLL after the voltages are
|
|
* stable to workaround this issue.
|
|
*/
|
|
static int bcm54140_b0_workaround(struct phy_device *phydev)
|
|
{
|
|
int spare3;
|
|
int ret;
|
|
|
|
spare3 = bcm_phy_read_rdb(phydev, BCM54140_RDB_SPARE3);
|
|
if (spare3 < 0)
|
|
return spare3;
|
|
|
|
spare3 &= ~BCM54140_RDB_SPARE3_BIT0;
|
|
|
|
ret = bcm_phy_write_rdb(phydev, BCM54140_RDB_SPARE3, spare3);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = phy_modify(phydev, MII_BMCR, 0, BMCR_PDOWN);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = phy_modify(phydev, MII_BMCR, BMCR_PDOWN, 0);
|
|
if (ret)
|
|
return ret;
|
|
|
|
spare3 |= BCM54140_RDB_SPARE3_BIT0;
|
|
|
|
return bcm_phy_write_rdb(phydev, BCM54140_RDB_SPARE3, spare3);
|
|
}
|
|
|
|
/* The BCM54140 is a quad PHY where only the first port has access to the
|
|
* global register. Thus we need to find out its PHY address.
|
|
*
|
|
*/
|
|
static int bcm54140_get_base_addr_and_port(struct phy_device *phydev)
|
|
{
|
|
struct bcm54140_priv *priv = phydev->priv;
|
|
struct mii_bus *bus = phydev->mdio.bus;
|
|
int addr, min_addr, max_addr;
|
|
int step = 1;
|
|
u32 phy_id;
|
|
int tmp;
|
|
|
|
min_addr = phydev->mdio.addr;
|
|
max_addr = phydev->mdio.addr;
|
|
addr = phydev->mdio.addr;
|
|
|
|
/* We scan forward and backwards and look for PHYs which have the
|
|
* same phy_id like we do. Step 1 will scan forward, step 2
|
|
* backwards. Once we are finished, we have a min_addr and
|
|
* max_addr which resembles the range of PHY addresses of the same
|
|
* type of PHY. There is one caveat; there may be many PHYs of
|
|
* the same type, but we know that each PHY takes exactly 4
|
|
* consecutive addresses. Therefore we can deduce our offset
|
|
* to the base address of this quad PHY.
|
|
*/
|
|
|
|
while (1) {
|
|
if (step == 3) {
|
|
break;
|
|
} else if (step == 1) {
|
|
max_addr = addr;
|
|
addr++;
|
|
} else {
|
|
min_addr = addr;
|
|
addr--;
|
|
}
|
|
|
|
if (addr < 0 || addr >= PHY_MAX_ADDR) {
|
|
addr = phydev->mdio.addr;
|
|
step++;
|
|
continue;
|
|
}
|
|
|
|
/* read the PHY id */
|
|
tmp = mdiobus_read(bus, addr, MII_PHYSID1);
|
|
if (tmp < 0)
|
|
return tmp;
|
|
phy_id = tmp << 16;
|
|
tmp = mdiobus_read(bus, addr, MII_PHYSID2);
|
|
if (tmp < 0)
|
|
return tmp;
|
|
phy_id |= tmp;
|
|
|
|
/* see if it is still the same PHY */
|
|
if ((phy_id & phydev->drv->phy_id_mask) !=
|
|
(phydev->drv->phy_id & phydev->drv->phy_id_mask)) {
|
|
addr = phydev->mdio.addr;
|
|
step++;
|
|
}
|
|
}
|
|
|
|
/* The range we get should be a multiple of four. Please note that both
|
|
* the min_addr and max_addr are inclusive. So we have to add one if we
|
|
* subtract them.
|
|
*/
|
|
if ((max_addr - min_addr + 1) % 4) {
|
|
dev_err(&phydev->mdio.dev,
|
|
"Detected Quad PHY IDs %d..%d doesn't make sense.\n",
|
|
min_addr, max_addr);
|
|
return -EINVAL;
|
|
}
|
|
|
|
priv->port = (phydev->mdio.addr - min_addr) % 4;
|
|
priv->base_addr = phydev->mdio.addr - priv->port;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int bcm54140_probe(struct phy_device *phydev)
|
|
{
|
|
struct bcm54140_priv *priv;
|
|
int ret;
|
|
|
|
priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
phydev->priv = priv;
|
|
|
|
ret = bcm54140_get_base_addr_and_port(phydev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
devm_phy_package_join(&phydev->mdio.dev, phydev, priv->base_addr, 0);
|
|
|
|
#if IS_ENABLED(CONFIG_HWMON)
|
|
mutex_init(&priv->alarm_lock);
|
|
|
|
if (phy_package_init_once(phydev)) {
|
|
ret = bcm54140_probe_once(phydev);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
phydev_dbg(phydev, "probed (port %d, base PHY address %d)\n",
|
|
priv->port, priv->base_addr);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int bcm54140_config_init(struct phy_device *phydev)
|
|
{
|
|
u16 reg = 0xffff;
|
|
int ret;
|
|
|
|
/* Apply hardware errata */
|
|
if (BCM54140_PHY_ID_REV(phydev->phy_id) == BCM54140_REV_B0) {
|
|
ret = bcm54140_b0_workaround(phydev);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
/* Unmask events we are interested in. */
|
|
reg &= ~(BCM54140_RDB_INT_DUPLEX |
|
|
BCM54140_RDB_INT_SPEED |
|
|
BCM54140_RDB_INT_LINK);
|
|
ret = bcm_phy_write_rdb(phydev, BCM54140_RDB_IMR, reg);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* LED1=LINKSPD[1], LED2=LINKSPD[2], LED3=LINK/ACTIVITY */
|
|
ret = bcm_phy_modify_rdb(phydev, BCM54140_RDB_SPARE1,
|
|
0, BCM54140_RDB_SPARE1_LSLM);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = bcm_phy_modify_rdb(phydev, BCM54140_RDB_LED_CTRL,
|
|
0, BCM54140_RDB_LED_CTRL_ACTLINK0);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* disable super isolate mode */
|
|
return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_PWR,
|
|
BCM54140_RDB_C_PWR_ISOLATE, 0);
|
|
}
|
|
|
|
static irqreturn_t bcm54140_handle_interrupt(struct phy_device *phydev)
|
|
{
|
|
int irq_status, irq_mask;
|
|
|
|
irq_status = bcm_phy_read_rdb(phydev, BCM54140_RDB_ISR);
|
|
if (irq_status < 0) {
|
|
phy_error(phydev);
|
|
return IRQ_NONE;
|
|
}
|
|
|
|
irq_mask = bcm_phy_read_rdb(phydev, BCM54140_RDB_IMR);
|
|
if (irq_mask < 0) {
|
|
phy_error(phydev);
|
|
return IRQ_NONE;
|
|
}
|
|
irq_mask = ~irq_mask;
|
|
|
|
if (!(irq_status & irq_mask))
|
|
return IRQ_NONE;
|
|
|
|
phy_trigger_machine(phydev);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int bcm54140_ack_intr(struct phy_device *phydev)
|
|
{
|
|
int reg;
|
|
|
|
/* clear pending interrupts */
|
|
reg = bcm_phy_read_rdb(phydev, BCM54140_RDB_ISR);
|
|
if (reg < 0)
|
|
return reg;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int bcm54140_config_intr(struct phy_device *phydev)
|
|
{
|
|
struct bcm54140_priv *priv = phydev->priv;
|
|
static const u16 port_to_imr_bit[] = {
|
|
BCM54140_RDB_TOP_IMR_PORT0, BCM54140_RDB_TOP_IMR_PORT1,
|
|
BCM54140_RDB_TOP_IMR_PORT2, BCM54140_RDB_TOP_IMR_PORT3,
|
|
};
|
|
int reg, err;
|
|
|
|
if (priv->port >= ARRAY_SIZE(port_to_imr_bit))
|
|
return -EINVAL;
|
|
|
|
reg = bcm54140_base_read_rdb(phydev, BCM54140_RDB_TOP_IMR);
|
|
if (reg < 0)
|
|
return reg;
|
|
|
|
if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
|
|
err = bcm54140_ack_intr(phydev);
|
|
if (err)
|
|
return err;
|
|
|
|
reg &= ~port_to_imr_bit[priv->port];
|
|
err = bcm54140_base_write_rdb(phydev, BCM54140_RDB_TOP_IMR, reg);
|
|
} else {
|
|
reg |= port_to_imr_bit[priv->port];
|
|
err = bcm54140_base_write_rdb(phydev, BCM54140_RDB_TOP_IMR, reg);
|
|
if (err)
|
|
return err;
|
|
|
|
err = bcm54140_ack_intr(phydev);
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
static int bcm54140_get_downshift(struct phy_device *phydev, u8 *data)
|
|
{
|
|
int val;
|
|
|
|
val = bcm_phy_read_rdb(phydev, BCM54140_RDB_C_MISC_CTRL);
|
|
if (val < 0)
|
|
return val;
|
|
|
|
if (!(val & BCM54140_RDB_C_MISC_CTRL_WS_EN)) {
|
|
*data = DOWNSHIFT_DEV_DISABLE;
|
|
return 0;
|
|
}
|
|
|
|
val = bcm_phy_read_rdb(phydev, BCM54140_RDB_SPARE2);
|
|
if (val < 0)
|
|
return val;
|
|
|
|
if (val & BCM54140_RDB_SPARE2_WS_RTRY_DIS)
|
|
*data = 1;
|
|
else
|
|
*data = FIELD_GET(BCM54140_RDB_SPARE2_WS_RTRY_LIMIT, val) + 2;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int bcm54140_set_downshift(struct phy_device *phydev, u8 cnt)
|
|
{
|
|
u16 mask, set;
|
|
int ret;
|
|
|
|
if (cnt > BCM54140_MAX_DOWNSHIFT && cnt != DOWNSHIFT_DEV_DEFAULT_COUNT)
|
|
return -EINVAL;
|
|
|
|
if (!cnt)
|
|
return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_MISC_CTRL,
|
|
BCM54140_RDB_C_MISC_CTRL_WS_EN, 0);
|
|
|
|
if (cnt == DOWNSHIFT_DEV_DEFAULT_COUNT)
|
|
cnt = BCM54140_DEFAULT_DOWNSHIFT;
|
|
|
|
if (cnt == 1) {
|
|
mask = 0;
|
|
set = BCM54140_RDB_SPARE2_WS_RTRY_DIS;
|
|
} else {
|
|
mask = BCM54140_RDB_SPARE2_WS_RTRY_DIS;
|
|
mask |= BCM54140_RDB_SPARE2_WS_RTRY_LIMIT;
|
|
set = FIELD_PREP(BCM54140_RDB_SPARE2_WS_RTRY_LIMIT, cnt - 2);
|
|
}
|
|
ret = bcm_phy_modify_rdb(phydev, BCM54140_RDB_SPARE2,
|
|
mask, set);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_MISC_CTRL,
|
|
0, BCM54140_RDB_C_MISC_CTRL_WS_EN);
|
|
}
|
|
|
|
static int bcm54140_get_edpd(struct phy_device *phydev, u16 *tx_interval)
|
|
{
|
|
int val;
|
|
|
|
val = bcm_phy_read_rdb(phydev, BCM54140_RDB_C_APWR);
|
|
if (val < 0)
|
|
return val;
|
|
|
|
switch (FIELD_GET(BCM54140_RDB_C_APWR_APD_MODE_MASK, val)) {
|
|
case BCM54140_RDB_C_APWR_APD_MODE_DIS:
|
|
case BCM54140_RDB_C_APWR_APD_MODE_DIS2:
|
|
*tx_interval = ETHTOOL_PHY_EDPD_DISABLE;
|
|
break;
|
|
case BCM54140_RDB_C_APWR_APD_MODE_EN:
|
|
case BCM54140_RDB_C_APWR_APD_MODE_EN_ANEG:
|
|
switch (FIELD_GET(BCM54140_RDB_C_APWR_SLP_TIM_MASK, val)) {
|
|
case BCM54140_RDB_C_APWR_SLP_TIM_2_7:
|
|
*tx_interval = 2700;
|
|
break;
|
|
case BCM54140_RDB_C_APWR_SLP_TIM_5_4:
|
|
*tx_interval = 5400;
|
|
break;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int bcm54140_set_edpd(struct phy_device *phydev, u16 tx_interval)
|
|
{
|
|
u16 mask, set;
|
|
|
|
mask = BCM54140_RDB_C_APWR_APD_MODE_MASK;
|
|
if (tx_interval == ETHTOOL_PHY_EDPD_DISABLE)
|
|
set = FIELD_PREP(BCM54140_RDB_C_APWR_APD_MODE_MASK,
|
|
BCM54140_RDB_C_APWR_APD_MODE_DIS);
|
|
else
|
|
set = FIELD_PREP(BCM54140_RDB_C_APWR_APD_MODE_MASK,
|
|
BCM54140_RDB_C_APWR_APD_MODE_EN_ANEG);
|
|
|
|
/* enable single pulse mode */
|
|
set |= BCM54140_RDB_C_APWR_SINGLE_PULSE;
|
|
|
|
/* set sleep timer */
|
|
mask |= BCM54140_RDB_C_APWR_SLP_TIM_MASK;
|
|
switch (tx_interval) {
|
|
case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS:
|
|
case ETHTOOL_PHY_EDPD_DISABLE:
|
|
case 2700:
|
|
set |= BCM54140_RDB_C_APWR_SLP_TIM_2_7;
|
|
break;
|
|
case 5400:
|
|
set |= BCM54140_RDB_C_APWR_SLP_TIM_5_4;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_APWR, mask, set);
|
|
}
|
|
|
|
static int bcm54140_get_tunable(struct phy_device *phydev,
|
|
struct ethtool_tunable *tuna, void *data)
|
|
{
|
|
switch (tuna->id) {
|
|
case ETHTOOL_PHY_DOWNSHIFT:
|
|
return bcm54140_get_downshift(phydev, data);
|
|
case ETHTOOL_PHY_EDPD:
|
|
return bcm54140_get_edpd(phydev, data);
|
|
default:
|
|
return -EOPNOTSUPP;
|
|
}
|
|
}
|
|
|
|
static int bcm54140_set_tunable(struct phy_device *phydev,
|
|
struct ethtool_tunable *tuna, const void *data)
|
|
{
|
|
switch (tuna->id) {
|
|
case ETHTOOL_PHY_DOWNSHIFT:
|
|
return bcm54140_set_downshift(phydev, *(const u8 *)data);
|
|
case ETHTOOL_PHY_EDPD:
|
|
return bcm54140_set_edpd(phydev, *(const u16 *)data);
|
|
default:
|
|
return -EOPNOTSUPP;
|
|
}
|
|
}
|
|
|
|
static struct phy_driver bcm54140_drivers[] = {
|
|
{
|
|
.phy_id = PHY_ID_BCM54140,
|
|
.phy_id_mask = BCM54140_PHY_ID_MASK,
|
|
.name = "Broadcom BCM54140",
|
|
.flags = PHY_POLL_CABLE_TEST,
|
|
.features = PHY_GBIT_FEATURES,
|
|
.config_init = bcm54140_config_init,
|
|
.handle_interrupt = bcm54140_handle_interrupt,
|
|
.config_intr = bcm54140_config_intr,
|
|
.probe = bcm54140_probe,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
.soft_reset = genphy_soft_reset,
|
|
.get_tunable = bcm54140_get_tunable,
|
|
.set_tunable = bcm54140_set_tunable,
|
|
.cable_test_start = bcm_phy_cable_test_start_rdb,
|
|
.cable_test_get_status = bcm_phy_cable_test_get_status_rdb,
|
|
},
|
|
};
|
|
module_phy_driver(bcm54140_drivers);
|
|
|
|
static struct mdio_device_id __maybe_unused bcm54140_tbl[] = {
|
|
{ PHY_ID_BCM54140, BCM54140_PHY_ID_MASK },
|
|
{ }
|
|
};
|
|
|
|
MODULE_AUTHOR("Michael Walle");
|
|
MODULE_DESCRIPTION("Broadcom BCM54140 PHY driver");
|
|
MODULE_DEVICE_TABLE(mdio, bcm54140_tbl);
|
|
MODULE_LICENSE("GPL");
|