WSL2-Linux-Kernel/tools/arch
Adrian Hunter 69db696bdb x86/insn: Fix PUSH instruction in x86 instruction decoder opcode map
[ Upstream commit 59162e0c11d7257cde15f907d19fefe26da66692 ]

The x86 instruction decoder is used not only for decoding kernel
instructions. It is also used by perf uprobes (user space probes) and by
perf tools Intel Processor Trace decoding. Consequently, it needs to
support instructions executed by user space also.

Opcode 0x68 PUSH instruction is currently defined as 64-bit operand size
only i.e. (d64). That was based on Intel SDM Opcode Map. However that is
contradicted by the Instruction Set Reference section for PUSH in the
same manual.

Remove 64-bit operand size only annotation from opcode 0x68 PUSH
instruction.

Example:

  $ cat pushw.s
  .global  _start
  .text
  _start:
          pushw   $0x1234
          mov     $0x1,%eax   # system call number (sys_exit)
          int     $0x80
  $ as -o pushw.o pushw.s
  $ ld -s -o pushw pushw.o
  $ objdump -d pushw | tail -4
  0000000000401000 <.text>:
    401000:       66 68 34 12             pushw  $0x1234
    401004:       b8 01 00 00 00          mov    $0x1,%eax
    401009:       cd 80                   int    $0x80
  $ perf record -e intel_pt//u ./pushw
  [ perf record: Woken up 1 times to write data ]
  [ perf record: Captured and wrote 0.014 MB perf.data ]

 Before:

  $ perf script --insn-trace=disasm
  Warning:
  1 instruction trace errors
           pushw   10349 [000] 10586.869237014:            401000 [unknown] (/home/ahunter/git/misc/rtit-tests/pushw)           pushw $0x1234
           pushw   10349 [000] 10586.869237014:            401006 [unknown] (/home/ahunter/git/misc/rtit-tests/pushw)           addb %al, (%rax)
           pushw   10349 [000] 10586.869237014:            401008 [unknown] (/home/ahunter/git/misc/rtit-tests/pushw)           addb %cl, %ch
           pushw   10349 [000] 10586.869237014:            40100a [unknown] (/home/ahunter/git/misc/rtit-tests/pushw)           addb $0x2e, (%rax)
   instruction trace error type 1 time 10586.869237224 cpu 0 pid 10349 tid 10349 ip 0x40100d code 6: Trace doesn't match instruction

 After:

  $ perf script --insn-trace=disasm
             pushw   10349 [000] 10586.869237014:            401000 [unknown] (./pushw)           pushw $0x1234
             pushw   10349 [000] 10586.869237014:            401004 [unknown] (./pushw)           movl $1, %eax

Fixes: eb13296cfa ("x86: Instruction decoder API")
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/r/20240502105853.5338-3-adrian.hunter@intel.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
2024-06-16 13:39:31 +02:00
..
alpha/include
arc/include/uapi/asm
arm/include
arm64/include tools headers UAPI: Sync files changed by the memfd_secret new syscall 2021-07-14 10:05:35 -03:00
csky/include/uapi/asm
h8300/include
hexagon/include/uapi/asm
ia64/include ia64: tools: remove duplicate definition of ia64_mf() on ia64 2021-04-16 16:10:37 -07:00
microblaze/include/uapi/asm
mips/include perf tools: Copy uapi/asm/perf_regs.h from the kernel for MIPS 2021-06-01 10:07:46 -03:00
parisc/include/uapi/asm parisc: Drop the HP-UX ENOSYM and EREMOTERELEASE error codes 2023-12-08 08:48:02 +01:00
powerpc/include tools include UAPI powerpc: Sync errno.h with the kernel headers 2021-05-10 09:01:00 -03:00
riscv/include/uapi/asm
s390/include tools headers UAPI s390: Sync ptrace.h kernel headers 2021-03-06 16:54:23 -03:00
sh/include
sparc/include
x86 x86/insn: Fix PUSH instruction in x86 instruction decoder opcode map 2024-06-16 13:39:31 +02:00
xtensa/include